Integrated interconnect circuit modeling for VLSI design

Transcription

1 Integrated nterconnect crcut modelng for VLSI desgn Won-Young Jung, Ghun-Up Cha, Young-Bae Km, Jun-Ho Baek, Choon-Kyung Km LG Semcon Co.,Ltd. D.A. Center 16, Woomyeon-dong, Seocho-gu, Seoul, , Korea. Tel:(02) Fax:(02) Abstract - An ntegrated nterconnect modelng system, SIMS, s developed wth the parametrzed modelng of nterconnect and the nterface wth a schematc capture and edtor. SIMS automatcally drves numercal nterconnect smualton as drected by technology engneers, creates polynomal model lbrary for nterconnect parastcs, generates netlst ncludng SPICE model for the nterconnect structure specfed by crcut desgners, automatcally drves crcut smulatons and dsplay the smulaton results through advanced GUI.. VLSI desgn wth SIMS makes t possble to consder parastc effects fast and accurately, whch becomes more mportant n deep submcron crcut desgn area. Wth ths capablty, crcut desgn wth optmzed nterconnect layout can be easly acheved. Ultmately the ntegrated system helps to reduce the cost of technology development and the tme-to-market by buldng up the concept of desgn-formanufacturablty. 2. SYSTEM OVERVIEW The conceptual dagram of the system structure s shown n Fg 1. SIMS s composed of two separate modules, called SIMG and ESCAPE respectvely.[4] SIMG automatcally drves 2D/3D numercal nterconnect smulator accordng to the nterconnect structure descrptons nput by the technology engneers and generates nterconnect model lbrary. ESCAPE s the n-house schematc capture tool whch, as drected by the types of nterconnect specfed by a desgner, accesses the nterconnect model lbrary generated by SIMG, creates the netlst ncludng nterconnect capactances, drves crcut smulatons and provdes realtme verfcaton of the crcut functonalty affected by nterconnect through advanced GUI. 1.INTRODUCTION As chp densty and crcut swtchng speed are mproved, the parastc effects nduced by the nterconnect has emerged as one of the most crtcal factors n restrctng crcut performances.[1] In order to ensure n-spec desgn, the parastc effects should be taken nto account as accurately and as early n desgn flow as possble. There have been several approaches to accomplsh ths. Earler, smplfed analytcal models were used to estmate nterconnect capactances, whch could not meet the level of accuracy requred by the present VLSI technology.[2] Wth the advent of numercal nterconnect smulator, another approach based on smulaton and extracton of nterconnect capactance was proposed to overcome ths dffculty.[3] However, an accurate nterconnect modelng system whch ams at the enhancement of desgn effcency should be ntegrated wth the exstng desgn methodology. It s the purpose of ths work to provde such an ntegrated desgn envronment, called SIMS(SPICE Interconnect Modelng System), to the desgn communty. In ths paper, the general concept and the structure of the system SIMS and the capactance modelng whch makes the embodment of the system posslbe wll be presented. Fg.1 The concept of SIMS(SPICE Interconnect Modelng System)

2 3. SIMG(SPICE Interconnect Model Generator) As seen n Fg.1, SIMG conssts of 4 submodules of PARSER, smulaton drver, parastcs extractor and ftter/generator. Parser takes the nput deck, reads n data from SIL to create the smulaton nput and structure, and sends ths nformaton to smulaton drver. Then, the smulaton drver ntates numercal nterconnect smulatons to calculate the parastcs as functons of layout parameters. The parastc extractor extracts the parastcs from the smulaton results and stores them nto the parastc database. Fnally, the ftter/generator creates nterconnect model lbrary based on least square ft. The automatc realtme verfcaton s mplemented to examne the accuracy of the model for arbtrary desgn parameters. SIMG creates data lbrary for smulaton nputs and nterconnect structures for the ease of use and lbrary management as technology changes. Not only the layout parameters lke nterconnect lne wdth, length and spacng but also the technology parameters such as materal constants, layer thcknesses and resstvtes can be assgned n the nput fle. Also the herarchy and the objectvty of the nput data allow the model lbrary manager to mantan structured database. The system envronment can be set ether by UNIX shell varables or by setup fles for mproved mantenance of the system. 4.PARAMETRIZATION OF THE INTER CONNECT STRUCTURE SIMG performs the numercal smulatons varyng the layout parameters after t reads n the parametrzed nterconnect structure template fle. The parametrzaton of the nterconnect structure s performed by the smulator s keyword ".param as followng ; technology parameter values n the smulaton. 6. INTERCONNECT CAPACITANCE MODELING A. Parametrzaton of parastc capactance The nterconnects used n IC chps can be approxmately descrbed as the array of nterconnects whch are placed parallel to each other above the ground plane as shown n Fg. 2. The capactance of each nterconnect n ths array s represented by the sum of all capactances wth other nterconnects as well as that wth the ground plane. However as the smulated capactance matrx shows n Fg.2, the contrbuton n capactance from other nterconnects s orders of magntude smaller than that from the two nearestneghbor nterconnects, and hence can be neglected. From ths observaton, the capactance of each nterconnect can be gven by: C nner = C g + 2*C (1.1) C edge = C g + C (1.2) where C nner and C edge are the capactances of nterconnect placed nsde and at the edge of the array respectvely, and Cg and C are the capactances of each nterconnect wth the ground plane(called ground capactance) and wth one of ts nearest neghbors(called couplng capactance), respectvely. The parameters whch affect nterconnect capactances can be grouped nto the technology parameters and layout parameters. Technology parameters such as layer thcknesses and resstvtes, delectrc constant can be consdered fxed and cannot be changed for optmzaton by desgners once.param parameter name1 = parameter value1;.param parameter name2 = parameter value2; : SIMS searches for the name of the parameter declared n the nput deck among nterconnect template structure fles, and transforms the value of the parameter. The structure fle translated as such s fed nto the smulator as an nput fle for smulaton. 5. PARASITICS DATABASE To generate models for an nterconnect structure, tens or hundreds of numercal smulatons have to be performed each of whch could take several mnutes. Therefore, when an unexpected accdent takes place or when model optons have to be changed durng smulaton, a large amount of tme wll be requred for redong smulatons. SIMS has the bult-n parastcs database for storng and fetchng out the parastc values for the same layout and/or Fg.2 The result of smulaton of couplng capactance between wre and other wre when fve parallel metal strp lnes run groundplane

3 the technology process specfcatons are defned. On the other hand, layout parameters are flexble to be optmzed for performance. Therefore n a gven process, the nterconnect capactance can be descrbed as a functon of layout parameters. C=f(layout parameters, tech. parameters=const.) (2.1) C=f(layout parameters) when technology parameters are fxed (2.2) From the analyss of smulaton results for nterconnect capactance, t s found that the nterconnect capactance s lnearly proportonal to the lne length, and to the lne wdth provded that the wdth s not too small. A strong nonlnearty n the dependence on wdth shows up for small wdth and also on spacng for all the range of lne spacng. From the above results, the nterconnect capactance can be expressed as a functon of layout parameters as follows: (a) Fg.3 (a) The dependence of couplng capactance on the wdth of the wre n gven range of space (b) The functon, F s(w), dependng on the space (b) C(L,S,W) =L*C s,w (S,W) (3) C s,w (S,W)=C w0 (S)+F s (W){C w1 (S)-C w0 (S)} (4) where C w0 (S) and C w1 (S) are the capactances per unt length at the mnmum wdth of W 0 and at the maxmum wdth of W1 n the wdth range, respectvely. F s (W) becomes (W- W 0 )/(W 1 -W 0 ) for W c <W 0 <W<W 1 where W c s the crtcal wdth below whch the non-lnearty shows up. In case the capactance s not lnearly proportonal to the nterconnect wdth, the capactances for S=S 1, S=S 2, S= S 3,..., and S= S n a gven range(s mn,s max ) can be expressed as follows: C s=s1,w (W)=C w0 (S1)+F s1 (W)*{C w1 (S 1 )-C w0 (S 1 )} (6.1) C s=s2,w (W)=C w0 (S2)+F s1 (W)*{C w1 (S 2 )-C w0 (S 2 )} (6.2) C s=s3,w (W)=C w0 (S3)+F s1 (W)*{C w1 (S 3 )-C w0 (S 3 )} (6.3) : C s=s,w (W)=C w0 (S)+F s1 (W)*{C w1 (S )-C w0 (S )} (6.4) In ths case, Fs(W) are nonlnear functons of W whose value ranges from 0 to 1. It s shown n Fg. 3,4 that Fs1(W), Fs2(W),..., and Fs(W) can be represented by the generalzed functon, Fs(W). In SIMS, Cw(S) and Fs(W) are represented by the n-th order polynomal as followng: C ( S) = A S W n = 0 F ( W) = A W S n= 0 and ther coeffcents can be easly obtaned by least square ft. By adopng polynomal-based capactance model for nterconnect, the need for repetton of tme-consumng numercal smulatons are elmnated once the modelbrarys (7) (8) (a) Fg.4 (a) The dependence of ground capactance on the wdth of the wre n gven range of space (b) The functon, F s(s), dependng on the space generated, leadng to a capablty of fast and accurate estmaton of nterconnect capactances. B.Parametrzaton of parastc nductance The parastc nductances n IC chps can be parametrzed and modeled n the same way as descrbed n the prevous secton. The nductance of an nterconnect lne s composed of the self nductance(l s ) nduced by tself and the mutual nductance (L m ) nduced by the neghborng nterconnects. These nductances can be descrbed as a functon of layout parameters and technology parameters as well. In the nterconnect smulator used n the study, RAPHAEL, the nductance s calculated as follows:[5][6] [] L [ ] = 1 1 c C where [L] s nductance matrx, [C] s capactance matrx and c s the speed of lght. As found n the analyss of smulaton result for nterconnect capactance, t s found that the nterconnect (b) (9)

4 Fg.5 The fttng result for capactance usng SIMS (RAPHAEL vs SIMS) nductance s lnearly proportonal to the lne length, but strongly nonlnear wth lne wdth and spacng. Therefore, bascally the same methodology of developng analytc models as for nterconnect capactances s employed for nterconnect nductances. 7. SIMULATION AND CURVE FITTING Model lbrary for parastcs s generated for each range of Fg.6 The fttng results for nductance usng SIMS(RAPHAEL vs SIMS) layout parameters usng least square ft. A specal care s taken for polynomal representaton of strong nonlnear functons. It s seen n Fg.5, 6 that an excellent accuracy of model s obtaned compared to the smulaton results. Dvdng the spacng range nto 3 subregons and the wdth range nto 2 subregons results n the maxmum fttng error less than 3%. 8.WIRE MODELING IN THE SCHEMATIC CAPTURE TOOL

5 Once the model lbrary for nterconnect parastcs s generated, crcut desgners can access the lbrary through the schematc capture tool n SIMS, whch n turn creates netlst ncludng the SPICE model for a partcular nterconnect pattern specfed by the desgner, automatcally drves crcut smulator and dsplay the crcut performance results through GUI. The desgner, therefore, can analyze the effects of varous nterconnect patterns on hs/her crcuts n a very fast and accurate manner. Moreover, cross-talk can be smulated n the ntegrated modelng system by assgnng separate ground nodes for dfferent nterconnect lnes. 9. CONCLUSION In ths paper, an ntegrated desgn envronment, SIMS, and related parameterzed modelng of nterconnect capactances and nductances are presented. SIMS ntegrates numercal nterconnect smulaton wth crcut smulaton through a schematc capture tool. It not only preserves the accuracy of numercal smulatons but also speed up the analyss by adoptng parametrzed parastcs modelng method based on nterconnect smulatons of varous nterconnect structures, openng wde the door to the desgn of crcut wth optmzed nterconnect layout. Through the nterface wth a schematc capture tool, SIMS can smulate the effects of nterconnect parastcs on crcut performances easly. The delay due to nterconnect n IC chps has emerged as one of the most crtcal factors n determnng performances, and n ths context, the capablty of fast and accurate nterconnect modelng and analyss provded by SIMS wll ultmately make an mportant contrbuton to the realzaton of the concept of desgn for manufacturablty and to the sgnfcant reducton n tme-to-market for the beneft of desgn communty. REFERENCES [1]H. B. Bakoglu, Crcut, Interconnectons, and Packagng for VLSI, Addson Wesley, [2]Peter E. Cottrell, Edward M. Buturla, "VLSI Wrng Capactance,"IBM J. Res.Develop.,pp , May, [3]Keh-Jeng Chang,Soo-Young Oh, Ken Lee,"HIVE: An effcent nterconnect capactance extractor to support submcron multlevel nterconnect desgn," Proceedngs of IEEE ICCAD,pp ,Nov.,1991. [4]Y.S. Hong, J.J. Cho, Y..B. Km, and C.K. Km, "An Extended Schematc CAPture System: ESCAPE," Ajont Conf. on Electronc Materal, semconductor, and CAD,KIEE,1990. [5]TMA,Inc.,RAPHAEL User's Manual Verson2.2, TMA,Inc.,Palo Alto, CA, [6]Cao we, Roger F. Harrngton, Joseph R. Mautz, Tapan K.Sarkar, Multconductor Transmsson Lnes n Mult-layered Delectrc Meda, IEEE Transactons on mcrowave Theory and Technques, Vol.32, No.4, pp439~ 450, Aprl, 1984 [7]Won-Young Jung, Ghun-Up Cha, Young-Bae Km, Jun-Ho Baek, Choon- Kyung Km, " SIMS (SPICE Interconnect Modelng System) for VLSI desgn," KOREA semconductor conference proceedngs, 1994.