Computer Graphics. Hardware Pipeline. Visual Imaging in the Electronic Age Prof. Donald P. Greenberg October 23, 2014 Lecture 16

Transcription

1 Computer Graphics Hardware Pipeline Visual Imaging in the Electronic Age Prof. Donald P. Greenberg October 23, 2014 Lecture 16

2 Moore s Law Chip density doubles every 18 months. Processing Power (P) in 15 years: P = P today 2 15years months = P t = P t 2 10 = 1000P t

3 Ivan Sutherland

4 Program of Computer Graphics, Cornell University General Electric

5 Program of Computer Graphics, Cornell University DPG

6 Cornell in Perspective Film Program of Computer Graphics, Cornell University

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8 Direct Model Illumination Camera Perspective Raster Operations Image Storage Display

9 Model Environment Geometry & topology Material properties Color, reflectance, textures (Cost, strength, thermal properties) Lighting Geometry & position Intensity, spectral distribution Direction, spatial distribution Model Camera Perspective Raster Operations Image Storage Display

10 Camera Model Viewer Position Viewer direction Field of view Wide angle Telephoto Depth of focus Near Far Camera Perspective Raster Operations Image Storage Display

11 Eye Coordinate System Z Y e X e Z e X Y

12 Perspective Model Transformation Perspective transformation Matrix multiplication Clipping Culling Camera Perspective Raster Operations Image Storage Display

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14 Hidden Line Algorithm

15 Hidden Line Algorithm

16 Mapping a Viewing Frustum to a Standard Viewbox Z e Y e Y s Z s X s X e z e = D Frustum of vision z e = F Screen coordinate system Donald P. Greenberg - Cornell Program of Computer Graphics

17 Perspective Projections in Computer Graphics Eye coordinate system Plan or elevation view

18 Object Space (One point perspective)

19 Image Space (One point perspective)

20 Raster Model Operations Conversion from polygons to pixels Hidden surface removal (z-buffer) Incremental shading Camera Perspective Raster Operations Image Storage Display

21 Visible Surface Algorithm Z-Buffer Algorithm 1. Set depth(x, y) = 1.0 intensity(x,y) = background color 2. For each polygon, find all pixels covered 3. Calculate z(x,y) of each pixel covered by the polygon 4. If z(x,y) < depth(x,y), polygon is closer set depth(x,y) = z(x,y) change color

22 Depth Buffer Algorithm

23 Depth Buffer Algorithm

24 Phong Reflection Model

25 Image Storage Model Typical frame buffer 1280 x 1024 pixels 3 channels (red, green, blue) 1 byte/channel Total memory 3 3/4 megabytes - single buffer 7 1/2 megabytes - double buffer Camera Perspective Raster Operations Image Storage Display

26 Model Display Digital to analog conversion 1920 x 1080 resolution 60 frames per second Total data rate 2 million pixels x 3 bytes/pixel x 60 frames/second = 360 megabytes/second Camera Perspective Raster Operations Image Storage Display

27 Refresh vs. Update Rate The refresh rate is the number of times per second the entire image is drawn The update rate is the number of times per second the image is changed

28 Direct Model Illumination User Input Camera Perspective Raster Operations Image Storage Display

29 Why a Pipeline? A pipeline allows multiple processes to occur in parallel. Example: An automobile assembly line. Assume 4 stations, each taking 2 minutes to do its task. It takes 8 minutes to make a car, but the rate at which cars are made is one every 2 minutes.

30 Automobile takes 8 minutes to make, but the assembly line makes a car every two minutes. Build frame Add engine Add windows Paint body 2 minutes 2 minutes 2 minutes 2 minutes Stage 1 Stage 2 Stage 3 Stage 4 A B C D E A B C D A B C A B Time (minutes) Donald P. Greenberg - Cornell Program of Computer Graphics

31 Graphics Hardware circa 1970 Model P-xform Clipping Lighting Rasterize System Memory (16 scanlines) Film Recorder CPU System used to generate Phong goblet

32 Graphics Hardware circa 1975 Model P-xform Clipping Lighting Rasterize Frame Buffer Display CPU Graphics Hardware Cost of Memory Prohibitive 512x480x8 bit frame buffer cost $80,000! No z-buffer (at 24 or 32 bits/pixel, it requires even more memory than FB) Only single frame buffer all work done in CPU until frame buffer(slow!)

33 Graphics Hardware circa 1986 Model Lighting P-xform Clipping Rasterize Z-Buffer Frame Frame Buffer Buffer Display CPU Graphics Hardware Added Z-Buffer Added Double Frame Buffer Rasterization performed in hardware

34 Graphics Hardware 1999 Model Texture Frame Lighting P-xform Rasterize Z-Buffer Clipping Mapping Frame Buffer Display Buffer CPU Graphics Hardware Addition of texture mapping units With texturing, high resolution detail is possible with relatively simple geometry

35 Multitexturing Hardware architectures now support accessing more than one texture in a single pass

36 Multipass Example: Light Maps Two separate textures, one for the material s composition, one for the lighting X = J.L.Mitchell, M. Tatro, and I. Bullard

37 Castle s Geometry Agata & Andrzej Wojaczek, Advanced Graphics Applications Inc.

38 Reflection Example - Castle Agata & Andrzej Wojaczek, Advanced Graphics Applications Inc.

39 Putting it all together Gloss textures on pear, shadows on curved surfaces, reflections dropping off with depth from table. J.L. Mitchell & E. Hart, ATI Technologies, Inc.

40 Graphics Pipeline s M L P S D V M Model L Lighting P Perspective/Clipping S Scan Conversion/Z-buffer D Display Storage V Video Donald P. Greenberg - Cornell Program of Computer Graphics

41 Graphics Pipeline M L P T S D V M Model L Lighting P Perspective/Clipping T Texturing S Scan Conversion/Z-buffer D Display Storage V Video Donald P. Greenberg - Cornell Program of Computer Graphics

42 Graphics Hardware 2003 Model Vertex Buffer Lighting Vertex Operations P-xform Clipping Texture Mapping CPU Rasterize Z-Buffer Pixel Operations Frame Frame Buffer Buffer Display Early GPU s performed lighting and clipping operations on locally stored model

43 Graphics Hardware Model Graphics Processing Unit GPU Texture Mapping CPU Rasterize Z-Buffer Pixel Operations Frame Frame Buffer Buffer Display

44 Graphics Hardware 2009 CPU Model Graphics Processing Unit GPU Rasterize Z-Buffer CPU Model CPU Model Graphics Processing Unit GPU Graphics Processing Unit GPU Rasterize Rasterize Z-Buffer Z-Buffer Frame Buffer Display CPU Model Graphics Processing Unit GPU Rasterize Z-Buffer

45 Interesting Trends Moore s Law is approximately 1.7x increase in speed a year; graphics accelerators are improving at 2x to 4x a year Reducing energy (watts) is more important than increasing processing speed (flops)

46 Faster than Moore s Law 10 9 One-pixel polygons (~10M 30Hz) nvidia G Peak Performance ( 's/sec) UNC Pxpl4 HP CRX 10 4 Flat shading SGI Iris HP VRX SGI GT Slope ~2.4x/year (Moore's Law ~ 1.7x/year) UNC Pxpl5 SGI SkyWriter SGI VGX HP TVRX Stellar GS1000 Gouraud shading SGI RE1 E&S F Year SGI RE2 Antialiasing UNC/HP PixelFlow SGI IR ATI SGI Radeon 256 R-Monster E&S Nvidia TNT GeForce Division 3DLabs Harmony SGI Pxpl6 Glint Cobalt Accel/VSIS Voodoo Megatek E&S Freedom Textures Division VPX PC Graphics Graph courtesy of Professor John Poulton (from Eric Haines)

47 Millions of transistors GeForce Transistor Count and Semiconductor Process Riva ZX Riva TNT2 GeForce2 GTS GeForce3 GeForce4 Ti 4600 GeForce FX GeForce 6800 Ultra Process (µm) GeForce 7800 GTX

48 NVIDIA s GK110 Kepler Chip billion transistors 2880 processor cores 28 nanometers PCI Express Gen3

49 Intel Integrated Graphics 2013

50 AMD Integrated Graphics 2014 Kaveri 28 nm 47% GPU 47% GPU

51 Nvidia s Maxwell Architecture

52 Nvidia s Maxwell Architecture Maxwell was designed in modular fashion so that components can be used in mobile applications

53 End...