Monday Morning. Graphics Hardware

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1 Monday Morning Department of Computer Engineering Graphics Hardware Ulf Assarsson

2 Skärmen består av massa pixlar

3 3D-Rendering Objects are often made of triangles x,y,z- coordinate for each vertex Y X Z

4 State-of-the-Art Real-Time Rendering 2001 Department of Computer Engineering

5 Y State-of-the-Art Department of Computer Engineering Real-Time Rendering X 2001 Z

6 Textures One application of texturing is to glue images onto geometrical object + =

7 Texturing: Glue images onto geometrical objects Purpose: more realism, and this is a cheap way to do it + =

8 Ljusberäkning per triangelhörn light blue Rasterizer Geometry red green

9 Environment mapping Department of Computer Engineering

10 Sphere map example Sphere map (texture) Sphere map applied on torus

11 Bump mapping by Blinn in 1978 Inexpensive way of simulating wrinkles and bumps on geometry Too expensive to model these geometrically geometry + = Bump map Stores heights: can derive normals Bump mapped geometry

12 Bump mapping: example

13 Partikelsystem Department of Computer Engineering Particles

14 Partikelsystem Department of Computer Engineering

15 Shadows More realism and atmosphere Department of Computer Engineering Neverwinter Nights Image courtesy of BioWare

16 Fragment shader example Leather float specrolloffedge = pow( (1.0 - VdH), 3.0); float rolloff = specrolloffedge + (1.0 - specrolloffedge) * specularrolloff; color C = LightColor * Ecc * Gain * rolloff;

17 What is vertex and fragment (pixel) shaders? Memory: Texture memory (read + write) typically Mb Program size: 64, 1024 or unlimited instructions Instructions: mul, rcp, mov,dp, rsq, exp, log, cmp, jnz 32 bits processors, usually SIMD

18 PixelShader 2.0 Only floats Instructions operate on 1,2,3 or 4 components x,y,z,w or r,g,b,a Free Swizzling

19 Cg - C for Graphics (NVIDIA)

20 20 Background: Graphics hardware architectures Evolution of graphics hardware has started from the end of the pipeline Rasterizer was put into hardware first (most performance to gain from this) Then the geometry stage Application will not be put into hardware! Two major ways of getting better performance: Pipelining Parallellization Combinations of these are often used

21 Stages Geometry - per vertex: Lighting (colors) Screen space positions light Geometry blue red green Rasterizer Rasterizer Rasterization & Per pixel: Textures Interpolated colors 21

22 Briefly about Graphics HW pipelining 22 In GeForce3: pipeline stages! 57 million transistors Pentium IV: 20 stages, 42 million transistors Newer cards: Radeon 9800: ~110M transistors GeForce FX 5800: 125 M transistors, 500 MHz GeForce 6800: 222 M transistors, 400 MHz Ideally: n stages n times throughput But latency is high (may also increase)! However, not a problem here Chip runs at about 200 MHz (5ns per clock) 5ns*700=3.5 µs We got about 20 ms per frame (50 frames per second) Graphics hardware is simpler to pipeline because: Pixels are (most often) independent of each other Few branches and much fixed functionality Don t need high clock freq: bandwidth to memory is bottleneck This is changing with increased programmability Simpler to predict memory access pattern (do prefecthing!)

23 Parallellism Simple idea: compute n results in parallel, then combine results GeForce FX 5800: 8 pixels/clock, 16 textures/clock With a pipeline of several 100 stages, there are many pixels being processed simultaneously Not always simple! Try to parallelize a sorting algorithm But pixels are independent of each other, so simpler for graphics hardware Can parallellize both geometry and rasterizer: 23

24 Taxonomy of hardware Need to sort from model space to screen space Gives four major architectures: Sort-first Sort-middle Sort-Last Fragment Sort-Last Image Will describe these briefly, and then focus on sort-middle and sort-last fragment (used in commercial hardware) 24

25 Sort-First Sorts primitives before geometry stage Screen in divided into large regions A separate pipeline is responsible for each region (or many) 25 G is geometry, FG & FM is part of rasterizer A fragment is all the generated information for a pixel on a triangle FG is Fragment Generation (finds which pixels are inside triangle) FM is Fragment Merge (merges the created fragments with various buffers (Z, color)) Not explored much at all

26 Sort-Middle 26 Sorts betwen G and R Pretty natural, since after G, we know the screen- space positions of the triangles Most hardware uses this! Examples include InfiniteReality (from SGI) and the KYRO architecture (from Imagination) Spread work arbitrarily among G s Then depending on screen- space position, sort to different R s Screen can be split into tiles. For example: Rectangular blocks (8x8 pixels) Every n scanlines The R is responsible for rendering inside tile A triangle can be sent to many FG s depending on overlap (over tiles)

27 Sort-Last Fragment Sorts betwen FG and FM XBOX uses this! Again spread work among G s The generated work is sent to FG s Then sort fragments to FM s An FM is responsible for a tile of pixels A triangle is only sent to one FG, so this avoids doing the same work twice Sort-Middle: If a triangle overlaps several tiles, then the triangle is sent to all FG s responsible for these tiles Results in extra work 27

28 Sort-Last Image Sorts after entire pipeline So each FG & FM has a separate frame buffer for entire screen (Z and color) 28 After all primitives have been sent to the pipeline, the z-buffers and color buffers are merged into one color buffer Can be seen as a set of independent pipelines Huge memory requirements! Used in research, but probably not commerically

29 Memory bandwith usage is huge!! Mainly due to texture reads FILTERING: For magnification: Nearest or Linear (box vs Tent filter) 29 For minification: Bilinear using mipmapping Trilinear using mipmapping Anisotropic some mipmap lookups along line of anisotropy

30 30 Bilinear filtering using Mipmapping

31 Anisotropic texture filtering 16 samples 31

32 32 Memory bandwidth usage is huge!! R is read, W is write, T is texture, Z is Z-buffer, C is color buffer Assuming 2 textures per pixel, and TR costs 24 bytes (triline MIP-mapping), the rest each costs 32 bits (4 bytes) A normal pixel costs: ZR+ZW+CW+2*TR=60 bytes per pixel At 60 fps, 1280x1024: 4.5 Gb/s But a pixel is overwritten many times! Overdraw=4 gives: 18 Gb/s! Then assume DDRAM at 300 MHz, 256 bits per access: 9.6 Gb/s 18>9.6!!

33 Memory bandwidth, cont d 18>9.6 On top of that bandwith usage is never 100%, and we can also use more textures, anti-aliasing, to use up even more bandwidth However, there are many techniques to reduce bandwith usage: Texture caching with prefetching Texture compression Z-compression Z-occlusion testing (HyperZ) 33

34 Z-occlusion testing and Z- compression One way of reducing bandwidth ATI Inc., pioneered with their HyperZ technology Very simple, and very effective Divide screen into tiles of 8x8 pixels Keep a status memory on-chip Very fast access Stores additional information that this algorithm uses Enables occlusion culling on triangle basis, z- compression, and fast Z-clears 34

35 KYRO II 35 Added by Ulf Assarsson 2004

36 KYRO II 36 Added by Ulf Assarsson 2004

37 Geforce 6800 Ultra 6800 Ultra, $499, 16 pipes, two Molex connectors, two slots, 400/ , $299, 12 pipes, one Molex connector, one slot, TBD

38 ~6Gp/s 4-8x floating-point shader power 4x shadow processing power 4x occlusion culling efficiency 2x vertex processing power ~2x frame buffer bandwidth

39

40 AGP 8 Pre T&L Vertex Cache (>4Kb) Triangle index lists: (i0,i1,i2), (i1,i2,i3)

41 The Vertex Shader Pipeline Department of Computer Engineering (6 in total)

42 AGP 8 The Vertex Shader Pipeline Pre T&L Vertex Cache (>4Kb) Department of Computer Engineering Triangle index lists: (i0,i1,i2), (i1,i2,i3) Post T&L Cache (~16 vertices à ~100 bytes) 3 shaded vertices a ~100 bytes 100Mtris/s

43 Pixel Shader Department of Computer Engineering

44 blue Department of Computer Engineering Pixel Shader red green Linear interpolation Perspective-correct interpolation

45 1 large 1 per 4 pixel pipelines >8Kb

46

47 Parallelism inside the pixel pipeline Department of Computer Engineering 216 (65,535) length pixel shader programs - shatters PS2.0 limit of 96 Dynamic Flow control - Loops & Branching, Call & Return, Subroutines Data type support - FP32, FP16 operand & texture formats Multiple Render Target Support

48 Raster Operations Pixel Pipeline 16 pixels per clock Color & Z 32 pixels per clock Z-only 64-bit FP Frame Buffer Blending

49 The Future What do we need more speed for? How much more do we need?

50 The Future What do we need more speed for? How much more do we need?

51 Hur mycket snabbare grafikkort behöver vi?

52 Hur mycket snabbare grafikkort behöver vi?

53 Hur mycket snabbare grafikkort behöver vi?

54 Hur mycket snabbare grafikkort behöver vi?

55 Hur mycket snabbare grafikkort behöver vi?

56 Hur mycket snabbare grafikkort behöver vi?

57 Hur mycket snabbare grafikkort behöver vi?

58 Hur mycket snabbare grafikkort behöver vi?

59 Hur mycket snabbare grafikkort behöver vi?

60 Hur mycket snabbare grafikkort behöver vi?

61 Hur mycket snabbare grafikkort behöver vi?

62 Hur mycket snabbare grafikkort behöver vi?

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