FPGA Acceleration of 3D Component Matching using OpenCL

Size: px
Start display at page:

Download "FPGA Acceleration of 3D Component Matching using OpenCL"

Transcription

1 FPGA Acceleration of 3D Component Introduction 2D component matching, blob extraction or region extraction, is commonly used in computer vision for detecting connected regions that meet pre-determined criteria, such as a threshold value. The technique can also the extended to volumes. Use cases include medical imaging volume analysis (e.g. MRI results), core porosity analysis (E.g. Oil gas) and many other connectivity analysis problems. Techniques A technique for 2D component labeling is presented here, with a follow on section describing how this can be extended to 3D volumes. This paper shows how it is possible to dramatically accelerate the 3D component matching on an energy-efficient FPGA-based platform using OpenCL the open standard for parallel programming. For 2D component matching several algorithms are commonly cited, the following are two examples... One component at a time The 2D image is scanned until a pixel meets the required criteria. The pixel s neighbours are then analyzed and a linked list is created of the connected neighbours. This process is repeated recursively until no more connected neighbours are found. All pixels that were part of a connected linked list are assigned the same index. The index is then incremented and the next unconnected point on the image is analyzed. The process continues until the entire image is scanned. This technique can easily be adapted for 3 dimensions. The random traversal through memory required for this approach places the performance bottle neck on system memory bandwidth. Two pass For two pass algorithm the image is scanned linearly from the top left corner to the bottom right corner. A component is given an ID according to the minimum value of its neighbours. If no neighbour exists the ID value is incremented and the pixel is set to this value. Figure 1 : Component ID labelling Figure 1 illustrates the surrounding pixels required to obtain the new ID for the current pixel. If the pixels A or D are non zero, differ from C and the pixel is valid, we have a condition where two ID s clash. At this point the lowest ID is assigned to the maximum ID and a note of the swap is made in a lookup table. This lookup table is used after the image is scanned to replace ID s that have been swapped for other ID s in the image.

2 Figure 2: Components merging After the image has been scanned the lookup table is used to replace merged ID s to create the final connected component image. This is illustrated in Figure 2. The second stage is not necessary if the data is stored as both the pre-merged image and component ID s. This avoids a costly rescan of the image. When the results are used later on, the pre-merged image is simply passed through the lookup table to produce the new image. Whether this is done or not depends upon the number of ID s discovered and the amount of resource required to store the ID s. This is dependent upon the size and complexity of the image. The two pass algorithm is most suitable for implementation on an FPGA as the data access is linear and therefore suitable for a pipelined design. 3D component labelling 3D component labelling is typically performed using the one component at a time approach. However, for large images this can quickly move the volume outside of CPU cache and the CPU will start cache thrashing, significantly reducing the overall performance. For an FPGA approach we would also not be able to hold the volume data in local memory, limiting performance to the global memory bandwidth of the accelerator. To avoid these issues the two pass approach is applied to create a series of 2D component matched planes. The 2D planes are then combined using a similar approach to the 2D matching illustrated in Figure 2, however the previous plane in the z axis is also considered. The number of individual ID s required for a large volume would exceed the storage capacity of local FPGA memory. Therefore, a technique is applied where only the current and previous plane ID s are stored. An ID that fails to appear and has not been linked with the current plane can be considered to be finished and will not occur again. At this point the ID is placed in global memory. This limits the number of ID s to store in local memory to 2x the maximum number ID s expected for any one plane. Linking between planes is illustrated in Figure 3. Figure 3 : Using overlapping planes to connect components in 3D It is often desirable to store statistics regarding the connective component data, such as the number of occurrences of an ID. In a similar fashion to the ID s the current statistics of an ID can be stored in local memory. Only when an ID no longer exists are its statistics committed to global memory. An added bonus of this approach is the ability to reuse planes for different volume analysis. If the purpose of the 3D connective component labelling is to produce spatial statistics on a volume, any overlapping volumes can reuse the 2D plane data without the need to recalculate. This can save significant amounts of processing time depending upon the amount of overlap that occurs. FPGA implementation The algorithm is relatively simple and contains no complex logic. Therefore it requires small amounts of compute resource relative to what is available in modern FPGA devices. Thanks to the techniques applied here, the algorithm also requires only a small percentage of the global memory bandwidth of what s typically available on FPGA accelerator boards. Therefore it is possible to implement many parallel instantiations, either working on different thresholds or volumes until either resource or global memory bandwidth is exhausted. The 3D volume cannot be subdivided for parallelisation, as the previous plane calculation is required prior to calculating the next. However, it is often desirable to process many different threshold values of a 3D volume in order to analysis boundaries between different materials, etc. Therefore, for this white paper it is assumed that multiple threshold values will be processed in parallel. 2

3 OpenCL Implementation The AOC compiler provided by Altera allows users to target FPGA accelerators using the Khronos OpenCL standard. This section describes how to implement the 3D connective component technique using OpenCL and targeting FPGA devices. dependencies. A single work-item flow pipelines loops within the kernel, executing a new index every clock cycle if possible. This allows a technique referred to as a sliding window to be utilised massively reducing the impact on global memory bandwidth. The Sliding Window allows previously calculated rows to be stored in local memory removing the need to constantly refer to off chip global memory. Figure 5 : Sliding window Figure 4 : Nallatech 385 FPGA card The FPGA device targeted here was a Stratix V A7 device. This device is a mid range FPGA of the Stratix V series and provides a good balance of on chip memory and logic gates. In order to achieve good acceleration it was necessary to replicate the algorithm as many times as possible. For the implementation described here, two processing algorithms were implemented. 1. Creates the 2D connected component planes for 3D volume, at various different threshold values. 2. The 3D connected component algorithm that merges planes together to create a connected volume, recording volume statistics as desired. This could be implemented as two different processing kernels, or as two distinct programs with the FPGA reprogrammed between stages 1 and 2. The latter is more desirable if re-use of plane data is expected and is the approach described here. With the sliding window implemented there is only one read and one write to global memory per pixel. After the plane has been processed the new plane ID lookup table is stored in global memory ready for the second phase (Linking of planes). It is possible to create multiple kernels on the FPGA accelerator, one for each threshold to processed, however as the FPGA is a blank canvas, every access to global memory must create its own memory controller circuitry. With 1 s of kernels implemented the memory control logic would occupy a large amount of the on device resource. To avoid replication of the memory circuitry we can create 2 kernels dedicated to handling global memory accesses, one for reading input data and another for writing output data; I.e. a producer and consumer kernel. These kernels then fan data out and consume results to and from multiple processing kernels. This prevents the unnecessary replication of global memory logic and allows more parallel paths to be implemented. Kernel 1 : Creating the Planes The OpenCL compiler allows two distinct programming approaches. The first is the traditional SIMD approach using an NDRange kernel, the second is a single work-item flow. This is the recommend approach by Altera if a design has loop or memory 3

4 Figure 8 : Linking IDs between planes Figure 6 : Multiple kernels connected via channels Figure 6 shows the arrangement of consumer, producer and worker kernels used to implement multiple paths. The communication between kernels is done via channels. Each worker kernel receives data from its own channel and writes results back to its own output channel. Each worker kernel is therefore identical with the exception of the channel IDs. Figure 8 illustrates the 9 pixels from the previous plane that are possible connections with the front pixel. As we scan along the current row any paths along the three back rows are tracked, see Figure 9. If no paths via the back or current plane are possible, a path is said to no longer exist and the current path ends. Once a row is complete the ID s are then modified to equal the minimum ID found on the valid paths. Kernel 2 : Linking the planes Once each plane has been created it is necessary to link the planes in order to create the 3D connected component volume. Again a sliding window is used to reduce the number of global memory accesses. In this case two inputs and one output are required as we require the current and previous planes input data. Figure 9: Link front plane to back plane As ID s can change from one row to the next, an ID conversion must be applied for new back pixel read from the sliding window. This would ordinarily require 9 reads from the ID lookup table, however we can use the locality of the data to realise that adjacent pixels of the back plane must be equivalent. We can therefore reduce the 9 possible ID s to just 4. This is convenient as the Altera FPGA devices permit 4 accesses to local memory simultaneously. After the plane is completed the statistics of any IDs that no longer exist are stored in global memory to be retrieved by the host. Figure 7 : Back plane sliding window Multiple Binaries An individual aocx (device binary) file was generated for the plane creation and for linking the planes. The host programs the device with the first binary and executes. The results produced by the first binary are placed in global memory. The device is then reprogrammed with the second binary and executes reading the previous binaries results from global memory. The final results are then retrieved by the host. 4

5 Benchmark The following benchmark targeted Nallatechs p385n_hpc_a7 accelerator board. This allowed up to 8 parallel worker kernels to be instantiated in a single FPGA device. This was then compared to a single core of a Xeon E GHz device with a cache size of 1536 Kbytes. The Xeon implemented a one component at a time technique optimized for a CPU. The performance improvement of the FPGA varies depending upon the complexity of the volume of data being analyzed. The more complex the image the better the FPGA performs compared to the CPU. When the image is sparse the FPGA has only a few ID s to report, however the CPU does not traverse far through the volume when processing its data and acceleration is less. When the data is dense, the CPU must traverse to all points in a nonlinear fashion, whereas the FPGA linearly traverses the data with significant performance improvement. To quantify the acceleration it is necessary to plot performance increase against the density of the image. Figure 1 shows the time taken to process 8 threshold values for varying density of the volume FPGA Xeon E5-243L 2GHz Xeon E5-243L 2GHz 2 Core Xeon E5-243L 2GHz 4 Core Figure 11 : Acceleration versus density of valid data (%) As can be seen from Figure 1 the performance of the Xeon tails off quickly for volumes with a high percentage of valid data points. This is due to the linked list used to track the current position growing in complexity. The FPGA version does not require the storage of a linked list and is therefore unaffected by how densely packed the volume is. However, the FPGA performance is affected by the number of unique path IDs. Any IDs that must be merged will have their IDs swapped after the end of each row. The likelihood of this occurring increases with the number of IDs and therefore increases the time spent in the ID swapping logic. For a very dense volume the number of unique IDs reduces until there is just 1 ID for a nearly full volume. At this point the FPGA has to perform no ID swapping and the FPGA implementation is then at its most efficient Acceleration FPGA Figure 1 : Processing time versus density of valid data (%) (256x256x256 data points, 8 parallel thresholds) Figure 12 : Processing time (seconds) versus percentage of volume occupied. (256x256x256 data points, 8 parallel thresholds) 5

6 Conclusion Using OpenCL and FPGAs it is possible to significantly accelerate 3D connected component matching. With the memory efficient algorithm described here, it is possible to replicate the processing kernel multiple times. This technique should extend to future larger FPGAs with more resource. Therefore next generation FPGAs should yield significantly greater performance than what is demonstrated here. The plane implementation will also scale to larger volumes. The only limitation will be on the number of IDs required for each plane. The number of potential unique IDs increases linearly with the area of the plane. These have to be store in local memory on the FPGA. However, there is no limit to the number of planes or depth of volume, global memory depth permitting. Future Roadmap The next generation of Altera FPGAs will provide an order of magnitude improvement over the results presented here. With the introduction of Stratix 1, Altera production will utilize 14nm Tri- Gate transistor technology. The resulting higher clock speed and denser devices result in a step change in overall performance. Applying the performance gains to the 385 results presented earlier, demonstrates a greater than 1x performance improvement versus Stratix V Stratix V Stratix 1 Figure 13 : Acceleration Versus a single Xeon Core 6

Efficient Hardware Acceleration on SoC- FPGA using OpenCL

Efficient Hardware Acceleration on SoC- FPGA using OpenCL Efficient Hardware Acceleration on SoC- FPGA using OpenCL Advisor : Dr. Benjamin Carrion Schafer Susmitha Gogineni 30 th August 17 Presentation Overview 1.Objective & Motivation 2.Configurable SoC -FPGA

More information

Single Pass Connected Components Analysis

Single Pass Connected Components Analysis D. G. Bailey, C. T. Johnston, Single Pass Connected Components Analysis, Proceedings of Image and Vision Computing New Zealand 007, pp. 8 87, Hamilton, New Zealand, December 007. Single Pass Connected

More information

How Much Logic Should Go in an FPGA Logic Block?

How Much Logic Should Go in an FPGA Logic Block? How Much Logic Should Go in an FPGA Logic Block? Vaughn Betz and Jonathan Rose Department of Electrical and Computer Engineering, University of Toronto Toronto, Ontario, Canada M5S 3G4 {vaughn, jayar}@eecgutorontoca

More information

Energy Efficient K-Means Clustering for an Intel Hybrid Multi-Chip Package

Energy Efficient K-Means Clustering for an Intel Hybrid Multi-Chip Package High Performance Machine Learning Workshop Energy Efficient K-Means Clustering for an Intel Hybrid Multi-Chip Package Matheus Souza, Lucas Maciel, Pedro Penna, Henrique Freitas 24/09/2018 Agenda Introduction

More information

CMSC 313 COMPUTER ORGANIZATION & ASSEMBLY LANGUAGE PROGRAMMING LECTURE 27, SPRING 2013

CMSC 313 COMPUTER ORGANIZATION & ASSEMBLY LANGUAGE PROGRAMMING LECTURE 27, SPRING 2013 CMSC 313 COMPUTER ORGANIZATION & ASSEMBLY LANGUAGE PROGRAMMING LECTURE 27, SPRING 2013 CACHING Why: bridge speed difference between CPU and RAM Modern RAM allows blocks of memory to be read quickly Principle

More information

(ii) Why are we going to multi-core chips to find performance? Because we have to.

(ii) Why are we going to multi-core chips to find performance? Because we have to. CSE 30321 Computer Architecture I Fall 2009 Lab 06 Introduction to Multi-core Processors and Parallel Programming Assigned: November 3, 2009 Due: November 17, 2009 1. Introduction: This lab will introduce

More information

Chain Coding Streamed Images through Crack Run-Length Encoding

Chain Coding Streamed Images through Crack Run-Length Encoding Chain Coding Streamed Images through Crack Run-Length Encoding D.G. Bailey School of Engineering and Advanced Technology, Massey University, Palmerston North, New Zealand. Email: D.G.Bailey@massey.ac.nz

More information

Altera SDK for OpenCL

Altera SDK for OpenCL Altera SDK for OpenCL A novel SDK that opens up the world of FPGAs to today s developers Altera Technology Roadshow 2013 Today s News Altera today announces its SDK for OpenCL Altera Joins Khronos Group

More information

Overview of Project's Achievements

Overview of Project's Achievements PalDMC Parallelised Data Mining Components Final Presentation ESRIN, 12/01/2012 Overview of Project's Achievements page 1 Project Outline Project's objectives design and implement performance optimised,

More information

OpenCL-Based Design of an FPGA Accelerator for Phase-Based Correspondence Matching

OpenCL-Based Design of an FPGA Accelerator for Phase-Based Correspondence Matching 90 Int'l Conf. Par. and Dist. Proc. Tech. and Appl. PDPTA'15 OpenCL-Based Design of an FPGA Accelerator for Phase-Based Correspondence Matching Shunsuke Tatsumi, Masanori Hariyama, Mamoru Miura, Koichi

More information

Challenges to Embedding Computer Vision J. Scott Gardner General Manager and Editor-in-Chief Embedded Vision Alliance (www.embedded-vision.

Challenges to Embedding Computer Vision J. Scott Gardner General Manager and Editor-in-Chief Embedded Vision Alliance (www.embedded-vision. Challenges to Embedding Computer Vision J. Scott Gardner General Manager and Editor-in-Chief Embedded Vision Alliance (www.embedded-vision.com) May 16, 2011 Figure 1 HAL 9000 a machine that sees. Source:

More information

Welcome. Altera Technology Roadshow 2013

Welcome. Altera Technology Roadshow 2013 Welcome Altera Technology Roadshow 2013 Altera at a Glance Founded in Silicon Valley, California in 1983 Industry s first reprogrammable logic semiconductors $1.78 billion in 2012 sales Over 2,900 employees

More information

System Verification of Hardware Optimization Based on Edge Detection

System Verification of Hardware Optimization Based on Edge Detection Circuits and Systems, 2013, 4, 293-298 http://dx.doi.org/10.4236/cs.2013.43040 Published Online July 2013 (http://www.scirp.org/journal/cs) System Verification of Hardware Optimization Based on Edge Detection

More information

"On the Capability and Achievable Performance of FPGAs for HPC Applications"

On the Capability and Achievable Performance of FPGAs for HPC Applications "On the Capability and Achievable Performance of FPGAs for HPC Applications" Wim Vanderbauwhede School of Computing Science, University of Glasgow, UK Or in other words "How Fast Can Those FPGA Thingies

More information

Accelerating CFD with Graphics Hardware

Accelerating CFD with Graphics Hardware Accelerating CFD with Graphics Hardware Graham Pullan (Whittle Laboratory, Cambridge University) 16 March 2009 Today Motivation CPUs and GPUs Programming NVIDIA GPUs with CUDA Application to turbomachinery

More information

Reconfigurable Multicore Server Processors for Low Power Operation

Reconfigurable Multicore Server Processors for Low Power Operation Reconfigurable Multicore Server Processors for Low Power Operation Ronald G. Dreslinski, David Fick, David Blaauw, Dennis Sylvester, Trevor Mudge University of Michigan, Advanced Computer Architecture

More information

CMSC 313 COMPUTER ORGANIZATION & ASSEMBLY LANGUAGE PROGRAMMING LECTURE 27, FALL 2012

CMSC 313 COMPUTER ORGANIZATION & ASSEMBLY LANGUAGE PROGRAMMING LECTURE 27, FALL 2012 CMSC 313 COMPUTER ORGANIZATION & ASSEMBLY LANGUAGE PROGRAMMING LECTURE 27, FALL 2012 ANNOUNCEMENTS Need student input on Lecturer Search Max Morawski Lecture 2:30pm 3:15pm, Fri 12/7, ITE 217 Meet with

More information

Higher Level Programming Abstractions for FPGAs using OpenCL

Higher Level Programming Abstractions for FPGAs using OpenCL Higher Level Programming Abstractions for FPGAs using OpenCL Desh Singh Supervising Principal Engineer Altera Corporation Toronto Technology Center ! Technology scaling favors programmability CPUs."#/0$*12'$-*

More information

SRC MAPstation Image Processing: Edge Detection

SRC MAPstation Image Processing: Edge Detection SRC MAPstation Image Processing: Edge Detection David Caliga, Director Software Applications SRC Computers, Inc. dcaliga@srccomputers.com Motivations The purpose of detecting sharp changes in image brightness

More information

GPGPUs in HPC. VILLE TIMONEN Åbo Akademi University CSC

GPGPUs in HPC. VILLE TIMONEN Åbo Akademi University CSC GPGPUs in HPC VILLE TIMONEN Åbo Akademi University 2.11.2010 @ CSC Content Background How do GPUs pull off higher throughput Typical architecture Current situation & the future GPGPU languages A tale of

More information

Fundamentals of Quantitative Design and Analysis

Fundamentals of Quantitative Design and Analysis Fundamentals of Quantitative Design and Analysis Dr. Jiang Li Adapted from the slides provided by the authors Computer Technology Performance improvements: Improvements in semiconductor technology Feature

More information

PowerVault MD3 SSD Cache Overview

PowerVault MD3 SSD Cache Overview PowerVault MD3 SSD Cache Overview A Dell Technical White Paper Dell Storage Engineering October 2015 A Dell Technical White Paper TECHNICAL INACCURACIES. THE CONTENT IS PROVIDED AS IS, WITHOUT EXPRESS

More information

1. Memory technology & Hierarchy

1. Memory technology & Hierarchy 1 Memory technology & Hierarchy Caching and Virtual Memory Parallel System Architectures Andy D Pimentel Caches and their design cf Henessy & Patterson, Chap 5 Caching - summary Caches are small fast memories

More information

Stratix vs. Virtex-II Pro FPGA Performance Analysis

Stratix vs. Virtex-II Pro FPGA Performance Analysis White Paper Stratix vs. Virtex-II Pro FPGA Performance Analysis The Stratix TM and Stratix II architecture provides outstanding performance for the high performance design segment, providing clear performance

More information

Advanced CUDA Optimization 1. Introduction

Advanced CUDA Optimization 1. Introduction Advanced CUDA Optimization 1. Introduction Thomas Bradley Agenda CUDA Review Review of CUDA Architecture Programming & Memory Models Programming Environment Execution Performance Optimization Guidelines

More information

Fast BVH Construction on GPUs

Fast BVH Construction on GPUs Fast BVH Construction on GPUs Published in EUROGRAGHICS, (2009) C. Lauterbach, M. Garland, S. Sengupta, D. Luebke, D. Manocha University of North Carolina at Chapel Hill NVIDIA University of California

More information

Digital Design Methodology (Revisited) Design Methodology: Big Picture

Digital Design Methodology (Revisited) Design Methodology: Big Picture Digital Design Methodology (Revisited) Design Methodology Design Specification Verification Synthesis Technology Options Full Custom VLSI Standard Cell ASIC FPGA CS 150 Fall 2005 - Lec #25 Design Methodology

More information

CSE 591: GPU Programming. Introduction. Entertainment Graphics: Virtual Realism for the Masses. Computer games need to have: Klaus Mueller

CSE 591: GPU Programming. Introduction. Entertainment Graphics: Virtual Realism for the Masses. Computer games need to have: Klaus Mueller Entertainment Graphics: Virtual Realism for the Masses CSE 591: GPU Programming Introduction Computer games need to have: realistic appearance of characters and objects believable and creative shading,

More information

Reduce Your System Power Consumption with Altera FPGAs Altera Corporation Public

Reduce Your System Power Consumption with Altera FPGAs Altera Corporation Public Reduce Your System Power Consumption with Altera FPGAs Agenda Benefits of lower power in systems Stratix III power technology Cyclone III power Quartus II power optimization and estimation tools Summary

More information

Digital Design Methodology

Digital Design Methodology Digital Design Methodology Prof. Soo-Ik Chae Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 1-1 Digital Design Methodology (Added) Design Methodology Design Specification

More information

Gzip Compression Using Altera OpenCL. Mohamed Abdelfattah (University of Toronto) Andrei Hagiescu Deshanand Singh

Gzip Compression Using Altera OpenCL. Mohamed Abdelfattah (University of Toronto) Andrei Hagiescu Deshanand Singh Gzip Compression Using Altera OpenCL Mohamed Abdelfattah (University of Toronto) Andrei Hagiescu Deshanand Singh Gzip Widely-used lossless compression program Gzip = LZ77 + Huffman Big data needs fast

More information

RUN-TIME RECONFIGURABLE IMPLEMENTATION OF DSP ALGORITHMS USING DISTRIBUTED ARITHMETIC. Zoltan Baruch

RUN-TIME RECONFIGURABLE IMPLEMENTATION OF DSP ALGORITHMS USING DISTRIBUTED ARITHMETIC. Zoltan Baruch RUN-TIME RECONFIGURABLE IMPLEMENTATION OF DSP ALGORITHMS USING DISTRIBUTED ARITHMETIC Zoltan Baruch Computer Science Department, Technical University of Cluj-Napoca, 26-28, Bariţiu St., 3400 Cluj-Napoca,

More information

Understanding Peak Floating-Point Performance Claims

Understanding Peak Floating-Point Performance Claims white paper FPGA Understanding Peak ing-point Performance Claims Learn how to calculate and compare the peak floating-point capabilities of digital signal processors (DSPs), graphics processing units (GPUs),

More information

LECTURE 5: MEMORY HIERARCHY DESIGN

LECTURE 5: MEMORY HIERARCHY DESIGN LECTURE 5: MEMORY HIERARCHY DESIGN Abridged version of Hennessy & Patterson (2012):Ch.2 Introduction Programmers want unlimited amounts of memory with low latency Fast memory technology is more expensive

More information

GPU ACCELERATED SELF-JOIN FOR THE DISTANCE SIMILARITY METRIC

GPU ACCELERATED SELF-JOIN FOR THE DISTANCE SIMILARITY METRIC GPU ACCELERATED SELF-JOIN FOR THE DISTANCE SIMILARITY METRIC MIKE GOWANLOCK NORTHERN ARIZONA UNIVERSITY SCHOOL OF INFORMATICS, COMPUTING & CYBER SYSTEMS BEN KARSIN UNIVERSITY OF HAWAII AT MANOA DEPARTMENT

More information

CSE 591/392: GPU Programming. Introduction. Klaus Mueller. Computer Science Department Stony Brook University

CSE 591/392: GPU Programming. Introduction. Klaus Mueller. Computer Science Department Stony Brook University CSE 591/392: GPU Programming Introduction Klaus Mueller Computer Science Department Stony Brook University First: A Big Word of Thanks! to the millions of computer game enthusiasts worldwide Who demand

More information

Architecture without explicit locks for logic simulation on SIMD machines

Architecture without explicit locks for logic simulation on SIMD machines Architecture without explicit locks for logic on machines M. Chimeh Department of Computer Science University of Glasgow UKMAC, 2016 Contents 1 2 3 4 5 6 The Using models to replicate the behaviour of

More information

TOOLS FOR IMPROVING CROSS-PLATFORM SOFTWARE DEVELOPMENT

TOOLS FOR IMPROVING CROSS-PLATFORM SOFTWARE DEVELOPMENT TOOLS FOR IMPROVING CROSS-PLATFORM SOFTWARE DEVELOPMENT Eric Kelmelis 28 March 2018 OVERVIEW BACKGROUND Evolution of processing hardware CROSS-PLATFORM KERNEL DEVELOPMENT Write once, target multiple hardware

More information

INTRODUCTION TO FPGA ARCHITECTURE

INTRODUCTION TO FPGA ARCHITECTURE 3/3/25 INTRODUCTION TO FPGA ARCHITECTURE DIGITAL LOGIC DESIGN (BASIC TECHNIQUES) a b a y 2input Black Box y b Functional Schematic a b y a b y a b y 2 Truth Table (AND) Truth Table (OR) Truth Table (XOR)

More information

Copyright 2012, Elsevier Inc. All rights reserved.

Copyright 2012, Elsevier Inc. All rights reserved. Computer Architecture A Quantitative Approach, Fifth Edition Chapter 2 Memory Hierarchy Design 1 Introduction Introduction Programmers want unlimited amounts of memory with low latency Fast memory technology

More information

Intel HLS Compiler: Fast Design, Coding, and Hardware

Intel HLS Compiler: Fast Design, Coding, and Hardware white paper Intel HLS Compiler Intel HLS Compiler: Fast Design, Coding, and Hardware The Modern FPGA Workflow Authors Melissa Sussmann HLS Product Manager Intel Corporation Tom Hill OpenCL Product Manager

More information

Computer Architecture. A Quantitative Approach, Fifth Edition. Chapter 2. Memory Hierarchy Design. Copyright 2012, Elsevier Inc. All rights reserved.

Computer Architecture. A Quantitative Approach, Fifth Edition. Chapter 2. Memory Hierarchy Design. Copyright 2012, Elsevier Inc. All rights reserved. Computer Architecture A Quantitative Approach, Fifth Edition Chapter 2 Memory Hierarchy Design 1 Programmers want unlimited amounts of memory with low latency Fast memory technology is more expensive per

More information

SDACCEL DEVELOPMENT ENVIRONMENT. The Xilinx SDAccel Development Environment. Bringing The Best Performance/Watt to the Data Center

SDACCEL DEVELOPMENT ENVIRONMENT. The Xilinx SDAccel Development Environment. Bringing The Best Performance/Watt to the Data Center SDAccel Environment The Xilinx SDAccel Development Environment Bringing The Best Performance/Watt to the Data Center Introduction Data center operators constantly seek more server performance. Currently

More information

Ray Tracing Acceleration Data Structures

Ray Tracing Acceleration Data Structures Ray Tracing Acceleration Data Structures Sumair Ahmed October 29, 2009 Ray Tracing is very time-consuming because of the ray-object intersection calculations. With the brute force method, each ray has

More information

John Hengeveld Director of Marketing, HPC Evangelist

John Hengeveld Director of Marketing, HPC Evangelist MIC, Intel and Rearchitecting for Exascale John Hengeveld Director of Marketing, HPC Evangelist Intel Data Center Group Dr. Jean-Laurent Philippe, PhD Technical Sales Manager & Exascale Technical Lead

More information

ΗΥ345 Operating Systems. Recitation 2 Memory Management - Solutions -

ΗΥ345 Operating Systems. Recitation 2 Memory Management - Solutions - ΗΥ345 Operating Systems Recitation 2 Memory Management - Solutions - Problem 7 Consider the following C program: int X[N]; int step = M; //M is some predefined constant for (int i = 0; i < N; i += step)

More information

Matrox Imaging White Paper

Matrox Imaging White Paper Reliable high bandwidth video capture with Matrox Radient Abstract The constant drive for greater analysis resolution and higher system throughput results in the design of vision systems with multiple

More information

Operating System Support

Operating System Support Operating System Support Objectives and Functions Convenience Making the computer easier to use Efficiency Allowing better use of computer resources Layers and Views of a Computer System Operating System

More information

Copyright 2012, Elsevier Inc. All rights reserved.

Copyright 2012, Elsevier Inc. All rights reserved. Computer Architecture A Quantitative Approach, Fifth Edition Chapter 2 Memory Hierarchy Design 1 Introduction Programmers want unlimited amounts of memory with low latency Fast memory technology is more

More information

Introduction to CUDA Algoritmi e Calcolo Parallelo. Daniele Loiacono

Introduction to CUDA Algoritmi e Calcolo Parallelo. Daniele Loiacono Introduction to CUDA Algoritmi e Calcolo Parallelo References q This set of slides is mainly based on: " CUDA Technical Training, Dr. Antonino Tumeo, Pacific Northwest National Laboratory " Slide of Applied

More information

Profiling-Based L1 Data Cache Bypassing to Improve GPU Performance and Energy Efficiency

Profiling-Based L1 Data Cache Bypassing to Improve GPU Performance and Energy Efficiency Profiling-Based L1 Data Cache Bypassing to Improve GPU Performance and Energy Efficiency Yijie Huangfu and Wei Zhang Department of Electrical and Computer Engineering Virginia Commonwealth University {huangfuy2,wzhang4}@vcu.edu

More information

Heterogeneous Computing with a Fused CPU+GPU Device

Heterogeneous Computing with a Fused CPU+GPU Device with a Fused CPU+GPU Device MediaTek White Paper January 2015 2015 MediaTek Inc. 1 Introduction Heterogeneous computing technology, based on OpenCL (Open Computing Language), intelligently fuses GPU and

More information

Memory Hierarchy Computing Systems & Performance MSc Informatics Eng. Memory Hierarchy (most slides are borrowed)

Memory Hierarchy Computing Systems & Performance MSc Informatics Eng. Memory Hierarchy (most slides are borrowed) Computing Systems & Performance Memory Hierarchy MSc Informatics Eng. 2011/12 A.J.Proença Memory Hierarchy (most slides are borrowed) AJProença, Computer Systems & Performance, MEI, UMinho, 2011/12 1 2

More information

Chapter 6 Memory 11/3/2015. Chapter 6 Objectives. 6.2 Types of Memory. 6.1 Introduction

Chapter 6 Memory 11/3/2015. Chapter 6 Objectives. 6.2 Types of Memory. 6.1 Introduction Chapter 6 Objectives Chapter 6 Memory Master the concepts of hierarchical memory organization. Understand how each level of memory contributes to system performance, and how the performance is measured.

More information

Memory Optimization for OpenCL on Intel FPGAs Exercise Manual

Memory Optimization for OpenCL on Intel FPGAs Exercise Manual Memory Optimization for OpenCL on Intel FPGAs Exercise Manual Software Requirements that cannot be adjusted: Intel FPGA SDK for OpenCL version 17.1 Software Requirements that can be adjusted: Operation

More information

General Purpose GPU Programming. Advanced Operating Systems Tutorial 9

General Purpose GPU Programming. Advanced Operating Systems Tutorial 9 General Purpose GPU Programming Advanced Operating Systems Tutorial 9 Tutorial Outline Review of lectured material Key points Discussion OpenCL Future directions 2 Review of Lectured Material Heterogeneous

More information

GPU programming basics. Prof. Marco Bertini

GPU programming basics. Prof. Marco Bertini GPU programming basics Prof. Marco Bertini CUDA: atomic operations, privatization, algorithms Atomic operations The basics atomic operation in hardware is something like a read-modify-write operation performed

More information

COPROCESSOR APPROACH TO ACCELERATING MULTIMEDIA APPLICATION [CLAUDIO BRUNELLI, JARI NURMI ] Processor Design

COPROCESSOR APPROACH TO ACCELERATING MULTIMEDIA APPLICATION [CLAUDIO BRUNELLI, JARI NURMI ] Processor Design COPROCESSOR APPROACH TO ACCELERATING MULTIMEDIA APPLICATION [CLAUDIO BRUNELLI, JARI NURMI ] Processor Design Lecture Objectives Background Need for Accelerator Accelerators and different type of parallelizm

More information

Memory Hierarchy Computing Systems & Performance MSc Informatics Eng. Memory Hierarchy (most slides are borrowed)

Memory Hierarchy Computing Systems & Performance MSc Informatics Eng. Memory Hierarchy (most slides are borrowed) Computing Systems & Performance Memory Hierarchy MSc Informatics Eng. 2012/13 A.J.Proença Memory Hierarchy (most slides are borrowed) AJProença, Computer Systems & Performance, MEI, UMinho, 2012/13 1 2

More information

Copyright 2012, Elsevier Inc. All rights reserved.

Copyright 2012, Elsevier Inc. All rights reserved. Computer Architecture A Quantitative Approach, Fifth Edition Chapter 2 Memory Hierarchy Design Edited by Mansour Al Zuair 1 Introduction Programmers want unlimited amounts of memory with low latency Fast

More information

EECS4201 Computer Architecture

EECS4201 Computer Architecture Computer Architecture A Quantitative Approach, Fifth Edition Chapter 1 Fundamentals of Quantitative Design and Analysis These slides are based on the slides provided by the publisher. The slides will be

More information

A Performance and Energy Comparison of FPGAs, GPUs, and Multicores for Sliding-Window Applications

A Performance and Energy Comparison of FPGAs, GPUs, and Multicores for Sliding-Window Applications A Performance and Energy Comparison of FPGAs, GPUs, and Multicores for Sliding-Window Applications Jeremy Fowers, Greg Brown, Patrick Cooke, Greg Stitt University of Florida Department of Electrical and

More information

Memory Systems IRAM. Principle of IRAM

Memory Systems IRAM. Principle of IRAM Memory Systems 165 other devices of the module will be in the Standby state (which is the primary state of all RDRAM devices) or another state with low-power consumption. The RDRAM devices provide several

More information

Concurrent Manipulation of Dynamic Data Structures in OpenCL

Concurrent Manipulation of Dynamic Data Structures in OpenCL Concurrent Manipulation of Dynamic Data Structures in OpenCL Henk Mulder University of Twente P.O. Box 217, 7500AE Enschede The Netherlands h.mulder-1@student.utwente.nl ABSTRACT With the emergence of

More information

A Hybrid Approach to CAM-Based Longest Prefix Matching for IP Route Lookup

A Hybrid Approach to CAM-Based Longest Prefix Matching for IP Route Lookup A Hybrid Approach to CAM-Based Longest Prefix Matching for IP Route Lookup Yan Sun and Min Sik Kim School of Electrical Engineering and Computer Science Washington State University Pullman, Washington

More information

Course web site: teaching/courses/car. Piazza discussion forum:

Course web site:   teaching/courses/car. Piazza discussion forum: Announcements Course web site: http://www.inf.ed.ac.uk/ teaching/courses/car Lecture slides Tutorial problems Courseworks Piazza discussion forum: http://piazza.com/ed.ac.uk/spring2018/car Tutorials start

More information

Cover TBD. intel Quartus prime Design software

Cover TBD. intel Quartus prime Design software Cover TBD intel Quartus prime Design software Fastest Path to Your Design The Intel Quartus Prime software is revolutionary in performance and productivity for FPGA, CPLD, and SoC designs, providing a

More information

Scalable Compression and Transmission of Large, Three- Dimensional Materials Microstructures

Scalable Compression and Transmission of Large, Three- Dimensional Materials Microstructures Scalable Compression and Transmission of Large, Three- Dimensional Materials Microstructures William A. Pearlman Center for Image Processing Research Rensselaer Polytechnic Institute pearlw@ecse.rpi.edu

More information

Computer Architecture A Quantitative Approach, Fifth Edition. Chapter 2. Memory Hierarchy Design. Copyright 2012, Elsevier Inc. All rights reserved.

Computer Architecture A Quantitative Approach, Fifth Edition. Chapter 2. Memory Hierarchy Design. Copyright 2012, Elsevier Inc. All rights reserved. Computer Architecture A Quantitative Approach, Fifth Edition Chapter 2 Memory Hierarchy Design 1 Introduction Programmers want unlimited amounts of memory with low latency Fast memory technology is more

More information

Is There A Tradeoff Between Programmability and Performance?

Is There A Tradeoff Between Programmability and Performance? Is There A Tradeoff Between Programmability and Performance? Robert Halstead Jason Villarreal Jacquard Computing, Inc. Roger Moussalli Walid Najjar Abstract While the computational power of Field Programmable

More information

Parallel Computing: Parallel Architectures Jin, Hai

Parallel Computing: Parallel Architectures Jin, Hai Parallel Computing: Parallel Architectures Jin, Hai School of Computer Science and Technology Huazhong University of Science and Technology Peripherals Computer Central Processing Unit Main Memory Computer

More information

Flexible Architecture Research Machine (FARM)

Flexible Architecture Research Machine (FARM) Flexible Architecture Research Machine (FARM) RAMP Retreat June 25, 2009 Jared Casper, Tayo Oguntebi, Sungpack Hong, Nathan Bronson Christos Kozyrakis, Kunle Olukotun Motivation Why CPUs + FPGAs make sense

More information

Algorithms and Architecture. William D. Gropp Mathematics and Computer Science

Algorithms and Architecture. William D. Gropp Mathematics and Computer Science Algorithms and Architecture William D. Gropp Mathematics and Computer Science www.mcs.anl.gov/~gropp Algorithms What is an algorithm? A set of instructions to perform a task How do we evaluate an algorithm?

More information

CS6303 Computer Architecture Regulation 2013 BE-Computer Science and Engineering III semester 2 MARKS

CS6303 Computer Architecture Regulation 2013 BE-Computer Science and Engineering III semester 2 MARKS CS6303 Computer Architecture Regulation 2013 BE-Computer Science and Engineering III semester 2 MARKS UNIT-I OVERVIEW & INSTRUCTIONS 1. What are the eight great ideas in computer architecture? The eight

More information

Embedded Systems Design Prof. Anupam Basu Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur

Embedded Systems Design Prof. Anupam Basu Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur Embedded Systems Design Prof. Anupam Basu Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur Lecture - 05 Optimization Issues Now I see, that is not been seen there;

More information

High performance Computing and O&G Challenges

High performance Computing and O&G Challenges High performance Computing and O&G Challenges 2 Seismic exploration challenges High Performance Computing and O&G challenges Worldwide Context Seismic,sub-surface imaging Computing Power needs Accelerating

More information

Page 1. Area-Subdivision Algorithms z-buffer Algorithm List Priority Algorithms BSP (Binary Space Partitioning Tree) Scan-line Algorithms

Page 1. Area-Subdivision Algorithms z-buffer Algorithm List Priority Algorithms BSP (Binary Space Partitioning Tree) Scan-line Algorithms Visible Surface Determination Visibility Culling Area-Subdivision Algorithms z-buffer Algorithm List Priority Algorithms BSP (Binary Space Partitioning Tree) Scan-line Algorithms Divide-and-conquer strategy:

More information

Computational Optimization ISE 407. Lecture1. Dr. Ted Ralphs

Computational Optimization ISE 407. Lecture1. Dr. Ted Ralphs Computational Optimization ISE 407 Lecture1 Dr. Ted Ralphs ISE 407 Lecture 1 1 Reading for this Lecture How Computers Work, R. Young (on-line) The Elements of Computing Systems, N. Nisan and S. Schocken

More information

August 1994 / Features / Cache Advantage. Cache design and implementation can make or break the performance of your high-powered computer system.

August 1994 / Features / Cache Advantage. Cache design and implementation can make or break the performance of your high-powered computer system. Cache Advantage August 1994 / Features / Cache Advantage Cache design and implementation can make or break the performance of your high-powered computer system. David F. Bacon Modern CPUs have one overriding

More information

Copyright 2012, Elsevier Inc. All rights reserved.

Copyright 2012, Elsevier Inc. All rights reserved. Computer Architecture A Quantitative Approach, Fifth Edition Chapter 1 Fundamentals of Quantitative Design and Analysis 1 Computer Technology Performance improvements: Improvements in semiconductor technology

More information

Parallel Architectures

Parallel Architectures Parallel Architectures CPS343 Parallel and High Performance Computing Spring 2018 CPS343 (Parallel and HPC) Parallel Architectures Spring 2018 1 / 36 Outline 1 Parallel Computer Classification Flynn s

More information

GPU Acceleration of Matrix Algebra. Dr. Ronald C. Young Multipath Corporation. fmslib.com

GPU Acceleration of Matrix Algebra. Dr. Ronald C. Young Multipath Corporation. fmslib.com GPU Acceleration of Matrix Algebra Dr. Ronald C. Young Multipath Corporation FMS Performance History Machine Year Flops DEC VAX 1978 97,000 FPS 164 1982 11,000,000 FPS 164-MAX 1985 341,000,000 DEC VAX

More information

Design Issues 1 / 36. Local versus Global Allocation. Choosing

Design Issues 1 / 36. Local versus Global Allocation. Choosing Design Issues 1 / 36 Local versus Global Allocation When process A has a page fault, where does the new page frame come from? More precisely, is one of A s pages reclaimed, or can a page frame be taken

More information

FPGA-based Supercomputing: New Opportunities and Challenges

FPGA-based Supercomputing: New Opportunities and Challenges FPGA-based Supercomputing: New Opportunities and Challenges Naoya Maruyama (RIKEN AICS)* 5 th ADAC Workshop Feb 15, 2018 * Current Main affiliation is Lawrence Livermore National Laboratory SIAM PP18:

More information

8. Best Practices for Incremental Compilation Partitions and Floorplan Assignments

8. Best Practices for Incremental Compilation Partitions and Floorplan Assignments 8. Best Practices for Incremental Compilation Partitions and Floorplan Assignments QII51017-9.0.0 Introduction The Quartus II incremental compilation feature allows you to partition a design, compile partitions

More information

CUDA PROGRAMMING MODEL Chaithanya Gadiyam Swapnil S Jadhav

CUDA PROGRAMMING MODEL Chaithanya Gadiyam Swapnil S Jadhav CUDA PROGRAMMING MODEL Chaithanya Gadiyam Swapnil S Jadhav CMPE655 - Multiple Processor Systems Fall 2015 Rochester Institute of Technology Contents What is GPGPU? What s the need? CUDA-Capable GPU Architecture

More information

FPGA Implementation of a Single Pass Real-Time Blob Analysis Using Run Length Encoding

FPGA Implementation of a Single Pass Real-Time Blob Analysis Using Run Length Encoding FPGA Implementation of a Single Pass Real-Time J. Trein *, A. Th. Schwarzbacher + and B. Hoppe * Department of Electronic and Computer Science, Hochschule Darmstadt, Germany *+ School of Electronic and

More information

An Appropriate Search Algorithm for Finding Grid Resources

An Appropriate Search Algorithm for Finding Grid Resources An Appropriate Search Algorithm for Finding Grid Resources Olusegun O. A. 1, Babatunde A. N. 2, Omotehinwa T. O. 3,Aremu D. R. 4, Balogun B. F. 5 1,4 Department of Computer Science University of Ilorin,

More information

Accelerating Applications. the art of maximum performance computing James Spooner Maxeler VP of Acceleration

Accelerating Applications. the art of maximum performance computing James Spooner Maxeler VP of Acceleration Accelerating Applications the art of maximum performance computing James Spooner Maxeler VP of Acceleration Introduction The Process The Tools Case Studies Summary What do we mean by acceleration? How

More information

5. ReAl Systems on Silicon

5. ReAl Systems on Silicon THE REAL COMPUTER ARCHITECTURE PRELIMINARY DESCRIPTION 69 5. ReAl Systems on Silicon Programmable and application-specific integrated circuits This chapter illustrates how resource arrays can be incorporated

More information

high performance medical reconstruction using stream programming paradigms

high performance medical reconstruction using stream programming paradigms high performance medical reconstruction using stream programming paradigms This Paper describes the implementation and results of CT reconstruction using Filtered Back Projection on various stream programming

More information

PERFORMANCE METRICS. Mahdi Nazm Bojnordi. CS/ECE 6810: Computer Architecture. Assistant Professor School of Computing University of Utah

PERFORMANCE METRICS. Mahdi Nazm Bojnordi. CS/ECE 6810: Computer Architecture. Assistant Professor School of Computing University of Utah PERFORMANCE METRICS Mahdi Nazm Bojnordi Assistant Professor School of Computing University of Utah CS/ECE 6810: Computer Architecture Overview Announcement Sept. 5 th : Homework 1 release (due on Sept.

More information

Performance of Multicore LUP Decomposition

Performance of Multicore LUP Decomposition Performance of Multicore LUP Decomposition Nathan Beckmann Silas Boyd-Wickizer May 3, 00 ABSTRACT This paper evaluates the performance of four parallel LUP decomposition implementations. The implementations

More information

Lecture 13: March 25

Lecture 13: March 25 CISC 879 Software Support for Multicore Architectures Spring 2007 Lecture 13: March 25 Lecturer: John Cavazos Scribe: Ying Yu 13.1. Bryan Youse-Optimization of Sparse Matrix-Vector Multiplication on Emerging

More information

Idea. Found boundaries between regions (edges) Didn t return the actual region

Idea. Found boundaries between regions (edges) Didn t return the actual region Region Segmentation Idea Edge detection Found boundaries between regions (edges) Didn t return the actual region Segmentation Partition image into regions find regions based on similar pixel intensities,

More information

1 The size of the subtree rooted in node a is 5. 2 The leaf-to-root paths of nodes b, c meet in node d

1 The size of the subtree rooted in node a is 5. 2 The leaf-to-root paths of nodes b, c meet in node d Enhancing tree awareness 15. Staircase Join XPath Accelerator Tree aware relational XML resentation Tree awareness? 15. Staircase Join XPath Accelerator Tree aware relational XML resentation We now know

More information

Accelerating the Pulsar Search Pipeline with FPGAs, Programmed in OpenCL

Accelerating the Pulsar Search Pipeline with FPGAs, Programmed in OpenCL Accelerating the Pulsar Search Pipeline with FPGAs, Programmed in OpenCL Oliver Sinnen, Tyrone Sherwin, and Haomiao Wang & Prabu Thiagaraj (Manchester Uni/Raman Research Institute, Bangalore) Parallel

More information

Objectives and Functions Convenience. William Stallings Computer Organization and Architecture 7 th Edition. Efficiency

Objectives and Functions Convenience. William Stallings Computer Organization and Architecture 7 th Edition. Efficiency William Stallings Computer Organization and Architecture 7 th Edition Chapter 8 Operating System Support Objectives and Functions Convenience Making the computer easier to use Efficiency Allowing better

More information

Hammer Slide: Work- and CPU-efficient Streaming Window Aggregation

Hammer Slide: Work- and CPU-efficient Streaming Window Aggregation Large-Scale Data & Systems Group Hammer Slide: Work- and CPU-efficient Streaming Window Aggregation Georgios Theodorakis, Alexandros Koliousis, Peter Pietzuch, Holger Pirk Large-Scale Data & Systems (LSDS)

More information

Lecture 6: Input Compaction and Further Studies

Lecture 6: Input Compaction and Further Studies PASI Summer School Advanced Algorithmic Techniques for GPUs Lecture 6: Input Compaction and Further Studies 1 Objective To learn the key techniques for compacting input data for reduced consumption of

More information