Digital Signal Processing: A Hardware-Based Approach

Transcription

1 Digitl Signl Processing: A Hrdwre-Bsed Approch Roert Esposito Electricl nd Computer Engineering Temple University troduction Teching Digitl Signl Processing (DSP) hs included the utilition of simultion tool (ST) for student projects nd homework. The leding ST in cdemi is MATLAB y MthWorks. MATLAB is vector sed environment tht is conducive to DSP simultion. Specificlly, filter design is simulted utiliing C-like code. Students re le to enter filter design s discrete time sequence or discrete trnsfer function. MATLAB hs uild in functions tht generte deterministic nd non-deterministic signls which cn then e inputted to the designed filter. The output of the filter cn then e nlyed in the time-domin or frequency-domin utiliing other MATLAB functions. MATLAB, however, is not conducive to teching the structurl spects of filter design. Simulink is lock sed design system tht provides grphicl environment nd customile set of lock lirries tht llows the user to simulte nd test vriety of systems such s digitl filters. Simulink hs n extensive DSP lirry tht contins locks for implementing everything from signl genertion to dptive filtering. Even though Simulink is more relistic implementtion environment thn MATLAB, it is still purely simultion. Reliing the need for users to e le to perform rel hrdwre implementtions, MthWorks collorted with Xilinx to produce System Genertor (SG). SG is group of extensive lirries tht re included in Simulink. The SG lirries include hrdwre sed locks tht interct with trditionl Simulink locks. Therefore, hrdwre designs cn e synthesied, downloded to Xilinx Field Progrmmle Gte Arry (FPGA) nd then compred in rel time to their Simulink simultion counterprts. Simulink IIR Filter Design IIR filter design is stndrd topic in ny DSP course. Specificlly, second order lowpss, highpss, ndpss nd ndstop filters cn e implemented nd nlyed. Shown in eqution, is well known trnsfer function of second order notch IIR filter 2. 2 K( 2 β + ) 2 β( α) α ) H( ) = () + + the trnsfer function of eqution, α determines the 3-dB ndwidth, β determines the center frequency nd K determines the mximum mgnitude vlue. This filter cn e implemented in Simulink in vrious wys. One implementtion method is the utilition of uilt in IIR filter lock where the user cn specify the numertor nd denomintor coefficients of the trnsfer function. Shown in figure, however, is discrete time eqution implementtion of the notch IIR filter in eqution with α =., β =.2, K =.55. this design, white noise sequence is smpled t smples per second nd inputted to the notch filter. Its output spectrum is then nlyed using fst Fourier trnsform (FFT) lock. Proceedings of the 2007 Middle Atlntic Section Fll Conference of the Americn Society for Engineering Eduction

2 2 Figure : Simulink Notch Filter The notch filter of eqution is implemented using n emedded MATLAB function nd dely locks s shown in figure. This implementtion is direct implementtion of the discrete time eqution tht represents the trnsfer function s shown in eqution 2. yn [ ] = β ( + α) yn [ ] αyn [ 2] + Kxn [ ] 2 Kβxn [ ] + Kxn [ 2] (2) System Genertor IIR Filter Design The Simulink implementtion of the IIR filter s shown in figure, does not tke into ccount structure. Shown in figure 2, is well known structure for IIR filters is Direct Form II. Direct Form II is cnonic IIR filter structure wherein the numer of delys is equl to the order of the filter. Cnonic structures re importnt to minimie hrdwre components. Figure 2: Generlied Direct Form II IIR Structure Proceedings of the 2007 Middle Atlntic Section Fll Conference of the Americn Society for Engineering Eduction

3 3 A Direct Form II structure tht represents the notch filter in eqution cn e implemented utiliing hrdwre locks in SG 3. Specificlly, the only SG hrdwre locks tht will e needed re delys, dders nd multipliers. Shown in figure 3, is the SG implementtion of the Direct Form II structure. Dely2 Gtewy -3 + AddSu2 Dely () Mult4 + AddSu3 Out Gtewy Out Dely - Gtewy AddSu + AddSu + () -3-3 () Gtewy 2 Mult Mult Dely - Gtewy 3 Gtewy 4 () -3 Mult2-3 () Mult3 Figure 3: SG Implementtion of Direct form IIR Filter The Gtewy- locks re essentilly nlog to digitl converters (ADC). The Gtewy- locks smple nd quntie signls from the Simulink environment so they cn e processed y digitl SG hrdwre locks. The Gtewy-Out lock is the opposite of the Gtewy- lock. The Gtewy-Out cts s digitl to nlog converter (DAC) for outputting signls to e nlyed ck to the Simulink environment. One distinct difference etween the Simulink structure in figure 2 nd the SG structure in figure 3 is the ddition of two extr delys (dely2 nd dely3). The structure in figure 2 ssumes tht multipliers - M nd -N hve ltency of ero. hrdwre design, however, locks sometimes hve ltency which cn throw off the synchronition of the dt pipeline. Since SG multipliers Mult, Mult2, Mult3, Mult4 nd Mult5 ech hve defult ltency of 3 smples, it is necessry to dd dely2 nd dely3 which hve ltency of 3 in order to mintin the integrity of eqution 2. Furthermore, unlike the structure in figure 2, quntition error ecomes n importnt issue. Specificlly, ech SG hrdwre lock of figure 3 hs finite wordlength. Before setting the fixed numer of its for ech lock, the user must hve knowledge of the rnge of dt points eing used in the design. Knowledge of the dt rnge llows for optiml setting of integer nd frctionl its. ML402 Bord After the initil design, the next logicl step is to implement nd verify the functionlity of the SG hrdwre design on n FPGA. The ML402 is development pltform used for hrdwre verifiction tht includes Xilinx Virtex 4 FPGA, push uttons, slide switches, LEDs nd n LCD. Shown in figure 4, is the ML402 ord 4. Proceedings of the 2007 Middle Atlntic Section Fll Conference of the Americn Society for Engineering Eduction

4 4 Figure 4: ML402 Bord An importnt feture of the ML402 is the Xilinx Virtex 4 FPGA 5. The Virtex 4 cn come in vriety of device pckges. Specificlly, one device pckge is the Virtex 4 XC4VSX35. The XC4VSX35 is DSP focused device tht comprises 92 emedded multipliers, 92 8KB of lock RAM nd 34,560 logic cells. This is the device tht ws trgeted in this puliction. Hrdwre Anlysis nd Verifiction Hrdwre synthesis is the process of trnslting nd mpping hrdwre design into trgeted rchitecture. The SG implementtion of n IIR filter s shown in figure 3 must e synthesied to the XC4VSX35 FPGA of the ML402 ord. Shown in figure 5, is screen shot of the SG window wherein synthesis options re selected. Figure 5: SG Synthesis Options figure 5, it is shown tht the compiltion device is selected s the Virtex 4 ML402 ord. This selection will llow Simulink to pss signls nd retrieve signls from the ML402 ord during process Proceedings of the 2007 Middle Atlntic Section Fll Conference of the Americn Society for Engineering Eduction

5 5 clled Hrdwre Co-Simultion. Hrdwre Co-Simultion is process wherein the synthesied design is running on the hrdwre ord while the Simulink simultion model is running on the PC. This llows the output of the hrdwre implementtion to e simultneously compred with the output of the simultion for verifiction purposes. When synthesis is complete, SG provides report which detils the mount nd type of FPGA resources tht were needed to implement the design. The IIR filter design of figure 3 utilied 20 emedded multipliers (0% of ville multipliers) nd 00 hrdwre slices (7% of ville slices). The design utilied 20 emedded multipliers insted of the five shown in the design ecuse of the dt wordlength. For this prticulr synthesis, the dt wordlength ws set t 32 its for ech lock. On the Virtex 4, however, ech emedded multiplier cn only perform n 8-it y 8-it multipliction. Therefore, in order to produce 32-it y 32-it multipliction, four 8-it multipliers were utilied for ech fully pipelined multipliction. This multiplier pipeline lso incresed the minimum ltency of ech multipliction to 5 clock cycles. Shown in figure 6, is the hrdwre co-simultion setup fter successful synthesis. The synthesied lock is shown on the ottom wherein it is connected to the Simulink inputs nd outputs in the sme mnner s the other models. Sy stem Genertor teger Dely Bnd-Limited White Noise -9 Z Gin Unit Dely2 Unit Dely3 x x x2 y notchfilter y y2. Constnt.2 Constnt A B K Emedded MATLAB Function Constnt2 Add 2 Divide Unit Dely Unit Dely Constnt3 Dely2 Gtewy -5 + AddSu2 Dely () Mult4 + AddSu3 Out Gtewy Out B-FFT Spectrum Scope Dely - Product Gtewy AddSu + AddSu + () -5-5 () -2 Product Product2 Gtewy 2 Mult Mult Constnt4 Dely - - Gin Gtewy 3 () -5-5 () Mult2 Mult3 Gtewy 4 Gtewy Gtewy Gtewy 2 JTAG Co-sim Gtewy Out Out Gtewy Out Gtewy 3 Gtewy 4 see_0_20 hwcosim Figure 6: Simulink Model (Top), Un-Synthesied Hrdwre (Middle), Synthesied Hrdwre (Bottom) After the synthesied lock hs een connected in the model, hrdwre co-simultion cn e executed. During co-simultion, the synthesied design is downloded to the trget device (ML402 Virtex 4). The design then runs on the FPGA nd communictes with the host PC vi JTAG cle. JTAG cle is stndrd communiction protocol tht is widely used in Xilinx development ords. JTAG llows Proceedings of the 2007 Middle Atlntic Section Fll Conference of the Americn Society for Engineering Eduction

6 6 Simulink to pss the inputs through the Gtewy- to the Virtex 4. The Virtex 4 then performs the notch filter s designed nd psses the output ck to Simulink through the Gtewy-Out. This provides mens for compring the simultion output with the ctul hrdwre output output. Shown in figure 7 nd 8, re comprisons of the spectrums of the Simulink white noise input, Simulink notch filter output nd hrdwre notch filter output. Figures 7 nd 8 hve dt wordlengths of 8 its nd 2 its respectively. The spectrum output of the 8-it hrdwre implemented notch filter in figure 7 does not perform s well s the Mtl simultion. The spectrum output of the 2-it hrdwre implementtion notch filter in figure 8, however, performs similr to the Mtl Simultion. Figure 7: Filter Output Spectrum (8-it word) Figure 8: Filter Output Spectrum (2-it word) Proceedings of the 2007 Middle Atlntic Section Fll Conference of the Americn Society for Engineering Eduction

7 7 Conclusion Teching nd understnding pertinent topics of Digitl Signl Processing cn no longer e limited to computer sed simultion. Prticulrly, nlysis of multirte filtering nd filter structures cn enefit from hrdwre sed pproch. Hrdwre implementtion of fundmentl DSP topics introduces the student to effects tht re olivious to computer simultion. Specificlly, finite wordlength effects, floting point vs. fixed point numer representtion nd pipeline synchronition. Xilinx System Genertor provides n esy to use softwre/hrdwre hyrid pltform for sic to dvnced hrdwre designs. Furthermore, students re not required to study hrdwre description lnguge, which trnsltes to fluent introduction of System Genertor into the course. References [] Snjit K. Mitr, Digitl Signl Processing: A Computer Bsed Approch, McGrw Hill, [2] MthWorks, Simulink, [3] Xilinx, System Genertor, [4] Xilinx, Virtex 4, [5] Xilinx, ML402, Proceedings of the 2007 Middle Atlntic Section Fll Conference of the Americn Society for Engineering Eduction