10GBASE-KR for 40G Backplane
|
|
- Brett Carter
- 6 years ago
- Views:
Transcription
1 1GBASE-KR for 4G Backplane Nov 7 Technology Hiroshi Takatori Hiroshi.Takatori@.us 1
2 Outline This contribution discusses, - Performance based on 1GBASE-KR Std - Theoretical Limit (Saltz SNR) and Time Domain Simulation - Performance Improvement - Summary
3 4G Backplane A Single Lane, 1GBASE-KR 8.3ap, Clause 7 Main Requirements Signaling: 1.315Gbaud(+/-1ppm), PAM Transmitter: 1mVpp Max, 3-tap Pre-Equalization, Total Jitter < 8%UIpp Return Loss: 9dB 5M ~.5GHz, 1dB/dec. from.5 ~ 7.5GHz Insertion Loss: < ILmax(f), 4.5dB at 5GHz, Informative Cross-talk: Defined as ICR, Ratio of IL to Power sum crosstalk, PSXT ICR > ICRmin = Log(f/5G), Informative BER: Better than 1**(-1) Receiver Interference Tolerance Broadband noise: 5.mVrsm(5GHzband) Jitter UI p-p: 13% (random), 3.5%(DCD), 11.5%(sinusoidal) Total 17 channels are uploaded to verify the system performance. 3
4 Channel discussed by 1GBASE-KR TYCO, 7 Channels Description Channel Name Line Card No. Connectors Backplane Total Length 5GHz TYCO 7 cases [1] Signal path One FEXT Two NEXT Case dB Case Case Case Case Case Case [1] 4
5 Description Channel discussed by 1GBASE-KR Molex, channels and Intel, 8 channels Channel Name Line Card No. Connectors Backplane Total Length 5GHz Molex cases [] Signal oath 3 FEXT 4 NEXT 1m_Improved _ m_Improved _ (?) Intel 8 cases [3] Signal path FEXT 6NEXT T1 T T B B B M M [] [3] 5
6 IL and ICR -1 ILmax -1-1 SDD1 (db) ~7dB TYCO 7 channels ~.5dB Molex channels ~7dB Intel 8 channels -6 1M 1E+8 5E+8 1E+9 1G 5E+9 1G 1E+1 E+1 Frequency (Hz) M 1E+8 5E+8 1E+9 1G 5E+9 1E+1 1G E+1 1M 1E+8 5E+8 1E+9 1G 5E+9 1E+1 1G E ICRmin HIGH CONFIDENCE 5 HIGH CONFIDENCE 5 HIGH CONFIDENCE 4 REGION 4 REGION 4 REGION ICR (db) 1 TYCO 1 Molex 1 Intel M 1E+8 5E+8 1E+9 1G 5E+9 1E+1 1G E+1 Frequency (Hz) M 1E+8 5E+8 1E+9 1G 5E+9 1E+1 1G E+1 1M 1E+8 5E+8 1E+9 1G 5E+9 1E+1 1G E+1 No cases are in HIGH CONFIDENCE 6
7 Performance Study The purpose is to confirm 1GBASE-KR applicability for 4G. 1 st Step: Calculate theoretical SNR (Saltz) against broadband noise, measured crosstalk, and IC electronic noise. nd Step: Check Jitter and other IC implementation loss by the time domain simulator 3 rd Step: Performance Improvement by Crosstalk Canceller Noise Margin is used throughout the discussion. Noise Margin = [Achievable SNR] SNRrequired SNRrequired is 17dB for PAM, BER = 1 **-1 It is preferred to be greater than on the order of 6dB for a robust operation. 7
8 Noise Margin by Saltz Three scenarios : 1. 5.mV-rms broadband noise defined by 1GBase-KR Receiver Interference Tolerance. Measured crosstalk from S-parameter 3. Crosstalk + -14dBm/Hz (IC electronic noise 3nV/sqrt(Hz) into 1ohm) Noise Margin (db) Black: 5.mV Broadband noise Blue: Crosstalk Red: Crosstalk + IC Noise 6dB Margin Transmit power: 1dBm (.4Vop with.75fs 1 st order low-pass) All except few cases met 6dB margin. Feasible subject to IC noise floor. The result does not include - Jitter - Implementation loss TYCO Molex INTEL Additions Backplane Channel Provided to the 8.3ap 8
9 Jitter and Implementation Loss A time domain simulator is created for nd step. RX Jitter TX-Pre-EQL Initial Settings by Standard ( D.41D**) TX Jitter Back Plane Channel NEXT and FEXT IC electronic Noise Receivers IC Termination: IEEE P8.3ap Document An Eye on Return Loss, by Richard Melliitz, Intel 14-May-5 SNR TX Jitter.8UIpp (5 sigma) jitter RX Jitter.1 UIrms random jitter (VCO) + systematic timing recovery jitter (bigger than receiver interference tolerance) IC Electronic Noise -14dBm/Hz FFE 8tap DFE 16, 3, 64, and 18tap Crosstalk Canceller added later as an option 9
10 Jitter and Implementation Loss SNR (db) Level IC Noise Sampled Eye Diagram Jitter SNR X-talk Following impairments are added one by one after the receiver is fully activated after 1 million-symbol iterations. - IC noise, -14dBm/Hz - TX and RX Jitter - DFE tap length reduction, 18, 64, 3, 16 - FEXT + NEXT CH1(Intel T) is shown as an example. All channels were simulated to verify the degradation. 15 DFE Tap length change Iteration Time (# of million symbols) 1
11 Margin with Jitter and IC Jitter and IC implementation loss + Crosstalk + -14dBm/Hz IC noise Receiver Resource: 8 tap FFE + 18 tap DFE Theoretical margin Result represents high performance design and could degrade more. Noise Margin (db) dB Margin Marginal for many cases. Industrial systems need to be robust against alien noise, impulsive noise, etc. Margin with Jitter and IC implementation How can they be improved? 7 TYCO Molex 8 INTEL Additions 11
12 Crosstalk Canceller Sampled Eye Crosstalk cancellation mode ( million iterations) is added at the end of the behavioral simulation. Level Margin was improved by 7dB in this example (CH1, Intel case-3). 35 Similar improvements shown in the previous chart were confirmed for all cases. SNR (db) 3 5 IC Noise Jitter SNR Canceller X-talk 7dB improvement 15 1 DFE Tap length change Iteration Time (# of million symbols) 1
13 Crosstalk Canceller Crosstalk cancellation is possible with 4-lane structure of 4G backplane. 18 Noise Margin (db) w/o Crosstalk Canceller With Crosstalk Canceller 6dB Margin TYCO Molex 8 INTEL Additions More than 6dB improvement can be made with crosstalk canceller. Another ~db improvement can be with optional FEC. 6dB margin is feasible. 13
14 Summary Performance of 1GBASE-KR is estimated with key IC implementation impairments. - Performance is marginal with the industrial grade backplane channels. - Solution as crosstalk canceller. - Even better margin can be obtained by with optional FEC. - Recommend HSSG to define additional channel bundling parameters to address crosstalk. Therefore, 1GBASE-KR is a good fit as a baseline for 4G system. 14
100G Signaling Options over Backplane Classes
100G Signaling Options over Backplane Classes IEEE P802.3bj January 2012 Newport Beach FutureWei Hiroshi Takatori Hiroshi.Takatori@huawei.com Contributors and Supporters Albert Vareljian Sanjay Kasturia,
More informationFeasibility of 40/100G Heterogeneous System based on Channel Data
Feasibility of 40/100G Heterogeneous System based on Channel Data Jan 2008 Technology Hiroshi Takatori Hiroshi.Takatori@.us 1 Outline Generalized methodology for feasibility analysis of heterogeneous (electro-optical)
More information40 GbE Over 4-lane 802.3ap Compliant Backplane
40 GbE Over 4-lane 802.3ap Compliant Backplane, Intel Contributors: Ted Ballou, Intel Ilango Ganga, Intel Robert Hays, Intel IEEE 802.3 HSSG November 2007 Agenda 40 GbE proposition 40 GbE system configuration
More informationSimulation Results for 10 Gb/s Duobinary Signaling
Simulation Results for 10 Gb/s Duobinary Signaling Populating the Signaling Ad Hoc Spreadsheet IEEE 802.ap Task Force Atlanta March 15-17, 2005 802.AP Backplane Ethernet Contributors Vitesse Majid Barazande-Pour
More informationFeasibility of 30 db Channel at 50 Gb/s
Feasibility of 30 db Channel at 50 Gb/s Ali Ghiasi Ghiasi Quantum LLC 50 GbE & NGOATH Plenary Mee>ng March 16, 2016 List of supporters q Upen Reddy Kare> Cisco q Vipul BhaN Inphi q James Fife - etoups
More informationIEEE 802.3ap Backplane Ethernet Overview
IEEE 802.3ap Backplane Ethernet Overview T10 SAS Adhoc Meeting Houston May 25 26, 2005 Ali Ghiasi aghiasi@broadcom.com 1 History of Backplane Ethernet Ethernet previously did not standardize backplane
More informationIBIS-AMI Modeling and Simulation of 56G PAM4 Link Systems
IBIS-AMI Modeling and Simulation of 56G PAM4 Link Systems Hongtao Zhang, hongtao@xilinx.com Fangyi Rao, fangyi_rao@keysight.com Xiaoqing Dong, dongxiaoqing82@huawei.com Geoff Zhang, geoffz@xilinx.com Outline
More informationCOM Analysis on Backplane and Cu DAC Channels
COM Analysis on Backplane and Cu DAC Channels Ali Ghiasi Ghiasi Quantum LLC IEEE 802.3cd Task Force Mee@ng Whistler May 25, 2016 Overview q Follow on the Macau presenta@on q Inves@ga@ng COM analysis on
More informationUpdated 50G PAM4 C2M Simulations
Updated 50G PAM4 C2M Simulations Ali Ghiasi Ghiasi Quantum LLC IEEE 802.3bs Electrical Adhoc Meeting Feb 20th, 2017 Contributor/Supporter q Rich Mellitz Samtec q Yasuo Hidaka Fujitsu A. Ghiasi IEEE 802.3
More information5 GT/s and 8 GT/s PCIe Compared
5 GT/s and 8 GT/s PCIe Compared Bent Hessen-Schmidt SyntheSys Research, Inc. Copyright 2008, PCI-SIG, All Rights Reserved 1 Disclaimer The material included in this presentation reflects current thinking
More informationModulation Schemes Link Budget Analysis under BCI Interference for RTPGE
Modulation Schemes Link Budget Analysis under BCI Interference for RTPGE January 2014 IEEE Reduced Twisted Pair Gigabit Ethernet Benson Huang, Albert Kuo Realtek Semiconductor Corp. Outline SNR Calculation
More informationUpdated 802.3cb Backplane Channel Analysis and PHY proposals
Updated 802.3cb Backplane Channel Analysis and PHY proposals Peter Wu, Jin Zhang, Marvell Semiconductor IEEE 802.3cb March 2016 Plenary Meeting, Macau 1 Supporters Anthony Calbone, Seagate Technology Richard
More informationIssue with 50G PAM4 C2M Specification
Issue with 50G PAM4 C2M Specification Ali Ghiasi Ghiasi Quantum LLC IEEE 802.3bs Electrical Adhoc Meeting Jan 23rd, 2017 Contributor/Supporter q Rich Mellitz Samtec q Yasuo Hidaka Fujitsu A. Ghiasi IEEE
More informationApplication Note. PCIE-RA Series Final Inch Designs in PCI Express Applications Generation GT/s
PCIE-RA Series Final Inch Designs in PCI Express Applications Generation 3-8.0 GT/s Copyrights and Trademarks Copyright 2012, Inc. COPYRIGHTS, TRADEMARKS, and PATENTS Final Inch is a trademark of, Inc.
More informationProposal for modeling advanced SERDES
Proposal for modeling advanced SERDES IBM, Cadence June 2006 1 CADENCE DESIGN SYSTEMS, INC. Presenters, Contributors Presenters / Contributors 1. Joe Abler IBM Systems & Technology Group High Speed Serial
More informationApplication Note. PCIE-EM Series Final Inch Designs in PCI Express Applications Generation GT/s
PCIE-EM Series Final Inch Designs in PCI Express Applications Generation 3-8.0 GT/s Copyrights and Trademarks Copyright 2015, Inc. COPYRIGHTS, TRADEMARKS, and PATENTS Final Inch is a trademark of, Inc.
More informationPCIEC PCI Express Jumper High Speed Designs in PCI Express Applications Generation GT/s
PCIEC PCI Express Jumper High Speed Designs in PCI Express Applications Generation 3-8.0 GT/s Mated with PCIE-RA Series PCB Connectors Copyrights and Trademarks Copyright 2015, Inc. COPYRIGHTS, TRADEMARKS,
More information100GEL C2M Channel Analysis Update
100GEL C2M Channel Analysis Update Jane Lim, Cisco Pirooz Tooyserkani, Cisco Upen Reddy Kareti, Cisco Joel Goergen, Cisco Marco Mazzini, Cisco 9/5/2018 IEEE P802.3ck 100Gb/s, 200Gb/s, and 400Gb/s Electrical
More informationSEAM-RA/SEAF-RA Series Final Inch Designs in PCI Express Applications Generation GT/s
SEAM-RA/SEAF-RA Series Final Inch Designs in PCI Express Applications Generation 3-8.0 GT/s Copyrights and Trademarks Copyright 2011 Samtec, Inc. Developed in conjunction with Teraspeed Consulting Group
More information10G Ethernet Over Structured Copper Cabling
I T I n f r a s t r u c t u r e S o l u t i o n s Note: The following technical article was current at the time it was published. However, due to changing technologies and standards updates, some of the
More informationHigh-Speed Jitter Testing of XFP Transceivers
White Paper High-Speed Jitter Testing of XFP Transceivers By Andreas Alpert Abstract Jitter is a key performance factor in high-speed digital transmission systems, such as synchronous optical networks/synchronous
More informationSpecifying Crosstalk. Adam Healey Agere Systems May 4, 2005
Specifying Crosstalk Adam Healey Agere Systems May 4, 2005 Proposal Use the power-sum crosstalk (MDNEXT and MDFEXT) limits proposed by D Ambrosia et al. [1] as the normative specification for crosstalk.
More informationCOM 2.40 with 100GEL Configurations Suggestions
COM 2.40 with 100GEL Configurations Suggestions Richard Mellitz, Samtec July 25, 2018, Ad Hoc IEEE 802.3 100 Gb/s, 200 Gb/s, and 400 Gb/s Electrical Interfaces Task Force 1 COM 2.40 Adds long FFE capability
More informationSequence Estimators with Block Termination in the presence of ISI
Hardware implementation i of Sequence Estimators with Block Termination in the presence of ISI Presentation to IEEE 802.3bj Arash Farhood Cortina Systems Joel Goergen Cisco Elizabeth Kochuparambil - Cisco
More informationATCA Platform Considerations for Backplane Ethernet. Aniruddha Kundu Michael Altmann Intel Corporation May 2004
ATCA Platform Considerations for Backplane Ethernet Aniruddha Kundu Michael Altmann Intel Corporation May 2004 IEEE 802.3ap Back Plane Ethernet TF Interim meeting May 2004 1 Introduction This presentation
More information40 and 100 Gigabit Ethernet Consortium Clause 86 40GBASE-SR4 and 100GBASE-SR10 PMD Test Suite v0.1 Technical Document
40 and 100 Gigabit Ethernet Consortium Clause 86 40GBASE-SR4 and 100GBASE-SR10 PMD Test Suite v0.1 Technical Document Last Updated: March 26, 2013 10:00am 40 and 100 Gigabit Ethernet Consortium 121 Technology
More informationComparison Between Equalization, COM Package Models, and COM For 100G Base KR Channels
Comparison Between Equalization, COM Package Models, and COM For 100G Base KR Channels Richard Mellitz, Samtec September 018 1 Table of Contents Experiment using seven 100G-Base-KR channel models For three
More information100Gbps/Lane Electrical Signaling. Loop-Timed Configurations. Ramin Farjadrad SVP of R&D
100Gbps/Lane Electrical Signaling Loop-Timed Configurations Ramin Farjadrad SVP of R&D Dual Duplex Definition Single Duplex (SD): Tx Rx Transmit data Receive data Rx Tx Dual Duplex (DD): Transmit/Receive
More informationUpdate on technical feasibility for PAM modulation
Update on technical feasibility for PAM modulation Gary Nicholl, Chris Fludger Cisco IEEE 80.3 NG00GE PMD Study Group March 0 PAM Architecture Overview [Gary Nicholl] PAM Link Modeling Analysis [Chris
More informationCEI-28G-VSR Channel Simulations, Validation, & Next Steps. Nathan Tracy and Mike Fogg May 18, 2010
CEI-28G-VSR Channel Simulations, Validation, & Next Steps Nathan Tracy and Mike Fogg May 18, 21 Summary of Contribution Updated information showing Tyco Electronics 25/28Gbps first generation modular interconnect
More information40 AND 100 GIGABIT ETHERNET TESTING SERVICE
40 AND 100 GIGABIT ETHERNET TESTING SERVICE Clause 95 100GBASE-SR4 PMD Test Plan Version 1.1 Technical Document Last Updated: January 23, 2018 40 and 100 Gigabit Ethernet Testing Service 21 Madbury Road,
More information400GBase-LR8: A Proposal for 10 km Objective Using 50 Gb/s PAM4 Signaling
400GBase-LR8: A Proposal for 10 km Objective Using 50 Gb/s PAM4 Signaling Ali Ghiasi Ghiasi Quantum LLC IEEE 802.3bs Task Force Berlin March 2015 1 List of supporters! Mike Furlong Clariphy! Sudeep Bhoja
More informationAn Overview of High-Speed Serial Bus Simulation Technologies
An Overview of High-Speed Serial Bus Simulation Technologies Asian IBIS Summit, Beijing, China September 11, 27.25.2.15.1.5 -.5 -.1 Arpad Muranyi arpad_muranyi@mentor.com Vladimir Dmitriev-Zdorov -.15
More informationPCI Express 3.0 Characterization, Compliance, and Debug for Signal Integrity Engineers
PCI Express 3.0 Characterization, Compliance, and Debug for Signal Integrity Engineers - Transmitter Testing - Receiver Testing - Link Equalization Testing David Li Product Marketing Manager High Speed
More informationIBIS-AMI Model Simulations Over Six EDA Platforms
IBIS-AMI Model Simulations Over Six EDA Platforms Romi Mayder, romi.mayder@xilinx.com Ivan Madrigal, ivan.madrigal@xilinx.com Brandon Jiao, brandon.jiao@xilinx.com Hongtao Zhang, hongtao.zhang@xilinx.com
More informationStatus Update - SDD21 & SDD11/22 Model Development
Status Update - SDD21 & SDD11/22 Model Development John DAmbrosia, Tyco Electronics Matt Hendrick, Intel January 2005 1 Acknowedgements Rich Mellitz, Intel Steve Krooswyk, Intel Mike Altmann, Intel Yves
More informationAdvanced Jitter Analysis with Real-Time Oscilloscopes
with Real-Time Oscilloscopes August 10, 2016 Min-Jie Chong Product Manager Agenda Review of Jitter Decomposition Assumptions and Limitations Spectral vs. Tail Fit Method with Crosstalk Removal Tool Scope
More informationIEEE-100GBASE-KR4/CR4, v3
COMPLIANCE STATEMENT 1. Specification IEEE-100GBASE-KR4/CR4, v3 Specification Title: Standard Body: Standard Name: Specification Owner: Warning Margin: IEEE 802.3 100GBASE-KR4/CR4 IEEE 100GBASE-KR4, 100GBASE-CR4
More informationKeysight Technologies IBIS-AMI Based Link Analysis of Realistic 56G PAM4 Channels
Keysight Technologies IBIS-AMI Based Link Analysis of Realistic 56G PAM4 Channels White Paper This white paper was first published at DesignCon in January, 2016. Reprinted with permission from DesignCon.
More informationAutomotive Ethernet BroadR-Reach
Automotive Ethernet BroadR-Reach Agilent PHY Compliance Solutions 1 Last update 2013/07/25 (YS) Agenda BroadR-Reach Overview Transmitter Testing Link Segment Testing 2 BroadR-Reach Applications 3 Connectivity
More informationTechnical Feasibility of optical PMDs with RS FEC
Technical Feasibility of optical PMDs with RS FEC Yu Xu, Xinyuan Wang HUAWEI TECHNOLOGIES CO., LTD. IEEE 802.3 50GE & NGOATH Study Group Background and Introduction In 50 Gb/s Ethernet Over a Single Lane
More informationRaj Kumar Nagpal, R&D Manager Synopsys. Enabling Higher Data Rates and Variety of Channels with MIPI D-PHY
Raj Kumar Nagpal, R&D Manager Enabling Higher Data Rates and Variety of Channels with MIPI D-PHY Agenda Design motivation MIPI D-PHY evolution Summary of MIPI D-PHY specification MIPI channel evolution
More informationUSB Type-C Active Cable ECN
USB Type-C Active Cable ECN Christine Krause Active Cable WG Chair (Sponsored by Intel Corporation) USB Developer Days 2017 Taipei, Taiwan October 24 25, 2017 1 Introduction Scope Requirements for active
More informationSHF Communication Technologies AG
SHF Communication Technologies AG Wilhelm-von-Siemens-Str. 23 Aufgang D 12277 Berlin Marienfelde Germany Phone ++49 30 / 772 05 10 Fax ++49 30 / 753 10 78 E-Mail: sales@shf.biz Web: http://www.shf.biz
More information400G PAM4 The Wave of the Future. Michael G. Furlong - Senior Director, Product Marketing
400G The Wave of the Future Michael G. Furlong - Senior Director, Product Marketing mfurlong@inphi.com ECOC 2017 100G is Ramping in the Cloud 100G Now Shipping (~2H2016) Numerous Market Reports Millions
More informationPredicting BER with IBIS-AMI: experiences correlating SerDes simulations and measurement
Predicting BER with IBIS-AMI: experiences correlating SerDes simulations and measurement Todd Westerhoff (SiSoft) Mike Steinberger (SiSoft) Walter Katz (SiSoft) Barry Katz (SiSoft) Adge Hawes (IBM) Kent
More informationInfiniBand FDR 56-Gbps QSFP+ Active Optical Cable PN: WST-QS56-AOC-Cxx
Data Sheet PN: General Description WaveSplitter s Quad Small Form-Factor Pluggable Plus (QSFP+) active optical cables (AOC) are highperformance active optical cable with bi-directional signal transmission
More informationERL for Parameter Update
ERL for Parameter Update Richard Mellitz, Samtec 02-21-2018 IEEE 802.3 New Ethernet Applications Ad Hoc 1 ToC Review SNR ISI Clause 136 host transmitter and receiver DOE experiment SNR ISI comparison ERL
More informationT Q S 2 1 L H 8 X 8 1 x x
Specification Quad Small Form-factor Pluggable Plus QSFP+ TO 4xSFP+ AOC Ordering Information T Q S 2 1 L H 8 X 8 1 x x Distance Model Name Voltage Category Device type Interface LOS Temperature TQS-21LH8-X81xx
More informationin Synchronous Ethernet Networks
Jitter and Wander Measurements in Synchronous Ethernet Networks Andreas Alpert ITSF November 2008 Agenda Introduction ti Synchronous Ethernet Ji d W d A Jitter and Wander Aspects Test Applications in SyncE
More informationSignal Integrity Analysis for 56G-PAM4 Channel of 400G Switch
Signal Integrity Analysis for 56G-PAM4 Channel of 400G Switch Sophia Feng/Vincent Wen of Celestica sopfeng@celestica.com Asian IBIS Summit Shanghai, PRC November 13, 2017 Agenda Background 200GBASE-KR4
More informationSerial ATA Gen2 Jitter Tolerance Testing
Serial ATA Gen2 Jitter Tolerance Testing Abstract Guy Foster SyntheSys Research, Inc. February 21, 2006 SR-TN054 Serial ATA [i] is an increasingly common serial bus technology aimed at disk drive applications.
More informationTechnical Feasibility of 4x10G and 10x10G Electrical Interfaces
Technical Feasibility of 4x10G and 10x10G Electrical Interfaces IEEE 802.3 Higher Speed Study Group 16-19 July 2007 Lew Aronson Chris Cole lew.aronson@finisar.com chris.cole@finisar.com Outline SMF Transceiver
More informationIEEE P802.3bs 200 Gb/s and 400 Gb/s Ethernet to RevCom (conditional)
IEEE P802.3bs 200 Gb/s and 400 Gb/s Ethernet to RevCom (conditional) IEEE 802.3 Conditional approval requests September 2017 Page 1 IEEE P802.3bs 200 Gb/s and 400 Gb/s Ethernet to RevCom (conditional)
More informationChannels for Consideration by the Signaling Ad Hoc
Channels for Consideration by the Signaling Ad Hoc John D Ambrosia Tyco Electronics Adam Healey, Agere Systems IEEE P802.3ap Signaling Ad Hoc September 17, 2004 Two-Connector Topology N2 H B September,
More informationUsing RJ45 Category 7 Cabling for 2 Lane, 1 and 2.5Gbps Serial Data Transmission
Using RJ45 Category 7 Cabling for 2 Lane, 1 and 2.5Gbps Serial Data Transmission Test 8561 (Category 7, 2 lane) J Sawdy, Sr. SI Engineer 4/14/10 Forward The RJ45 connector is found in enterprise installations
More informationThe Future of Electrical I/O for Microprocessors. Frank O Mahony Intel Labs, Hillsboro, OR USA
The Future of Electrical I/O for Microprocessors Frank O Mahony frank.omahony@intel.com Intel Labs, Hillsboro, OR USA 1 Outline 1TByte/s I/O: motivation and challenges Circuit Directions Channel Directions
More informationTransmitter testing for MMF PMDs
Transmitter testing for MMF PMDs IEEE P802.3cd, San Diego, July 2016 Jonathan Ingham Foxconn Interconnect Technology Supporters Will Bliss (Broadcom) Ali Ghiasi (Ghiasi Quantum) Vasu Parthasarathy (Broadcom)
More informationPerformance Evaluation of Transcoding and FEC Schemes for 100 Gb/s Backplane and Copper Cable
Performance Evaluation of Transcoding and FEC Schemes for 100 Gb/s Backplane and Copper Cable IEEE 802.3bj Task Force Atlanta, November 8-10, 2011 Roy Cideciyan - Outline Error models at RS decoder input
More informationPCI Express 4.0. Electrical compliance test overview
PCI Express 4.0 Electrical compliance test overview Agenda PCI Express 4.0 electrical compliance test overview Required test equipment Test procedures: Q&A Transmitter Electrical testing Transmitter Link
More information40Gb/s QSFP+ Parallel Active Optical Cable (AOC) QSFP-40G-xxAOC. Product Specification
40Gb/s QSFP+ Parallel Active Optical Cable (AOC) QSFP-40G-XXAOC Product Specification Features 4 independent full-duplex channels Up to 11.2Gb/s data rate per channel QSFP+ MSA compliant Up to 100m transmission
More informationAchieving PCI Express Compliance Faster
Achieving PCI Express Compliance Faster Agenda PCIe Overview including what s new with Gen4 PCIe Transmitter Testing PCIe Receiver Testing Intro to Tektronix s PCIe Tx and Rx Test Solution PCIe Market
More informationECEN720: High-Speed Links Circuits and Systems Spring 2017
ECEN720: High-Speed Links Circuits and Systems Spring 2017 Lecture 1: Introduction Sam Palermo Analog & Mixed-Signal Center Texas A&M University Class Topics System and design issues relevant to high-speed
More informationSignal Integrity in Embedded Computer Applications
Signal Integrity in Embedded Computer Applications "SI for Embedded" by EyeKnowHow 02.03.2010 1 Agenda 1) Introduction 2) Crosstalk 3) Inter Symbol Interference (ISI) 4) Power Integrity 5) Resources "SI
More informationPCI Express Electrical Basics
PCI Express Electrical Basics Dean Gonzales Advanced Micro Devices Copyright 2015, PCI-SIG, All Rights Reserved 1 Topics PCI Express Overview Enhancements for 8GT/s Target Channels for the Specification
More informationCrosstalk Measurements for Signal Integrity Applications. Chris Scholz, Ph.D. VNA Product Manager R&S North America
Crosstalk Measurements for Signal Integrity Applications Chris Scholz, Ph.D. VNA Product Manager R&S North America Outline ı A brief history of crosstalk ı Introduction to crosstalk Definition of crosstalk
More informationRevisi&ng MCBHCB Requirements in Support of 50G/lane PAM4
Revisi&ng MCBHCB Requirements in Support of 50G/lane PAM4 Ali Ghiasi Ghiasi Quantum LLC IEEE 802.3cd Task Force Mee@ng San Diego July 26, 2016 Background q Comment 128 was submiked on P802.3bs dram 1.4
More informationReference Architecture Proposals and Channel Data
Reference Architecture Proposals and Channel Data Richard Mellitz, Samtec Howard Heck. Intel Contribution Acknowledgment: Oluwafemi Akinwale and Subas Bastola, Intel IEEE802.3 Plenary July 2018, San Diego,
More informationSHFP-2G-B Gb/s BiDi SFP Transceiver Hot Pluggable, Simplex LC/SC, +3.3V, Single mode, 20km, 0~70 C 1310/1550nm or 1310/1490nm DFB/PIN
SHFP-2G-B20 2.5Gb/s BiDi SFP Transceiver Hot Pluggable, Simplex LC/SC, +3.3V, Single mode, 20km, 0~70 C 1310/1550nm or 1310/1490nm DFB/PIN SHFP-2G-B20 high performance, cost-effective 2.5G BiDi SFP transceiver
More informationADS USB 3.1 Compliance Test Bench
ADS 2016.01 USB 3.1 Compliance Test Bench Notices Keysight Technologies, Inc. 1983-2016 1400 Fountaingrove Pkwy., Santa Rosa, CA 95403-1738, United States All rights reserved. No part of this documentation
More informationVirtex-6 FPGA GTX Transceiver Characterization Report
Virtex-6 FPGA GTX Transceiver Characterization Report PCI Express 2.0 (2.5 and 5.0 Gb/s) Electrical Standard Xilinx is disclosing this user guide, manual, release note, and/or specification (the Documentation
More informationUsing IBIS-AMI in the Modeling of Advanced SerDes Equalization for Serial Link Simulation
Using IBIS-AMI in the Modeling of Advanced SerDes Equalization for Serial Link Simulation CDNLive Boston August 2013 Mark Marlett and Mahesh Tirupattur, Analog Bits Ken Willis and Kumar Keshavan, Cadence
More informationOIF CEI-56G Project Activity
OIF CEI-56G Project Activity Progress and Challenges for Next Generation 400G Electrical Links David R Stauffer Kandou Bus, SA OIF Physical & Link Layer Working Group Chair June 12, 2014 Electrical Implementation
More informationSuccessfully negotiating the PCI EXPRESS 2.0 Super Highway Towards Full Compliance
the PCI EXPRESS 2.0 Super Highway Towards Full Compliance Page 1 Agenda Introduction PCIe 2.0 changes from 1.0a/1.1 Spec 5GT/s Challenges Error Correction Techniques Test tool and fixture changes Agilent
More informationAgilent Technologies Advanced Signal Integrity
Agilent Technologies Advanced Signal Integrity Measurements for Next Generation High Speed Serial Standards Last Update 2012/04/24 (YS) Appendix VNA or TDR Scope? ENA Option TDR Overview USB 3.0 Cable/Connector
More informationLatency and FEC options for 25G Ethernet
Latency and FEC options for 25G Ethernet Adee Ran Intel Corp. August 2014 August 12, 2014 IEEE 802.3 25 Gb/s Ethernet Study Group 1 Goals Explore FEC encoding/decoding options Discuss FEC gain/latency
More informationIEEE Gb/s, 100 Gb/s, and 200 Gb/s Ethernet Task Force
1 IEEE 802.3 50 Gb/s, 100 Gb/s, and 200 Gb/s Ethernet Task Force Vittal Balasubramanian, Dell Yasuo Hidaka, Fujitsu Upen Reddy Kareti, Cisco Erdem Matoglu, Amphenol-TCS Jim Nadolny, Samtec Rick Rabinovich,
More informationTektronix Innovation Forum
Tektronix Innovation Forum Enabling Innovation in the Digital Age DisplayPort 1.2 Spec Updates and overview of Physical layer conformance testing Presenter: John Calvin DisplayPort 1.2 Spec Updates Agenda
More information100G SWDM4 MSA Technical Specifications Optical Specifications
100G SWDM4 MSA Technical Specifications Specifications Participants Editor David Lewis, LUMENTUM The following companies were members of the SWDM MSA at the release of this specification: Company Commscope
More informationBER- and COM-Way of Channel- Compliance Evaluation: What are the Sources of Differences?
DesignCon 016 BER- and COM-Way of Channel- Compliance Evaluation: What are the Sources of Differences? Vladimir Dmitriev-Zdorov, Mentor Graphics vladimir_dmitriev-zdorov@mentor.com, 70-494-1196 Cristian
More informationModeling MultiGigabit FPGA Channels with Agilent ADS 2008
Modeling MultiGigabit FPGA Channels with Agilent ADS 2008 Andy Turudic Sr. Manager, High-End FPGAs Altera aturudic@altera.com Amolak Badesha Field Applications Engineer - Agilent 2008 Altera Corporation
More informationOptimal Management of System Clock Networks
Optimal Management of System Networks 2002 Introduction System Management Is More Challenging No Longer One Synchronous per System or Card Must Design Source-Synchronous or CDR Interfaces with Multiple
More informationPPI MCB HCB Detail Specifications and Connector Pinout
PPI MCB HCB Detail Specifications and Connector Pinout IEEE P802.3ba New Orleans Jan 13 2009 Ali Ghiasi Broadcom Corporation aghiasi@broadcom.com 802.3 HSSG 1/15 Nov 13, 2007 1 Key Items Require Further
More informationUsing Chiplets to Lower Package Loss. IEEE Gb/s Electrical Lane Study Group February 26, 2018 Brian Holden, VP of Standards Kandou Bus SA
1 Using Chiplets to Lower Package Loss IEEE 802.3 100 Gb/s Electrical Lane Study Group February 26, 2018 Brian Holden, VP of Standards Kandou Bus SA Chiplet Technology Big, 70mm packages are routine A
More informationMDI for 4x25G Copper and Fiber Optic IO. Quadra (CFP4 proposal) Connector System
MDI for 4x25G Copper and Fiber Optic IO Quadra (CFP4 proposal) Connector System Nov 7, 2011 Nathan Tracy, TE Connectivity Tom Palkert, Molex 4x25Gb/s MDI Potential Requirements Critical Needs: Excellent
More informationAgenda. Time Module Topics Covered. 9:30 11:00 Wireless Technologies that Enable the Connected Car
Agenda Time Module Topics Covered 9:30 11:00 Wireless Technologies that Enable the 11:00 12:00 V2X: Car-to-X Communication (802.11 and LTE-V) Cellular, Wifi, Automotive Radar, BlueTooth, GNSS, NFC, WPC/TPS/RKE
More informationAirMax VSe High Speed Backplane Connector System
AirMax VSe High Speed Backplane Connector System July 2012 FCI Customer Presentation For External Use Where will AirMax VSe connectors be used & Why? More bandwidth density is being demanded from equipment
More informationMaximising Serial Bandwidth And Signal Integrity In FPGAs
Maximising Serial Bandwidth And Signal Integrity In FPGAs Francesco Contu High Speed IO specialist, EMEA South francescocontu@xilinxcom Agilent High Speed Digital Design & Validation Seminars 2012 Agenda
More informationDYNAMIC LINE MANAGEMENT FOR VECTORING SCENARIOS
DYNAMIC LINE MANAGEMENT FOR VECTORING SCENARIOS STRATEGIC WHITE PAPER Operators are embracing vectoring technology as a means to extend and protect their legacy investments in copper access. However, the
More informationOptions to fix the low frequency jitter (gearbox) issue. Piers Dawe Mellanox Adee Ran Intel Casper Dietrich Mellanox
Options to fix the low frequency jitter (gearbox) issue Piers Dawe Mellanox Adee Ran Intel Casper Dietrich Mellanox History: IEEE 802.3 CAUI-10 to 100GBASE-LR4 jitter conversion CAUI-10 10 GBd, NRZ 100GBASE-LR4/SR4
More information40GBASE-T Cabling channel MDI-to-MDI
40GBASE-T Cabling channel MDI-to-MDI Chris DiMinico MC Communications/ Panduit cdiminico@ieee.org 1 802.3bq (NGBASE-T) Channel Modeling Ad Hoc 802.3bq 40GBASE-T Channel Modeling Ad Hoc initiated May Interim
More information45. Management Data Input/Output (MDIO) Interface
Draft Amendment to IEEE Std. 0. January, 00 0. Management Data Input/Output (MDIO) Interface Editor's notes: To be removed prior to final publication.. This clause contains all modifications to clause
More informationFeatures: Applications: Description: Product Datasheet
KRN-SF-(X)SM020G - 1.25Gb/s 20Km SFP Transceiver Hot Pluggable, Duplex LC, +3.3V, 1310nm, FP-LD, Single-mode KRN-SF-(X)SM020GD - 1.25Gb/s 20Km SFP Transceiver Hot Pluggable, Duplex LC, +3.3V, 1310nm, FP-LD,
More informationVerification of ICN Usability in Characterizing System Crosstalk
Asian IBIS Summit Shanghai, P.R. China November 9, 212 Verification of ICN Usability in Characterizing System Crosstalk Dongxiaoqing, Huangchunxing www.huawei.com HUAWEI TECHNOLOGIES CO., LTD. ICN Definition
More information100GbE Architecture - Getting There... Joel Goergen Chief Scientist
100GbE Architecture - Getting There... Joel Goergen Chief Scientist April 26, 2005 100GbE Architecture - Getting There Joel Goergen Force10 Networks joel@force10networks.com Subject : 100GbE Architecture
More informationComparison of BER Estimation Methods which Account for Crosstalk
Comparison of BER Estimation Methods which Account for Crosstalk As presented at DesignCon 2009 Co-authored by: Michael Steinberger, Signal Integrity Software, Inc. msteinb@sisoft.com Barry Katz, Signal
More informationSHFP-GE-EX. 1.25Gb/s SFP Transceiver Hot Pluggable, Duplex LC, +3.3V, 1550nm DFB/PIN, Single mode, 40km, 0~70 C
SHFP-GE-EX 1.25Gb/s SFP Transceiver Hot Pluggable, Duplex LC, +3.3V, 1550nm DFB/PIN, Single mode, 40km, 0~70 C SHFP-GE-EX high performance, cost effective transceiver complies with the Small Form Factor
More informationCost Effective Solution for Receiver Characterization
12.5 Gb/s Programmable Pattern Generator Cost Effective Solution for Receiver Characterization Product Highlights 24Mb pattern memory supports virtually any pattern Integrated two tap de-emphasis Fully
More information10-Gigabit Ethernet DWDM OTN Optical Interface Specifications
1-Gigabit Ethernet DWDM OTN Optical Interface Specifications M12 router and T Series routers support the following 1-Gigabit Ethernet DWDM OTN PIC transceiver. To determine DWDM OTN support, see the cables
More informationAgilent N5393B PCI Express Automated Test Application
Agilent N5393B PCI Express Automated Test Application Compliance Testing Methods of Implementation Agilent Technologies Notices Agilent Technologies, Inc. 2004-2009 No part of this manual may be reproduced
More information