FPGA Implementation of CORDIC Algorithms for Sine and Cosine Generator
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1 The 5th Internatonal Conference on Electrcal Engneerng and Informatcs 25 August -, 25, Bal, Indonesa FPGA Implementaton of CORDIC Algorthms for Sne and Cosne Generator Antonus P. Renardy, Nur Ahmad, Ashbr A. Fadla, Naufal Shdq, Tro Adono Department of Electrcal Engneerng, School of Electrcal Engneerng and Informatcs Bandung Insttute of Technology, Jl. Ganesha No. Bandung, 432, Indonesa Emal: Abstract Trgonometrc-related calculatons whch are wdely found n a broad range of applcatons can be performed by usng COordnate Rotaton DIgtal Computer (CORDIC) algorthm. CORDIC s often utlzed n the absence of hardware multpler snce ths algorthm requres only addton, subtracton, bt shftng, and lookup table. Ths paper provdes an mplementaton of conventonal CORDIC algorthm wth ppelned archtecture and Vrtually Scalng-Free Adaptve (VSFA) CORDIC. All desgns are mplemented n Verlog and syntheszed by usng Altera Quartus II wth FPGA DE2 as target board. The ppelned CORDIC consumes,3 logc element, ns latency, and 42.7 MHz mamum frequency, whle VSFA CORDIC utlzes 2,9 logc element, ns latency, and MHz mamum frequency. Both desgns are used to generate sne and cosne wave between π and π whch result n mamum error of for ppelned CORDIC and for VSFA CORDIC. Based on performance comparson n term of area multpled by delay (A T ), our ppelned CORDIC s superor among other desgns. Keywords FPGA, CORDIC, VSFA, Sne and Cosne Generator. I. INTRODUCTION Sne and cosne are the basc functons whch can be derved from any comple functons used n a broad range of applcatons such as dgtal sgnal processng, wreless communcaton, bometrcs, robotcs, etc []. Several methods est to generate hardware that performs sne and cosne calculatons, whch are Lookup Table (LUT), Maclaurn seres, and CORDIC. Table lookup method utlzes blocks of memory whch store values of the functon to be computed for every possble nput arguments. Ths method s relatvely smple to be employed snce no specfc calculatons are requred, relyng only on the values stored on the table. However, the number of table entres requred wll rse eponentally as the number of bts, whch are used to represent the output argument, rse [2]. Ths wll result n larger area requred for hardware mplementaton. MacLaurn seres s used to represent a functon as nfnte sum of ts dervatves derved from Taylor seres that s evaluated at zero. In practce, the number of terms n the seres are determned based on the requred accuracy [3]. For applcaton that requres mamum error to be 2 8 = , the number of terms requred s N =9whch corresponds to mamum error of Consequently, nne eponentatons, eght addtons, and nne factoral operatons need to be carred out to produce the functon. For hardware mplementaton, the values factoral operatons can be stored on a lookup table snce these are fed regardless of the nput argument of the functon. However, ths wll also consume larger area as the number of bts ncreases. COordnate Rotaton DIgtal Computer (CORDIC), nvented by J. E. Volder n 959 [4], s an algorthm that can be used to perform trgonometrc-related calculatons. By changng some parameters, CORDIC can also be used n wde varety of elementary transcendental functon nvolvng eponentals, logarthms, and square roots [5]. CORDIC s smple and effcent snce ths algorthm requres only addton, subtracton, bt shftng, and table lookup. Ths leads to an effcent and low-cost mplementaton wth generally faster speed than most hardware approaches. Several archtectures est n order to keep the requrements and constrants of dfferent applcatons. Iteratve archtecture provdes hardware mplementaton wth mnmum sze wth throughput as the tradeoff, whle parallel and ppelned CORDIC offers hgh-speed and hgh-throughput computaton. Ths paper provdes a prototype for mplementng CORDIC algorthm wth ppelned archtecture and Vrtually Scalng Free Adaptve (VSFA) CORDIC. In addton, both desgns are used for sne and cosne calculaton. The rest of ths paper s organzed as follows. Secton II eplans conventonal CORDIC and Vrtually Scalng Free Adaptve (VSFA) CORDIC algorthms. Secton III descrbes the mplementaton of both CORDIC algorthm. Secton IV shows the smulaton result and performance evaluaton. Fnally, the conclusons are provded n Secton V. II. A. Conventonal CORDIC CORDIC ALGORITHM Conventonal CORDIC algorthm s derved from rotaton of a vector [ y ] T n Cartesan coordnate whch can be epressed n (), where [ y ] T s the fnal vector produced after rotaton and θ s the target angle of rotaton. By factorng out the cosne functon, we can obtan (2). cos(θ) sn(θ) y = () sn(θ) cos(θ) y [ ] [ ][ ] tan(θ) y = cos(θ) (2) tan(θ) y
2 CORDIC employs teraton n whch the angle θ s epressed as summaton of elementary rotaton angles α whch s defned n (3), where b s the bt precson of the angle argument and σ the drecton of the rotaton, whch can only be or. The elementary rotatonal angle α s restrcted to have only certan values as as shown n (4). b θ = σ α (3) = α =tan (2 ) (4) The fnal vector produced by teraton can be epressed n (5) by substtutng (3) nto (2) wth defnton n (4). The remanng angle n each teraton s shown n (6). [ ] b y = cos(α ) = [ σ 2 σ 2 ][ y ] (5) z + = z + σ 2 (6) In rotaton mode, each teraton wll decrease the angle component (z ) approachng zero, whle n vectorng mode the ordnate (y ) s made to be zero. Ths s acheved by ether rotatng the vector clockwse or counter-clockwse. By ntalzng the three CORDIC parameters (,y,z ), dfferent output can be produced. For nstance, by settng =, y =and z = π/2, each teraton wll make and y closer to cos(π/2) and sn(π/2) respectvely. B. Vrtually Scalng-Free Adaptve CORDIC Unlke the conventonal CORDIC whch reles on rotaton on both drecton, Vrtually Scalng-Free Adaptve CORDIC rotates only on one drecton, ether t s clockwse or counterclockwse. The elementary rotatonal angle chosen s suffcently small enough to be epressed as sn(α ) = α =2 (7) Ths poses another condton for the algorthm. Let us consder the epanson of sne and cosne functon n the form of polynomal seres as follows sn(α )=α α3 3! + α5 5! (8) cos(α )= α2 2! + α4 (9) 4! Usng the appromaton of α =2, we can rewrte as sn(α )= ! cos(α )= 2 2 2! ! ! () () To make () and () comply wth the appromaton n (7), only the frst term of the epanson of sne functon remans, whle t s the frst and second term for the cosne functon, leavng all other terms reduced to zero. From the largest term that s neglected on both functon, t can be nferred that 2 3 3! =2 (3+log 2 6) =2 ( ) 2 b (2) snce rght shftng by more than b bts wll result n zero, assumng the mplementaton s done on b-bts data. Equaton (2) also means that b = p (3) 3 wth the upper lmt b for the same reason. Therefore, () can be wrtten as (4). It s clear that, unlke (5), no scalng coeffcent appears, hence the name scalngfree. It can be noted that (4) can also be realzed n the same manner, dfferng only n addtonal adder and shfter. [ ] b [ ][ ] 2 (2+) 2 y = 2 2 (2+) (4) y =p The largest angle that can be computed through ths method s only ± 7., far less than conventonal CORDIC (99.9 ) [6]. Thus, doman-foldng has to be employed n order to be able to compute full crcle. The method s to dvde each quadrant nto four doman equally, each havng angular span of π/8. Consder the frst quadrant, n whch the target angle can le n one of the four doman: A ([,π/8)), B ([π/8,π/4)), C ([π/4, 3π/8)), and D ([3π/8,π/2)). We can epress θ n terms of another angle φ: θ = φ n doman A θ = π/4 φ n doman B θ = π/4+φ n doman C θ = π/2 φ n doman D (5) By substtutng (5) to (), the CORDIC equaton operaton on nput vector [ y ] T n each doman can be epressed as: fa cos(φ) sn(φ) = y fa sn(φ) cos(φ) y () [ ] [ ][ ] fb = y cos(φ)+sn(φ) (cos(φ) sn(φ)) fb 2 (cos(φ) sn(φ)) cos(φ)+sn(φ) y (7) [ ] [ ][ ] fb = y cos(φ)+sn(φ) (cos(φ) sn(φ)) fb 2 (cos(φ) sn(φ)) cos(φ)+sn(φ) y (8) fd sn(φ) cos(φ) = y fd cos(φ) sn(φ) y (9) where f denotes the fnal vector from CORDIC operatons wth target angle lyng n respectve doman. Thus, by usng the epresson of CORDIC rotaton for postve and negatve angle φ and φ: + cos(φ) sn(φ) y = (2) + sn(φ) cos(φ) y cos(φ) sn(φ) y = (2) sn(φ) cos(φ) y Equaton () - (9) can be epressed as: fa = y fa = y φ = θ [ ] fb = y [ + ] fb = y + φ = π/4 θ (22) (23) 2
3 [ ] fc = 2 + y [ ] fc = 2 + y φ = θ π/4 fd = y + y fd = + φ = π/2 θ (24) (25) It shows that CORDIC operaton n doman B, C, and D can be obtaned from CORDIC operaton n doman A, or we could say that doman B, C, and D s folded back to doman A. Also, as the consequence of doman foldng operaton, an addtonal scale factor / 2 for doman B and C appears. Thus, the addtonal hardwares are requred to mplement ths scale factor, whch can be realzed by smple shft and add operaton. Epresson for doman foldng n other quadrant are summarzed n Table I. TABLE I. DOMAIN FOLDING RESULTS OF CORDIC ROTATOR FOR DIFFERENT QUADRANTS Range of Target Angle y [,π/8) fa y fa [π/8,π/4) fb y fb [π/4, 3π/8) fc y fc [3π/8,π/2) fd y fd [π/2, 5π/8) y fa fa [5π/8, 3π/4) y fb fb [3π/4, 7π/8) y fc fc [7π/8,π) y fd fd [π, 9π/8) fa y fa [9π/8, 5π/4) fb y fb [5π/4, π/8) fc y fc [π/8, 3π/2) fd y fd [3π/2, 3π/8) y fa fa [3π/8, 7π/4) y fc fb [7π/4, 5π/8) y fd fc [5π/8, 2π) y fb fd In order to calculate cosne and sne value, the nput angle are frst processed n Quadrant Detector. Ths block has three nputs whch corresponds to the nput argument of CORDIC rotaton epressons (, y, z). The and y port of ths block are set to 36E and. Ths s necessary n order to acheve the fnal vector n the form of [cos θ sn θ] T wthout the need of addtonal post-processng. The output of ths block s the approprate, y, and z argument wth respect to the quadrant of the target angle, as shown n Fgure 2. 2 X Y Output Regster Angle Z Quadrant Detector Xo Yo Zo D Dy Dz Input Regster Q Qy Qz CORDIC Core Xo Yo Zo X Y Z D Dy Dz Q Qy Qz Clk Cos Sn III. HARDWARE IMPLEMENTATION Fg.. Top level module of ppelned CORDIC A. Bt Wdth and Data Format In order to meet desgn specfcaton of 2 8 accuracy and consderng the angle range of nput argument to be [ π, π], -bt wde datapath wth sgned fed-pont number representaton s chosen. However, for the Vrtually Scalng- Free Adaptve CORDIC, angle nput argument s 7-bt wde sgned fed-pont wth data format. Ths s due the fact that the crcut s desgned to compute angle rangng from to 2π. Ths data format s defned n Table II. TABLE II. FIXED POINT DATA FORMAT Archtecture Sgn Numeral Fractonal Ppelned CORDIC bt 2 bts 3 bts VSFA CORDIC bt 3 bts 3 bts X Y (Z<-p/2) (Z>p/2) - - Z>p/2 Z<-p/2 Xo Yo (Z<-p/2) (Z>p/2) B. Ppelned CORDIC Z>p/2 Top level module of ppelned CORDIC s shown n Fgure. The ppelned CORDIC has three nputs: Clk for clock, for reset (actve low), and Angle for the target angle. It also has two outputs, Cos and Sn, whch represents cosne and sne result of the target angle respectvely. Two man blocks are avalable: Quadrant Detector and CORDIC Core. Fg. 2. P/2 - Z Quadrant detector n ppelned CORDIC Zo 3
4 CORDIC Core s the realzaton of CORDCIC s dfference equatons n ppelned archtecture. There are 4 stages of ppelne n the core, each of whch conssts of the structure shown n Fgure 3. In each stage, three adders/substractor, two arthmetc rght-shfters, one drecton block that controls the drecton of rotaton, and an nverse tangent constant are present. Snce the amount of bt-shftng performed on each stage s constant, the shfter can be mplemented as seres of wre. Drecton Selector sgn y sgn z >> >> arctan produce modfed target angle Ph. Ths blocks also generate two 2-bt wde sgnal, Quad and Doman whch wll later be used as sgnal for post-processng requred due to doman foldng technque. CORDIC Core s mplemented n ppelned archtecture. The dfference s n the number of stage and the crcutry n each stage, whch are shown n Fgure 5 and Fgure 6. Wth the same reason as the prevous secton, the shfter unt can be replaced wth seres of wre. The allowed value for CORDIC teraton are =4, 5, 6,, 5 as n (3). The teraton step =5can be omtted snce the shfter wll produce retenton of sgn bt only. The teraton step =7can use crcutry n Fgure 6 snce the 2 + shfter wll also produce retenton of sgn bt. + y + z + X Y Fg. 3. Elementary rotatonal unt of ppelned CORDIC core In order to reduce the crtcal delay path, each ppelne stage s separated by a regster. Ths leads to a penalty n term of ncreased latency as the ppelne stage ncreases. The total latency for ths desgn s 4 clock cycles. Ths desgn s able to acheve throughput of one due to the nature of the archtecture C. Vrtually Scalng-Free Adaptve (VSFA) CORDIC The top level module has three nputs and two outputs, smlar to the top level of Conventonal CORDIC n the prevous secton. There are three man blocks: Quadrant and Doman detecton, CORDIC Core wth regon of convergence [,π/8), and Output Processng block as shown n Fgure 4. Fg. 5. X + Y + Elementary rotatonal unt of VSFA CORDIC ( <b/2) X Y Angle 2 7 Clk X Y Z Quadrant & Doman Detector X Y Ph Quad Doman X + Y + Fg. 4. X Y Ph Quad_In Doman_In CORDIC Core X Y Quad_Out Doman_Out 2 2 X Y Quad Doman Xo Cos Yo Sn Output Processng Top level module of VSFA CORDIC Quadrant and Doman Detecton block has three nputs: -bt wde X and Y, and also 7-bt wde Z. The purpose of ths block s to detect the quadrant and doman n where the target angle les and subsequently apples doman foldng to Fg. 6. Elementary rotatonal unt of VSFA CORDIC ( b/2) The teraton process represented by the ppelne stages are eecuted adaptvely usng archtecture llustrated n Fgure 8. The elementary rotatonal unt correspondng to =4s repeated s tmes, whle for =5 4 s used only once. In order to balance the ppelne, elementary rotatonal unt for =(7, 8), (9, ), (, 2) are each pared to create one stage, snce the number of adders s the same as wth 7. Each elementary rotatonal unt has Enable sgnal, based on the locaton of logc n the 2-bt unsgned representaton of Ph. For eample, f the bnary representaton of Ph s, then the sequence of actve elementary rotatonal unt s =4, 4, 4, 4, 4, 4, 5, 3. Output Processng block s used to fold back the results obtaned n CORDIC Core nto the orgnal quadrant and 4
5 (a) ppelned CORDIC verfcaton (b) VSFA CORDIC verfcaton Fg. 7. Functonal smulaton showng nput and output output error of cosne and sne calculaton between π and π s and the average s The comparson of error performance between ppelned and VSFA CORDIC s shown n Table V. Fg. 8. Ppelned Archtecture of VSFA CORDIC [7] doman of the target angle. Ths block conssts of two fed scalng unt of / 2 and two adder/subtractor unts. IV. SIMULATION AND PERFORMANCE EVALUATION A. Smulaton and Verfcaton Both CORDIC algorthms mplemented n ths paper are specfc to generate sne and cosne functon. Therefore, t s optmzed to only capable of workng n rotaton mode. The nput argument of and y are also predefned, and the user can only nput the angle argument z. The smulaton s perfomed by usng ModelSm software. The verfcaton s done by comparng sne and cosen calculaton results produced by the proposed desgns wth the result from the model desgn wrtten n Matlab. Fgure 7a shows the functonal smulaton of ppelned CORDIC. It can be nferred from the smulaton that the desgn has 4 clock cycles latency and throughput of one. Ths amount of latency results from ppelned archtecture nterstage regsters, whch are 4 stages n total. The mamum output error of cosne and sne calculaton between π and π s and the average s The functonal smulaton of VSFA CORDIC s shown n Fgure 7b. Ths desgn has better latency, 2 clock cycles n total, compared to the conventonal CORDIC. The mamum B. Synthess and Performance Comparson The complaton and synthess of proposed desgns are performed by usng Altera Quartus II software wth FPGA DE2-7 as target board. Measurement of performance, such as resource utlzaton such as logc elements, memory bts, and multplers, and mamum workng frequency can be obtaned n complaton report. The amount of cycles can be calculated wth ModelSm. The latency s obtaned by dvdng amount of cycles needed for processng one frame wth mamum frequency. The performance of ppelned CORDIC compared to VSFA CORDIC s descrbed n Table III. It s shown that both ppelned and VSFA CORDIC have embedded multpler. In addton, the frequency are very hgh, thus both can be mplemented n hgh-speed applcatons as a trgonometrc functon unt. However, n term of area (A) and latency (T ), ppelned CORDIC s superor and preferable to be used. We also compare our ppelned CORDIC wth other desgns reported n the lterature. In order to have the same TABLE III. TABLE IV. PERFORMANCE OF PIPELINED AND VSFA CORDIC Components Ppelned VSFA Total Logc Elements,3 2,9 Combnatonal Functons,4,852 Regsters Memory Bts Embedded Multplers PLLs Fma (MHz) Latency (ns) PERFORMANCE COMPARISON OF OUR PIPELINED CORDIC WITH OTHERS Parameter Our [6] [8] [9] [] Slces , LUTs Fma (Mhz) A T ( 6 )
6 TABLE V. ERROR PERFORMANCE COMPARISON BETWEEN PIPELINED AND VSFA CORDIC Angle Cosne Sne (Real) (Ppelned) (VSFA) (Real) (Ppelned) (VSFA) Real He Value Value Error Value Error Value Value Error Value Error π/ FFF 2 π/2 π/256 3DF FFF FFF FFD 2 π/2 π/28 37B C9 C7 2 C6 3 FFE FFB 3 FFC 2 3π/8 25B3 C3F C3B 4 C3E D9 D9 D9 π/4 922 A A A A 9E 3 A π/8 C9 D9 D8F D8F C3F C3F C3F π/28 C9 FFE FFB 3 FFC 2 C9 CD 4 C6 3 π/ FFF FFF FFD FFF 2 parameter settng for benchmarkng, our ppelned desgn s syntheszed usng Xln ISE desgn sute wth Spartan 3 as target devce. For performance comparson, we use a parameter of area multpled by delay (A T ). The parameter A s defned by the amount of resources requred (n ths case, A = Slces + LUTs), whle parameter T denotes the tme requred to perform computaton. It s desred to have smallest area and shortest delay (fastest frequency). Even though [9] and [] consume smaller area, both desgns take longer delay compared to our. Based on A T parameter as can be seen n Table IV, our ppelned desgn s shown to have best performance among others. V. CONCLUSION Two CORDIC archtectures, ppelned CORDIC and Vrtually Scalng-Free Adaptve (VSFA) CORDIC, have been succesfully mplemented n Altera DE2-7 FPGA development board. The functonal verfcaton s performed by usng ModelSm software wth accuracy of 2 3 and mamum error of for ppelned CORDIC and for VSFA CORDIC. The ppelned CORDIC consumes,3 logc element, ns latency, and 42.7 MHz mamum frequency, whle VSFA CORDIC utlzes 2,9 logc element, ns latency, and MHz mamum frequency. Based on performance comparson n term of area-delay parameter(a T ), our ppelned CORDIC s shown to have best performance among others, hence more sutable to be used n varous applcatons, especally those whch requre hghspeed data transfer. [7] K. Maharatna, S. Banerjee, E. Grass, M. Krstc, and A. Troya, Modfed vrtually scalng-free adaptve cordc rotator algorthm and archtecture, Crcuts and Systems for Vdeo Technology, IEEE Transactons on, vol. 5, no., pp , 25. [8] E. Garca, R. Cumpldo, and M. Aras, Ppelned cordc desgn on fpga for a dgtal sne and cosne waves generator, n Electrcal and Electroncs Engneerng, 26 3rd Internatonal Conference on. IEEE, 26, pp. 4. [9] L. Vachhan, K. Srdharan, and P. K. Meher, Effcent cordc algorthms and archtectures for low area and hgh throughput mplementaton, Crcuts and Systems II: Epress Brefs, IEEE Transactons on, vol. 56, no., pp. 6 65, 29. [] S. Aggarwal and K. Khare, Hardware effcent archtecture for generatng sne/cosne waves, n VLSI Desgn (VLSID), 22 25th Internatonal Conference on. IEEE, 22, pp REFERENCES [] R. R. Teja and P. S. Reddy, Sne/cosne generator usng ppelned cordc processor, Proc. IACSIT Internatonal Journal of Engneerng and Techonology, vol. 3, no. 4, pp , 2. [2] V. Kantabutra, On hardware for computng eponental and trgonometrc functons, Computers, IEEE Transactons on, vol. 45, no. 3, pp , 996. [3] C. K. Cockrum, Implementaton of the cordc algorthm n a dgtal down-converter, 28. [Onlne]. Avalable: cockrum.net/cockrum Fall 28 Fnal Paper.pdf [4] J. E. Volder, The CORDIC trgonometrc computng technque, Electronc Computers, IRE Transactons on, no. 3, pp , 959. [5] J. S. Walther, A unfed algorthm for elementary functons, n Proceedngs of the May 8-2, 97, sprng jont computer conference. ACM, 97, pp [6] K. Maharatna, A. Troya, S. Banerjee, and E. Grass, Vrtually scalngfree adaptve cordc rotator, IEE Proceedngs-Computers and Dgtal Technques, vol. 5, no. 6, pp , 24. 6
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