A Beginner s Guide to SerDes and AMI Modeling. Todd Westerhoff, SiSoft Corey Mathis, MathWorks

Transcription

1 A Beginner s Guide to SerDes and AMI Modeling Todd Westerhoff, SiSoft Corey Mathis, MathWorks

2 SPEAKERS Corey Mathis Industry Marketing Manager, MathWorks Corey is responsible for the communications, electronics, and semiconductor market segments. Prior to joining MathWorks, Corey managed a global automotive sensors business at Sensata Technologies, and spent nine years at Agilent Technologies in a variety of roles including applications engineering and business development. He has an MBA from Boston University and a bachelor s in electrical engineering from Union College in Schenectady, NY. Todd Westerhoff VP Semiconductor Relations, SiSoft twesterh@sisoft.com, Todd Westerhoff has over 36 years of experience in modeling and simulation, including 19 years of signal integrity experience. He is responsible for SiSoft's activities working with semiconductor vendors to develop high quality simulation models. Todd has been heavily involved with the IBIS-AMI modeling specification since its inception. He has held senior technical and management positions for Cisco and Cadence and worked as an independent signal integrity consultant. Todd holds a B.E.E.E. degree from the Stevens Institute of Technology in Hoboken, New Jersey.

3 Background Good mixed-signal SerDes models are hard to develop o Modeling analog and digital subsystems together o Model abstraction => adding analog parasitics, fixed point conversation o Portability issues between EDA tools AMI models are equally hard to develop o AMI development typically occurs after the fact o Created by different group o Limited testing before distribution

4 SerDes Architectural Exploration

5 Simulink for SerDes Simulation Model continuous-time and discrete-time components together Graphical environment for building signal processing, communications, and physical systems Express components at varying levels of abstraction Fast behavioral simulation using variable step ODE solvers for time domain analysis of control loops, VCOs, PLLs, noise Integration with MATLAB or C code

6 Multiple Ways to Model 4 tap TX with normalization captured two ways Architectural diagram Algorithmic description Channel behavior with & without equalization

7 SerDes Mixed-signal Examples Search for mixed-signal library

8 What Are IBIS-AMI Models? Developed as an open standard so SerDes suppliers can share models with customers without exposing IP Original standard included only electrical information, version 5.0 added Algorithmic Modeling Interface (AMI) to include signal processing Models compatible with standard EDA tools Tx AMI Tx Ckt Tx Pkg Interconnect Channel/System Interconnect Rx Pkg Interconnect Rx Ckt Rx AMI.ami.dll.ibs.sNp.ibs.ami.dll

9 Creating AMI models from SerDes models Convert AMI algorithmic model into C code using Embedded Coder A Pilot Support Package (PSP) from MathWorks customizes Embedded Coder to provide AMI parameter file Flow supports any blocks or algorithms that support C code generation, including embedded MATLAB code using the MATLAB Function Block

10 IBIS-AMI Model Types Simple, linear, non-adaptive Init or LTI model TX: 4 tap filter Complex, non-linear, adaptive Getwave or NLTV model RX: CTLE, Saturation, 8 tap DFE, CDR Design characteristics drive proper IBIS-AMI model type

11 AMI Model Generation Identify model type Identify AMI parameters Generate Code & Compile Based on design characteristics (Init/LTI or Getwave/NLTV) C++ code.ami file

12 Generated Code AMI wrapper Model behavior in C++

13 AMI Parameters AMI RX Example Saturation Block Code, Continuous Time, Time-Domain CDR/DFE Code, Sampled Time, Time-Domain Peaking Filter Structural, Continuous Time, Frequency-Domain Clock Ticks output

14 AMI RX - Architectural Simulation Pad Data Clock Position Latch CDR Inc./Dec. Early / Late Count DFE Taps

15 Model Validation = Simulink QCD

16 Integrated Design Flow Tight analysis loop speeds three critical aspects of design: o Design capture and analysis o Regression testing / issue identification o Design debugging and tuning

17 Standardized Top-Level Test Bench Simulation control Ensures consistent channel modeling Enforces correct partitioning of IBIS-AMI analog / algorithmic models Fast / accurate comparison of Simulink and QCD simulation results Test bench inputs Test bench outputs Speeds the design and validation process

18 Channel & Analog Modeling Channels Models Combined flow leverages QCD capabilities: o S-parameter validation, interpolation, extrapolation o Analog TX/RX modeling o Vendor AMI model libraries

19 Accelerating Regression Testing 1. Set up channels and test conditions Set up and manage 100 s of channels & 1,000 s of tests in one place Run all tests at the same time 2. Simulations run in parallel Simulations run in parallel o Speedups >100x are achievable 3. Review pass/fail results & waveforms Simulations post-processed to extract key metrics and pass/fail criteria

20 Compliance Testing Channel Tests Insertion Loss Deviation Tx/Rx Equalization Tests Compliance Kit Library Eye Rx Latch

21 Isolate & Debug Model Problems 1. Filter & sort 3. QCD generates waveform & test parameters 2. Identify case(s) for debugging 4. Simulate & debug in Simulink and MATLAB QCD post-processing produces design metrics that can be sorted/filtered Eye mask analysis produces pass/fail criteria & margin Automatically extract waveforms & model parameters to drive Simulink

22 Portable, Compliant Models Eye Diagram Output Clock Output Control Inputs Performance Test Simulation Time Reference Time Relative Speed Statistical 1 sec 1 sec 1.000x TimeDomain_008spb 1.46 min/mbit 1.30 min/mbit 0.889x TimeDomain_016spb 1.87 min/mbit 1.46 min/mbit 0.783x TimeDomain_032spb 3.33 min/mbit 2.60 min/mbit 0.781x TimeDomain_064spb 7.97 min/mbit 6.02 min/mbit 0.755x TimeDomain_128spb min/mbit min/mbit 0.814x Simulation Speed Compliance - Samples/Bit Compliance - Block Size Validation tests show generated AMI models work as well as models created by hand

23 Reusing SerDes Models for AMI AMI model Quantum Channel Designer SerDes test bench generation Regression / compliance testing IBIS-AMI model validation Simulink / MATLAB Interactive design & debug Building block library AMI code generation Test bench data

24 Summary AMI models can be created from Architectural models normally created during the SerDes design cycle The parameters exposed in an AMI model can be varied depending on the application Models produced with this process behave just like any other well-constructed AMI model

25 For More Information [1] MathWorks, IBIS-AMI Pilot Support Package User Guide, Natick, MA, [2] Burns, D., Madsen, J., Westerhoff, T., Katz, W., Understanding IBIS-AMI Simulations, DesignCon 2015, Santa Clara, CA, [3] Steinberger, M., Westerhoff, T., White, C., Demonstration of SerDes Modeling Using the Algorithmic Model Interface (AMI) Standard, DesignCon 2008, Santa Clara, CA, [4] IBIS 6.1 Specification, IBIS Open Forum, September 2015, [5] Dramstad, K., Hawes, A., Katz, B., Katz, W., Westerhoff, T., Experiences Correlating IBIS-AMI Models and Measurement, DesignCon 2010, Santa Clara, CA, 2010.

26 Corey Mathis Todd Westerhoff

27 Backup

28 Adding Simulink AMI models to IBIS models Since Simulink only generates code for the AMI portion of the model, the.ami and.dll generated from Embedded Coder need to be referenced under the [Algorithmic Model] section of the.ibs model: FIR.ami Model_RX.ibs FIR_win32. dll