Reversible Realization of Quaternary Decoder, Multiplexer, and Demultiplexer Circuits

Transcription

1 Egieerig Letters, :, EL Reversible Realizatio of Quaterary Decoder, Multiplexer, ad Demultiplexer Circuits Mozammel H.. Kha, Member, ENG bstract quaterary reversible circuit is more compact tha the correspodig biary reversible circuit i terms of umber of iput/output lies required. Decoder, multiplexer, ad demultiplexer are very importat buildig blocks of digital systems. this paper, we show reversible realizatio of these circuits usig quaterary shift gates (QSG), quaterary cotrolled shift gates (QCSG), ad quaterary Toffoli gates (QTG). We also show the realizatio of multi-digit QCSG ad QTG usig QSGs ad QCSG. dex Terms Decoder, demultiplexer, multiple-valued logic, multiplexer, quaterary logic, reversible logic Toffoli gates (QTG) eeded for sythesis of QGFSP expressio. Experiece shows that CD based geeral sythesis methods are sometimes ot very cost effective for sythesis of some medium-scale buildig blocks. this case, problem specific maual sythesis of such medium-scale buildig blocks is relatively cost effective. Decoder, multiplexer, ad demultiplexer are very importat buildig blocks of digital systems. this paper, we show a problem specific maual approach of reversible realizatio of these circuits usig quaterary shift gates (QSG), quaterary cotrolled shift gates (QCSG), ad quaterary Toffoli gates (QTG). We also show the realizatio of multi-digit QCSG ad QTG usig QSGs ad QCSG.. NTRDUCTN Reversible logic [] is a very prospective approach of logic sythesis for power reductio i future computig techologies. a reversible circuit, the umber of iputs ad outputs are same ad there is a oe-to-oe mappig betwee iput values ad output values. Reversible circuits are costructed usig reversible gates. Quaterary logic is very suitable for ecoded realizatio of biary logic fuctios by groupig -bits together ito quaterary digits. This sort of quaterary ecoded reversible realizatio of biary logic fuctio requires half times iput/output lies tha the origial biary reversible realizatio. s the umber of iput/output lies is reduced, this quaterary ecoded realizatio of biary logic fuctio makes the circuit more compact ad maageable, especially for the quatum techology, where the cost of qudit (quatum digit) realizatio ad qubit (quatum bit) realizatio are almost same. However, quaterary ecoded realizatio of biary logic fuctio requires ecodig of biary iputs ito quaterary values ad decodig of quaterary outputs ito biary values. Reversible realizatio of such biary-to-quaterary ecoder ad quaterary-to-biary decoder are discussed i [] i the cotext of quaterary quatum logic. Similar realizatio ca also be doe i other quaterary reversible techologies. Quaterary reversible logic sythesis is a very ew research area [-]. Paper [] preseted a quaterary reversible logic sythesis method usig quaterary Galois field sum of products (QGFSP) expressio ad paper [] preseted determiatio of QGFSP expressio for a give fuctio usig quaterary Galois field decisio diagram (QGFDD). Papers [, ] preseted realizatio of quaterary Mauscript received September,. Mozammel H.. Kha is with the Departmet of Computer Sciece ad Egieerig, East West Uiversity, Mohakhali, Dhaka, Bagladesh, phoe: +--; fax: +--; mhakha@ ewubd.edu.. BCKGRUND N GF() PERTNS Galois field (), abbreviated as GF(), is a fiite field F = {,,, } with two biary operatios additio (deoted by +) ad multiplicatio (deoted by or absece of ay operator) as defied i Table. dditio ad multiplicatio operatios are both commutative ad associative. Multiplicatio operatio is distributive over additio operatio. For more details about GF() operatios, see []. Table. GF() operatios +. QUTERNRY SHFT GTES There are! = possible permutatios of,,, ad. Therefore, there are possible truth tables for -digit reversible gates. mog these -digit reversible gates, we will use oly four gates of the form y = x + z [GF()] for z {,,,}. The GF() expressios ad correspodig truth tables of these gates are show i Table. We will refer the -digit gates of Table as quaterary shift gates (QSG). The gate for y = x + ca be regarded as a buffer gate or a wire. The QSGs ca be realized usig liquid io-trap quatum techology [] ad other reversible techologies. We will graphically represet the QSGs usig the symbol of Figure. Two QSGs i cascade behave like aother QSG. Equivalet QSG correspodig to all cascade pairs are give i Table, which ca be easily verified usig GF() expressios or truth tables of QSGs from Table. f a (dvace olie publicatio: November )

2 Egieerig Letters, :, EL cascade pair of two QSGs is equivalet to + gate, the the secod QSG is said to be the iverse of the first QSG. verse gates are used to restore the iput sigal for reuse i the circuit. Table. GF() expressios ad truth tables for quaterary shift gates put = x + y = x + y = x + y = x + x y Figure. Symbol of quaterary shift gates (QSG) Table. Equivalet QSGs correspodig to cascade pairs of two QSGs d gate st gate The realizatio of -digit QCSG usig -digit QCSGs is show i Figure. From Figure, we see that if ad oly if x = x =, the a = ad + z shift is applied o x. For all other combiatios of x ad x, a will ever be ad + z shift will ot be applied o x. The right most two -digit QCSGs are iverse gates of the left most two QCSGs ad are used to restore the iput costat for reuse i the circuit. auxiliary costat iput used i the desig of a reversible circuit is called acilla digit. This realizatio eeds elemetary gates ad acilla digit. The realizatio of -digit QCSG usig -digit QCSGs is show i Figure. Figure, if ad oly if x = x =, the a =. gai, if ad oly if a = x =, the b =. This implies that, b = if ad oly if x = x = x = ad + z shift is applied o x cotrolled iput. This realizatio eeds elemetary gates ad acilla digits. this way, we ca realize a -digit QCSG. We ca easily show that for a -digit QCSG, the umber of acilla digits is ( ) ad the umber of elemetary gates is ( ) +. a x y Figure. Realizatio of -digit quaterary cotrolled shift gate (QCSG) V. QUTERNRY CNTRLLED SHFT GTES The symbol of the -digit quaterary cotrolled shift gate (QCSG) is show i Figure. The gate applies a shift operatio (Table ) o the cotrolled iput x whe the cotrollig iput x is. The outputs of the gate are y = x ad y = x + z if ad oly if x = ; y = x otherwise. The QCSG ca be realized usig liquid io-trap quatum techology [] ad other reversible techologies. We propose a -digit QCSG usig the symbol of Figure. Figure, x L x are cotrollig iputs ad x is the cotrolled iput. The cotrolled output is y = x + z if ad oly if x = x = L x = ; y = x otherwise. x x y Figure. Symbol of -digit quaterary cotrolled shift gate (QCSG) x y y x y x y a b x y Figure. Realizatio of -digit quaterary cotrolled shift gate (QCSG) V. QUTERNRY TFFL GTE The -digit quaterary Toffoli gate (QTG) is show i Figure, where x L x are the iputs, y i = x (for i i =,, L, ) are the pass through outputs ad y = xx L x + x [GF()] is the cotrolled output. Realizatio of QTG usig QCSGs ad -digit QCSGs is discussed i []. x + x y y + x x Figure. Symbol of -digit quaterary cotrolled shift gate (QCSG) y y x Figure. Quaterary Toffoli gate (QTG) y (dvace olie publicatio: November )

3 Egieerig Letters, :, EL V. REVERSBLE RELZTN F QUTERNRY DECDER The truth table of quaterary decoder with active- output is show i Table. For a give iput combiatio, oly the ed output will be ad the remaiig outputs will be. Reversible realizatio of quaterary decoder with active- output is show i Figure. The outputs are geerated alog costat iputs. For a give iput combiatio, the iput values are made by applyig QSGs alog lies ad the a QCSG is used to chage the correspodig iput to output, the other outputs remai. For example, for iput combiatio =, two + QSGs are placed alog lies to make the iput values ad the a QCSG is used to chage the correspodig iput to output =. utputs through are realized usig the same techique. However, the iput values correspodig to the QCSGs are made by cascaded QSGs. Therefore, the effective shift at all cotrollig poits are explicitly show i the figure to make the circuit easily uderstadable. t ca be see that for a give combiatio of, oly oe QCSG will be active ad will apply a + shift o the correspodig costat iput to produce the output ad other outputs will remai. Quaterary decoder of ay size ca be realized usig the same techique. Moreover, the outputs may be made active- or active- by simply replacig + shifts of the QCSGs by appropriate shifts. V. REVERSBLE RELZTN F QUTERNRY MULTPLEXER The truth table of quaterary multiplexer is show i Table, where the output is equal to the ed multiplexer iput. Reversible realizatio of the multiplexer is show i Figure. Depedig o the iput combiatio, oe of the decoder outputs becomes ad the other decoder outputs remai s. The decoder outputs multiplied with their correspodig multiplexer iputs become s ad these s are added to the costat iput alog the output lie. The oly decoder output multiplied with the correspodig multiplexer iput becomes exactly equal to the multiplexer iput ad is added with the costat iput alog the output lie to produce the multiplexer output. For example, if =, the the decoder output becomes ad the other decoder outputs become. this case, is multiplied by ad the other multiplexer iputs are multiplied by. Therefore, oly is added with the costat iput to produce the output, which is exactly equal to. Table. Truth table of quaterary decoder with active- output outputs (dvace olie publicatio: November )

4 Egieerig Letters, :, EL Figure. Reversible realizatio of quaterary decoder with active- outputs Table. Truth table of quaterary multiplexer Therefore, oly the demultiplexer output will be equal to the demultiplexer iput ad the other demultiplexer outputs will be s. V. REVERSBLE RELZTN F QUTERNRY DEMULTPLEXER The truth table of quaterary demultiplexer is show i Table, where oly the ed output is equal to the demultiplexer iput ad the remaiig outputs are s. Reversible realizatio of the demultiplexer is show i Figure. Depedig o the iput combiatio, oe of the decoder outputs becomes ad the other decoder outputs remai s. The decoder outputs are multiplied with the demultiplexer iput ad become s. These s are the added with the costat iput s to produce outputs. The oly decoder output is multiplied with the demultiplexer iput to produce. This is the added with the costat iput to produce o the ed output lie. For example, if =, the the decoder output becomes ad the remaiig decoder outputs become s. this case, is added oly with the costat iput alog the demultiplexer output lie ad s are added with the other costat iput s. decoder outputs multiplexer iputs output Figure. Reversible realizatio of quaterary multiplexer Table. Truth table of quaterary demultiplexer (dvace olie publicatio: November )

5 Egieerig Letters, :, EL decoder outputs iput demultiplexer outputs Figure. Reversible realizatio of quaterary demultiplexer REFERENCES [] T. Toffoli., Reversible Computig, i utomata, Laguages ad Programmig, J. W. Bakker ad J. va Leeuwe, ED. Spriger Verlag,, pp. -. [] M. H.. Kha ad M.. Perkowski, GF() based sythesis of quaterary reversible/quatum logic circuits, Joural of Multiple-Valued Logic ad Soft Computig, vol.,. [] M. H.. Kha, N. K. Siddika, ad M.. Perkowski, Miimizatio of quaterary Galois field sum of products expressio for multi-output quaterary logic fuctio usig quaterary Galois field decisio diagram, th EEE t. Symp. Multiple-Valued Logic (SMVL ), Dallas, Texas, US, - May (submitted). [] M. H.. Kha, Quatum realizatio of quaterary Feyma ad Toffoli gates, teratioal Coferece o Electrical ad Computer Egieerig (CECE ), Dhaka, Bagladesh, - December,, pp. -. []. Muthukrisha ad C. R. Stroud Jr., Multivalued logic gates for quatum computatio, Physical Review. vol.,, /-. X. CNCLUSN Multiple-valued reversible circuits are a promisig choice for future computig techology. Quaterary logic has the advatage that classical biary logic fuctios ca be expressed as quaterary logic fuctios by groupig -bits together ito quaterary digits. Quaterary ecoded reversible realizatio of biary logic fuctio will be half-times compact tha the reversible realizatio of origial biary logic fuctio i terms of the umber of iput/output lies required. There is oly a few works o CD based geeral sythesis method of quaterary logic fuctios [, ]. Experiece shows that CD based geeral sythesis methods are sometimes ot very cost effective for sythesis of some medium-scale buildig blocks. this case, problem specific maual sythesis of such medium-scale buildig blocks is relatively cost effective. Here, we preset problem specific maual sythesis of quaterary decoder, multiplexer, ad demultiplexer circuits usig reversible gates. These circuits are practically importat medium-scale buildig blocks for sythesis of large digital systems. These problem specific maual sythesis results will also help us to compare the complexity of CD based geeral sythesis methods. To aid the sythesis, we have used two macro-level quaterary gates multi-digit quaterary cotrolled shift gate (QCSG) ad quaterary Toffoli gates ad show their realizatio usig basic quaterary gates. (dvace olie publicatio: November )