On the False Path Problem in Hard Real-Time Programs

Size: px
Start display at page:

Download "On the False Path Problem in Hard Real-Time Programs"

Transcription

1 On the False Path Problem in Hard Real-Time Programs Peter Altenbernd C-LAB D Paderborn, Germany Abstract This paper addresses the important subject of estimating the worst-case execution time (WCET) of hard real-time programs essentially needed for further evaluation of realtime systems. Purely structure oriented methods, analysing the control flow of the program without taking into account functional dependencies, tend to overestimate the execution time. An exact solution of this NP-complete problem is impossible for larger applications. In this paper, we propose a new heuristic of finding an estimate on the WCET. It provides a reasonable trade-off between analysis results and analysis efforts: the results will still be better than purely structure oriented methods without spending too much time on finding an exact solution. For this purpose our approach does not need any user annotations except for maximum loop counts and maximum recursion depths. The actual algorithm combines pruned path enumeration with the concept of symbolic execution. 1. Introduction Predicting the execution times of programs by static timing analysis tools is a fundamental problem in hard realtime systems. It is important for system design, especially with respect to schedulability testing, (e.g. [17, 1]) which relies on the values delivered by the static timing analysis. Most of the recent work on this subject focusses on analytical methods to extract the worst-case execution time (WCET) from a given program. One simple approach to deal with the problem is to find the longest structural path in the control flow of the program, and to assume its length to be the worst-case execution time. The disadvantage of this method is that it ignores mutual exclusive control flow branches, resulting in overestimated values, as demonstrated by the example of Fig.1. Due to the two if-statements, where the second one depends on the first, the program will run either through block a and then through d, or through b and then through c. Howbegin if E < 0 then /* block a=251 */ end; condition := F ALSE; x := E + 45; else /* block b=229 */ condition := T RU E; x :=?E; if condition then /* block c=412 */ result := x DIV y; else /* block d=352 */ result := y; Figure 1. A simple example program ever, a purely structure oriented analysis would compute the worst-case execution time as M AX(a; b) + M AX(c; d) = 663, instead of 641 = M AX(a + d; b + c), the true value. Hence, the value is not given by the longest structural path (a; c), but by the longest executable path (sometimes referred to as feasible path) (b; c). In the following, we will refer to non-executable paths, like (a; c) or (b; d), as false paths (sometimes referred to as dead path), and to the problem of finding the longest executable path in a realtime program as the false path problem. The false path problem is NP-complete, i.e. for the exact solution all possible input value combinations would have to be considered, so that exact approaches are excluded from use when dealing with larger applications. In this paper, we propose a new heuristic of dealing with the false path problem without the need of user annotations on mutual exclusive control flow branches. It provides a reasonable trade-off between analysis results and analysis efforts: the results will still be better than purely structure oriented methods without spending too much time on find-

2 ing the exact solution. Basically our method is a combination of path enumeration with pruning (for structural analysis) and symbolic execution (for executability analysis). Our paper addresses the determination of the worst-case execution time with the following assumptions: We use the term program in the sense of a sequential program. Our method is devoted to hard real-time programs, i.e. the code to be analysed is quite restrictive: Maximum loop counts must be known in advance, as well as maximum function recursion depths. Since we deal with programs automatically generated from differential equations, we can easily fulfill these restrictions. Our analysis will run on the abstract description of the program: the control flow graph (CFG) to be generated at compile time. It is assumed that the computation time of all blocks of basic statements is known in advance. Caching and pipelining effects are beyond the scope of the paper. In this paper we will focus on worst-case times only. Our method is applicable to get the best-case times as well. The remainder of the paper is structured as follows: the next section illustrates how our approach is related to others. In Section 3, we introduce our new method of finding the longest executable path. In Subsection 3.1, our model of the control flow graph is described. Subsections 3.2 and 3.3 deal with the particular problems of loops and function calls. In Section 4 some experimental results are presented. Finally, Section 5 gives some conclusions. 2. Related Work Early work in the field of determinating the worst-case execution time focussed mainly on measuring the program runtimes on the target machine, like [9], or like the dual loop benchmark paradigm [4]. Within this method the program to be analysed is embedded into a loop, which is executed for a number of times. This way it is possible to measure a maximum/average runtime of the program. The disadvantages of this approach are obvious: the results are input dependent and the system overhead cannot be accurately determined. The simulation of the target processor including its software [5] is another non-analytical approach, which mainly suffers from the same disadvantages as the loop benchmark paradigm and additionally from the quite slow computation speed of the simulator. Approaching analytical methods, the simplest technique is to find the longest structural path in the control flow graph (e.g. [15]). As mentioned in Section 1, this method tends to overestimate the worst-case execution time, resulting in severe processor underutilisations, which is considerably improved by our method. More sophisticated analytical methods which try to find the longest executable path have to cope with the huge complexity of the false path problem. Techniques which try solve the problem exactly, like [16], are only applicable to very limited program sizes. To overcome the complexity problem, some methods, like [7], which tries to simultaneously consider functional and timing analysis, require timing annotations to be added by the user. These methods typically improve the runtime behaviour of the analysis while concurrently delivering very accurate results. Their disadvantage is that the user has to be an expert on the insights of the static timing analysis tool and of the program code. However, our approach does not need any user knowledge about the timing of the real-time program, or vice versa, i.e. it takes into consideration that many of todays real-time programs are automatically synthesised. In [12] another user-annotated method, which is based on integer linear programming (ILP), is proposed. This method is very well-suited for modelling the whole system including the processor architecture and the annotations. Nevertheless, the computational results are not better than the results of a purely structural method, where the annotations are used to manipulate the control flow graph. Furthermore, this method is only applicable to relatively small examples, since larger examples create huge ILPs, which are difficult to solve with reasonable costs. In contrast, our method is based on the control flow graph, and its heuristical behaviour guarantees its applicability to larger examples as well. Most of the recent work in the field of static timing analysis of real-time programs focusses on the impact of pipelining [11] and caching [14] strategies. Though these are also imported problems, our approach emphasises the false path problem. However, the concepts of handling pipelines and caches can be included into our method as well. There is a similar false path problem in the field of hardware development, where it is of interest to find the longest executable path in a network of logic gates. This problem was firstly addressed in 1987 [6], and proved to be NPcomplete in [13]. In contrast to the real-time field, this problem also has to deal with signal delay times, which makes it more difficult to solve. On the other hand, a digital circuit only has to deal with logic signal values (variables), and not with more complex data types as in real-time programs, which makes the problem easier to solve. Conceptionally, our heuristic is slightly similar to the digital circuit analysis of [3].

3 3. False Path Problem Heuristic Basically, our method is a combination of path enumeration with pruning and symbolic execution. We use a branchand-bound algorithm to perform the actual path search in the control flow graph. The algorithm is bounded at each node (block) of the search by early rejecting alternatives, which will not improve the currently best solution. Symbolic execution is a sort of simulated execution of the program. It is used to maintain a virtual memory representing current variable values, as far as they are known. It evaluates program statements concurrently to the path search algorithm. The symbolic execution will not try to evaluate each statement perfectly: It will only try its best. Our algorithm behaves heuristicly, since it is started with no knowledge about the input data values. However, values (or at least value ranges) are assigned when approaching certain branches as in if-statements, i.e. if the entrance condition for a certain branch is E < 0 for example, then it is assumed for the control flow following the branch that E is negative. This can be demonstrated by the example of Fig. 1. The path search will start with visiting block a due to the longer execution time of a compared to b. The symbolic execution will then store that E is negative. Furthermore, it will assign FALSE to condition and the value of E plus 45 to x, i.e. x is now known to be below 45. In the next step, the path search is forced to visit block d, not c, due to condition = FALSE. Using this method the false paths (a,c) and (b,d) are excluded. Hence, our heuristical symbolic execution is sufficient to avoid many false paths, though it does not take into account the input values Control Flow Graph Our algorithm is based on an attributed control flow graph, a directed graph G = (V; E), where the set of hierarchical vertices V represents blocks of program statements, and the set of edges E represents the actual control flow including branches. Each (hierarchical) vertex is of one of the following types: atomic, complex, function, or loop. Complex vertices are used to represent hierarchy and loop bodies, whereas atomic vertices are used to represent basic statement blocks at the lowest level. Atomic vertices are annotated by an attribute C giving the total maximum computation effort, necessary to run the statements inside. Function vertices are further decomposed by an internal lower-level complex vertex, representing the function body. Similarly, loop vertices are further decomposed by an internal lower-level complex vertex, representing the loop body. An example involving all mentioned vertex types is shown in Fig. 2. complex atomic atomic atomic atomic function complex atomic loop complex Figure 2. Example of a control flow graph 3.2. Loops Since we are dealing with hard real-time systems, we presume that loops behave deterministically, i.e. the maximum loop count is known in advance. This is quite restrictive, but our concern are hard-real time programs automatically generated from differential equations, so that we can easily fulfill this restriction. During the analysis, loops are treated as follows: whenever the algorithm reaches a loop vertex, it will first analyse the loop body (i.e. compute the worst-case execution time of the loop body) before continuing with the rest of the current level. The loop body analysis is repeated either until the symbolic execution evaluates the termination condition to true, or until the maximum loop count is reached. Variables which have been set inside of the loop have to be cleared after processing the loop. If not done so, all possible combinations of processing all loops would have to be considered. This is important when the variable is evaluated at a later instant outside the loop. Similarly, variables, which are embedded in an if-statement adn which have been set inside of the loop, are cleared at the end of each loop. If not done so, all possible combinations of processing this loop would have to be considered. This is important when the variable is evaluated at a later instant inside the loop. A loop vertex is annotated by an attribute M giving the maximum loop count and by an attribute C giving the maximum costs for evaluating the loop exit condition.

4 3.3. Function Calls Function or procedure calls are treated with the help of the function vertices. They express the hierarchical structure of the real-time program. For recursive functions the maximum recursion depth must be known in advance for the same reasons as the maximum loop count. During the worst-case-execution-time analysis, function vertices are handled by first analysing the function body before continuing with the rest of the current level. Recursive functions are only analysed as often as stated by the maximum recursion depth. Function vertices are annotated by an attribute C giving the maximum costs for calling (not executing) the function. Recursive functions are additionally annotated by an attribute M, the maximum recursion depth The Algorithm example condition:=false x:=e+45 if E < 0 C=30 mdts=663 if condition condition:=true x:= E C=221 mdts=633 C=199 mdts=611 result:=x/y C=382 mdts=382 C=30 mdts=412 result:=y C=322 mdts=322 Figure 3. Control flow graph of the example program The control flow graph will be extracted at compile time from the real-time program, including all vertex attributes described in the previous subsections. Then, in a preprocessing step, the maximum-delay-to-sink (mdts) values are computed for all vertices. The mdts-value of a vertex is the length of the longest structural path from the vertex to a vertex with no successor. The control flow graph of the example of Fig. 1 is shown in Fig. 3 including all mdts-values. The mdts-value of the source vertex of a graph is equal to the length of the longest structural path of the program. The mdts-values are needed to bound the path enumeration as far as possible. These values help to detect quite early whether an alternative leads to a better solution than the current best or not. The computational costs for the mdts-values grow proportional to the number of vertices, using a breath-firstsearch technique. function WCET(integer wcet, vertex V, memory M) begin! (memory, integer) switch (V:type) case atomic: for all statements S i in V do M.eval(S i); wcet += V:C; break; case loop: M.eval(exit condition); wcet += V:C while (not loop end(m, V:M)) do /* V =loop body */ (M; wcet) = WCET(wcet; V 0 ; M); wcet += V:C; M.eval(exit condition); break; case function: if (not max recurs depth(v:m)) then /* V =function body */ (M; wcet) = WCET(wcet; V 0 ; M); wcet += V:C; M.eval(call stmt); break; end switch; if (no successor(v )) then max := MAX(max, wcet); else M.eval(branch condition); for all successors V i of V do if (M.possible(V i) and wcet + V i:mdts > max) /* branch access and still better solution */ then WCET(wcet, V i, M); /* recursion */ return (M, wcet); end; function main() begin max := 0; /* current maximum wcet */ WCET(0, program, free memory); end. Figure 4. The WCET algorithm A pseudo-code of the simplified algorithm is given in Fig. 4. It is basically a recursive branch-and-bound algorithm enriched by the concept of symbolic execution, which is represented by the function M.eval(S). This function is used to transfer the result of the execution of a statement S into the virtual memory M. The recursive function WCET(), representing the worst-case-execution-time analysis, returns a tuple consisting of the virtual memory and the resulting worst-case execution time. The edges at each vertex are sorted in descending order by the mdts-values of the corresponding vertices. This gives the algorithm the

5 capability to find quite long paths very early. The mdtsvalues are further used to bound the current branch decision: whenever the current worst-case execution time wcet plus the mdts-value of the considered edge is less than the current maximum worst-case execution time max, it is not necessary to further explore the vertices following this edge. The algorithm is demonstrated in a more detailed manner than before by the example of Fig. 3. It starts by processing the if E<0 vertex, i.e. 30 is assigned to wcet. It carries on with the left branch of the vertex due to its greater mdtsvalue, i.e. E<0 is stored in M, the variables condition and x are set respectively, and 251 is assigned to wcet. The next vertex to process is if condition (wcet:=281). condition evaluates to FALSE, so that the right branch is processed next (wcet:=603). The maximum is set to 603. The algorithm steps back now to the beginning if E<0, i.e. the memory is cleared, and wcet is 30 again. Then the algorithm tries to visit the right branch, which is possible since the bound condition of the algorithm allows to carry on, i.e. E0 is stored in M, the variables condition and x are set respectively, and 229 is assigned to wcet. The next vertex to process again is if condition (wcet:=259). condition evaluates to TRUE, so that the left branch is processed next, i.e. wcet is set to 641, which is the final result. 4. Experimental Evaluation id #if #loop mdts wcet CPU reduce [s] factor GespAut % Pendel % AZsphp % Trajec % R3Tempo % dhrystone % Figure 5. Experimental results Some experimental results are shown in Fig.5, comparing the results of purely structural analysis (row mdts) with our new method (row wcet). The first five examples are mechatronical applications, all having no loops inside. The last example ( dhrystone ) is usually taken for benchmarking compiler optimisations, i.e. the dhrystone program does not compute anything meaningful. The effectivity of our algorithm highly depends on the internal structure of the considered example, i.e. the estimated bound on the worstcase execution time is reduced to between 1% and 50%. After intensively studying the code of the considered examples, we can state that in all cases our estimated value is equal to the true value of the worst-case execution time to be delivered by an exact method. The computational effort of our method mainly grows with the number of if-statements (O(2 #if )) and with the number of loop counts. A check on executability of a certain path is about linear to the CFG size. The large grows in complexity due to if-statements limits the applicability of our current algorithm to about 15 to 20 if-statements. However, this can easily be overcome by using the k-longest path search [18] instead of path enumeration as in our case, in connection with the concepts on executability analysis presented in this paper. Then the path search complexity is only O(k (jv j + jej) log k). The use of this concept is as follows: first, the k longest paths (k=#if should be adequate) are searched for. Then the longest of these paths is checked for executability using the concept of symbolic execution. If this is a false path, it will be continued with the second longest and so on, until an executable path is found. Considering the examples of Fig. 5 it is likely to find an executable path within the k longest ones. The estimate on the worst-case execution time is the length of the first executable path. If all k longest paths are false, then the worst-case execution time is bound by the length of the k-longest path. 5. Conclusions and Future Work This paper is a contribution to the important subject of estimating the worst-case execution time of hard real-time programs essentially needed for further evaluation of realtime systems. It especially addresses the false path problem, i.e. it overcomes the problem of overestimation of purely structure oriented methods. Due to the huge complexity of the false path problem, our method does not try to find an exact solution. It provides a reasonable trade-off between analysis results and analysis efforts: the results will still be better than purely structure oriented methods without spending too much time on accuracy. For this purpose our approach does not need any user annotations except for maximum loop counts and maximum recursion depths. The actual algorithm combines pruned path enumeration with the concept of symbolic execution. Our future work will mainly deal with changing the path search strategy from path enumeration to k-longest path search as suggested in Section 4. Since the runtime behaviour of our method highly depends on the number of if-statements, it is desirable only to consider if-statements related on former if-statements during the path search. To identify parts of a program whose executions are correlated with one another, compiler techniques, like [10], can be included in our method. Furthermore, the effects of caching and pipelining are important to be considered as well. The work presented in this paper will be used in the mechatronic project METRO granted by the German Ministry of Education and Research (BMBF). Within this

6 project our new technique will be used to support the mapping of periodic hard real-time tasks to a parallel computer [2], resulting in the configuration of an operating system [8]. References [17] K. Tindell. Adding Time-Offsets To Schedulability Analysis. Report YCS221, Department of Computer Science, University of York, [18] S. H. C. Yen, D. H. C. Duand, and S. Ghanta. Efficient Algorithms for Extracting the K Most Critical Paths in Timing Analysis. In Proceedings of the 26th Design Automation Conference, pages , [1] P. Altenbernd. Deadline-Monotonic Software Scheduling for the Co-Synthesis of Parallel Hard Real-Time Systems. In Proceedings of the European Design and Test Conference, pages , [2] P. Altenbernd and C. Ditze. Allocation of Periodic Hard Real-Time Tasks. In Proceedings of the IFAC/IFIP Workshop on Real-Time Programming, [3] P. Altenbernd and J. Strathaus. Solving the Path Sensitization Problem in Linear Time. In Proceedings of the European Design Automation Conference, pages , [4] N. Altman and N. Weideman. Timing Variations in Dual Loop Benchmarks. CMU/SEI-87-TR-22, Software Enginieering Institute, Carnegie Mellon University, [5] C. N. Arnold. Using the ETA System Multiprocessor Simulator to Prepare for the ETA. I/O, 1(1):9 12, [6] J. Benkoski, E. VandenMeersch, L. Claesen, and H. DeMan. Efficient Algorithms for Solving the False Path Problem in Timing Verification. In Proceedings of International Conference on Computer Aided Design, pages 44 47, [7] R. Chapman. Static Timing Analysis and Program Proof. Ph.D. Thesis, Computer Science, University of York, [8] C. Ditze. DReaMS Concepts for a D)istributed Rea)l-Time M)anagement S)ystem. In Proceedings of the IFAC/IFIP Workshop on Real-Time Programming, [9] P. Gopinath and R. Gupta. Applying Compiler Techniques to Scheduling in Real-Time Systems. In IEEE Real-Time Symposium, pages , [10] R. Gupta and P. Gopinath. Correlation Analysis Techniques for Refining Execution Time Estimates of Real-Time Aplications. In IEEE Workshop on Real-Time Operating Systems and Software, pages 54 58, [11] M. G. Harmon, T. P. Baker, and D. B. Whalley. A Retargetable Technique for Predicting Execution Time of Code Segments. Journal of Real-Time Systems, 7(x): , [12] Y.-T. S. Li and S. Malik. Performance Analysis of Embedded Software Using Implicit Path Enumeration. In Proceedings of the 32th Design Automation Conference, pages , [13] P. C. McGeer and R. K. Brayton. Integrating Functional and Temporal Domains in Logic Design. Kluwer, [14] M. K. Milligan and H. G. Cragon. Techniques to Support the Use of Cache Memory in Hard Real-Time Systems. In Proceedings of the IFAC/IFIP Workshop on Real-Time Programming, [15] A. Mok. Evaluating Tight Execution Time Bounds of Programs by Annotations. In IEEE Workshop on Real-Time Operating Systems and Software, pages 74 80, [16] C. Y. Park. Predicting Deterministic Executions Times of Real-Time Programs. Seatle 98195, University of Washington, 1992.

Worst-Case Execution Times Analysis of MPEG-2 Decoding

Worst-Case Execution Times Analysis of MPEG-2 Decoding Worst-Case Execution Times Analysis of MPEG-2 Decoding Peter Altenbernd Lars-Olof Burchard Friedhelm Stappert C-LAB PC 2 C-LAB 33095 Paderborn, GERMANY peter@c-lab.de baron@upb.de fst@c-lab.de Abstract

More information

Eliminating Annotations by Automatic Flow Analysis of Real-Time Programs

Eliminating Annotations by Automatic Flow Analysis of Real-Time Programs Eliminating Annotations by Automatic Flow Analysis of Real-Time Programs Jan Gustafsson Department of Computer Engineering, Mälardalen University Box 883, S-721 23 Västerås, Sweden jangustafsson@mdhse

More information

Classification of Code Annotations and Discussion of Compiler-Support for Worst-Case Execution Time Analysis

Classification of Code Annotations and Discussion of Compiler-Support for Worst-Case Execution Time Analysis Proceedings of the 5th Intl Workshop on Worst-Case Execution Time (WCET) Analysis Page 41 of 49 Classification of Code Annotations and Discussion of Compiler-Support for Worst-Case Execution Time Analysis

More information

Automatic flow analysis using symbolic execution and path enumeration

Automatic flow analysis using symbolic execution and path enumeration Automatic flow analysis using symbolic execution path enumeration D. Kebbal Institut de Recherche en Informatique de Toulouse 8 route de Narbonne - F-62 Toulouse Cedex 9 France Djemai.Kebbal@iut-tarbes.fr

More information

ait: WORST-CASE EXECUTION TIME PREDICTION BY STATIC PROGRAM ANALYSIS

ait: WORST-CASE EXECUTION TIME PREDICTION BY STATIC PROGRAM ANALYSIS ait: WORST-CASE EXECUTION TIME PREDICTION BY STATIC PROGRAM ANALYSIS Christian Ferdinand and Reinhold Heckmann AbsInt Angewandte Informatik GmbH, Stuhlsatzenhausweg 69, D-66123 Saarbrucken, Germany info@absint.com

More information

Allowing Cycle-Stealing Direct Memory Access I/O. Concurrent with Hard-Real-Time Programs

Allowing Cycle-Stealing Direct Memory Access I/O. Concurrent with Hard-Real-Time Programs To appear in: Int. Conf. on Parallel and Distributed Systems, ICPADS'96, June 3-6, 1996, Tokyo Allowing Cycle-Stealing Direct Memory Access I/O Concurrent with Hard-Real-Time Programs Tai-Yi Huang, Jane

More information

History-based Schemes and Implicit Path Enumeration

History-based Schemes and Implicit Path Enumeration History-based Schemes and Implicit Path Enumeration Claire Burguière and Christine Rochange Institut de Recherche en Informatique de Toulouse Université Paul Sabatier 6 Toulouse cedex 9, France {burguier,rochange}@irit.fr

More information

Worst-Case Utilization Bound for EDF Scheduling on Real-Time Multiprocessor Systems

Worst-Case Utilization Bound for EDF Scheduling on Real-Time Multiprocessor Systems Worst-Case Utilization Bound for EDF Scheduling on Real-Time Multiprocessor Systems J.M. López, M. García, J.L. Díaz, D.F. García University of Oviedo Department of Computer Science Campus de Viesques,

More information

Summary: Open Questions:

Summary: Open Questions: Summary: The paper proposes an new parallelization technique, which provides dynamic runtime parallelization of loops from binary single-thread programs with minimal architectural change. The realization

More information

An Approach to Task Attribute Assignment for Uniprocessor Systems

An Approach to Task Attribute Assignment for Uniprocessor Systems An Approach to ttribute Assignment for Uniprocessor Systems I. Bate and A. Burns Real-Time Systems Research Group Department of Computer Science University of York York, United Kingdom e-mail: fijb,burnsg@cs.york.ac.uk

More information

Transforming Execution-Time Boundable Code into Temporally Predictable Code

Transforming Execution-Time Boundable Code into Temporally Predictable Code Transforming Execution-Time Boundable Code into Temporally Predictable Code Peter Puschner Institut for Technische Informatik. Technische Universitdt Wien, Austria Abstract: Traditional Worst-Case Execution-Time

More information

Conditional Elimination through Code Duplication

Conditional Elimination through Code Duplication Conditional Elimination through Code Duplication Joachim Breitner May 27, 2011 We propose an optimizing transformation which reduces program runtime at the expense of program size by eliminating conditional

More information

Timing Analysis Enhancement for Synchronous Program

Timing Analysis Enhancement for Synchronous Program Timing Analysis Enhancement for Synchronous Program Extended Abstract Pascal Raymond, Claire Maiza, Catherine Parent-Vigouroux, Fabienne Carrier, and Mihail Asavoae Grenoble-Alpes University Verimag, Centre

More information

Run-Time Environments/Garbage Collection

Run-Time Environments/Garbage Collection Run-Time Environments/Garbage Collection Department of Computer Science, Faculty of ICT January 5, 2014 Introduction Compilers need to be aware of the run-time environment in which their compiled programs

More information

Single-Path Programming on a Chip-Multiprocessor System

Single-Path Programming on a Chip-Multiprocessor System Single-Path Programming on a Chip-Multiprocessor System Martin Schoeberl, Peter Puschner, and Raimund Kirner Vienna University of Technology, Austria mschoebe@mail.tuwien.ac.at, {peter,raimund}@vmars.tuwien.ac.at

More information

The Cheapest Way to Obtain Solution by Graph-Search Algorithms

The Cheapest Way to Obtain Solution by Graph-Search Algorithms Acta Polytechnica Hungarica Vol. 14, No. 6, 2017 The Cheapest Way to Obtain Solution by Graph-Search Algorithms Benedek Nagy Eastern Mediterranean University, Faculty of Arts and Sciences, Department Mathematics,

More information

A CSP Search Algorithm with Reduced Branching Factor

A CSP Search Algorithm with Reduced Branching Factor A CSP Search Algorithm with Reduced Branching Factor Igor Razgon and Amnon Meisels Department of Computer Science, Ben-Gurion University of the Negev, Beer-Sheva, 84-105, Israel {irazgon,am}@cs.bgu.ac.il

More information

Worst Case Execution Time Analysis for Synthesized Hardware

Worst Case Execution Time Analysis for Synthesized Hardware Worst Case Execution Time Analysis for Synthesized Hardware Jun-hee Yoo ihavnoid@poppy.snu.ac.kr Seoul National University, Seoul, Republic of Korea Xingguang Feng fengxg@poppy.snu.ac.kr Seoul National

More information

6.1 Motivation. Fixed Priorities. 6.2 Context Switch. Real-time is about predictability, i.e. guarantees. Real-Time Systems

6.1 Motivation. Fixed Priorities. 6.2 Context Switch. Real-time is about predictability, i.e. guarantees. Real-Time Systems Real-Time Systems Summer term 2017 6.1 Motivation 6.1 Motivation Real-Time Systems 6 th Chapter Practical Considerations Jafar Akhundov, M.Sc. Professur Betriebssysteme Real-time is about predictability,

More information

Evaluating Static Worst-Case Execution-Time Analysis for a Commercial Real-Time Operating System

Evaluating Static Worst-Case Execution-Time Analysis for a Commercial Real-Time Operating System Evaluating Static Worst-Case Execution-Time Analysis for a Commercial Real-Time Operating System Daniel Sandell Master s thesis D-level, 20 credits Dept. of Computer Science Mälardalen University Supervisor:

More information

Embedded Systems Lecture 11: Worst-Case Execution Time. Björn Franke University of Edinburgh

Embedded Systems Lecture 11: Worst-Case Execution Time. Björn Franke University of Edinburgh Embedded Systems Lecture 11: Worst-Case Execution Time Björn Franke University of Edinburgh Overview Motivation Worst-Case Execution Time Analysis Types of Execution Times Measuring vs. Analysing Flow

More information

Scan Scheduling Specification and Analysis

Scan Scheduling Specification and Analysis Scan Scheduling Specification and Analysis Bruno Dutertre System Design Laboratory SRI International Menlo Park, CA 94025 May 24, 2000 This work was partially funded by DARPA/AFRL under BAE System subcontract

More information

Modeling Systems Using Design Patterns

Modeling Systems Using Design Patterns Modeling Systems Using Design Patterns Jaroslav JAKUBÍK Slovak University of Technology Faculty of Informatics and Information Technologies Ilkovičova 3, 842 16 Bratislava, Slovakia jakubik@fiit.stuba.sk

More information

Combining Analyses, Combining Optimizations - Summary

Combining Analyses, Combining Optimizations - Summary Combining Analyses, Combining Optimizations - Summary 1. INTRODUCTION Cliff Click s thesis Combining Analysis, Combining Optimizations [Click and Cooper 1995] uses a structurally different intermediate

More information

F-Soft: Software Verification Platform

F-Soft: Software Verification Platform F-Soft: Software Verification Platform F. Ivančić, Z. Yang, M.K. Ganai, A. Gupta, I. Shlyakhter, and P. Ashar NEC Laboratories America, 4 Independence Way, Suite 200, Princeton, NJ 08540 fsoft@nec-labs.com

More information

HW/SW Codesign. WCET Analysis

HW/SW Codesign. WCET Analysis HW/SW Codesign WCET Analysis 29 November 2017 Andres Gomez gomeza@tik.ee.ethz.ch 1 Outline Today s exercise is one long question with several parts: Basic blocks of a program Static value analysis WCET

More information

Efficient Microarchitecture Modeling and Path Analysis for Real-Time Software. Yau-Tsun Steven Li Sharad Malik Andrew Wolfe

Efficient Microarchitecture Modeling and Path Analysis for Real-Time Software. Yau-Tsun Steven Li Sharad Malik Andrew Wolfe Efficient Microarchitecture Modeling and Path Analysis for Real-Time Software Yau-Tsun Steven Li Sharad Malik Andrew Wolfe 1 Introduction Paper examines the problem of determining the bound on the worst

More information

CSE 417 Branch & Bound (pt 4) Branch & Bound

CSE 417 Branch & Bound (pt 4) Branch & Bound CSE 417 Branch & Bound (pt 4) Branch & Bound Reminders > HW8 due today > HW9 will be posted tomorrow start early program will be slow, so debugging will be slow... Review of previous lectures > Complexity

More information

Probabilistic Worst-Case Response-Time Analysis for the Controller Area Network

Probabilistic Worst-Case Response-Time Analysis for the Controller Area Network Probabilistic Worst-Case Response-Time Analysis for the Controller Area Network Thomas Nolte, Hans Hansson, and Christer Norström Mälardalen Real-Time Research Centre Department of Computer Engineering

More information

Optimizing Closures in O(0) time

Optimizing Closures in O(0) time Optimizing Closures in O(0 time Andrew W. Keep Cisco Systems, Inc. Indiana Univeristy akeep@cisco.com Alex Hearn Indiana University adhearn@cs.indiana.edu R. Kent Dybvig Cisco Systems, Inc. Indiana University

More information

Real-time integrated prefetching and caching

Real-time integrated prefetching and caching Real-time integrated prefetching and caching Peter Sanders Johannes Singler Rob van Stee September 26, 2012 Abstract The high latencies for access to background memory like hard disks or flash memory can

More information

Response Time Analysis of Asynchronous Real-Time Systems

Response Time Analysis of Asynchronous Real-Time Systems Response Time Analysis of Asynchronous Real-Time Systems Guillem Bernat Real-Time Systems Research Group Department of Computer Science University of York York, YO10 5DD, UK Technical Report: YCS-2002-340

More information

Sireesha R Basavaraju Embedded Systems Group, Technical University of Kaiserslautern

Sireesha R Basavaraju Embedded Systems Group, Technical University of Kaiserslautern Sireesha R Basavaraju Embedded Systems Group, Technical University of Kaiserslautern Introduction WCET of program ILP Formulation Requirement SPM allocation for code SPM allocation for data Conclusion

More information

Branch-and-Bound Algorithms for Constrained Paths and Path Pairs and Their Application to Transparent WDM Networks

Branch-and-Bound Algorithms for Constrained Paths and Path Pairs and Their Application to Transparent WDM Networks Branch-and-Bound Algorithms for Constrained Paths and Path Pairs and Their Application to Transparent WDM Networks Franz Rambach Student of the TUM Telephone: 0049 89 12308564 Email: rambach@in.tum.de

More information

17/05/2018. Outline. Outline. Divide and Conquer. Control Abstraction for Divide &Conquer. Outline. Module 2: Divide and Conquer

17/05/2018. Outline. Outline. Divide and Conquer. Control Abstraction for Divide &Conquer. Outline. Module 2: Divide and Conquer Module 2: Divide and Conquer Divide and Conquer Control Abstraction for Divide &Conquer 1 Recurrence equation for Divide and Conquer: If the size of problem p is n and the sizes of the k sub problems are

More information

Interprocess Communication By: Kaushik Vaghani

Interprocess Communication By: Kaushik Vaghani Interprocess Communication By: Kaushik Vaghani Background Race Condition: A situation where several processes access and manipulate the same data concurrently and the outcome of execution depends on the

More information

Statistical Timing Analysis Using Bounds and Selective Enumeration

Statistical Timing Analysis Using Bounds and Selective Enumeration IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 22, NO. 9, SEPTEMBER 2003 1243 Statistical Timing Analysis Using Bounds and Selective Enumeration Aseem Agarwal, Student

More information

Module 1 Lecture Notes 2. Optimization Problem and Model Formulation

Module 1 Lecture Notes 2. Optimization Problem and Model Formulation Optimization Methods: Introduction and Basic concepts 1 Module 1 Lecture Notes 2 Optimization Problem and Model Formulation Introduction In the previous lecture we studied the evolution of optimization

More information

ABC basics (compilation from different articles)

ABC basics (compilation from different articles) 1. AIG construction 2. AIG optimization 3. Technology mapping ABC basics (compilation from different articles) 1. BACKGROUND An And-Inverter Graph (AIG) is a directed acyclic graph (DAG), in which a node

More information

Fast optimal task graph scheduling by means of an optimized parallel A -Algorithm

Fast optimal task graph scheduling by means of an optimized parallel A -Algorithm Fast optimal task graph scheduling by means of an optimized parallel A -Algorithm Udo Hönig and Wolfram Schiffmann FernUniversität Hagen, Lehrgebiet Rechnerarchitektur, 58084 Hagen, Germany {Udo.Hoenig,

More information

Graphical Tool For SC Automata.

Graphical Tool For SC Automata. Graphical Tool For SC Automata. Honours Project: 2000 Dr. Padmanabhan Krishnan 1 Luke Haslett 1 Supervisor Abstract SC automata are a variation of timed automata which are closed under complementation.

More information

Cover Page. The handle holds various files of this Leiden University dissertation

Cover Page. The handle   holds various files of this Leiden University dissertation Cover Page The handle http://hdl.handle.net/1887/22891 holds various files of this Leiden University dissertation Author: Gouw, Stijn de Title: Combining monitoring with run-time assertion checking Issue

More information

Real-Time Adaptive A*

Real-Time Adaptive A* Real-Time Adaptive A* Sven Koenig Computer Science Department University of Southern California Los Angeles, CA - skoenig@usc.edu Maxim Likhachev Computer Science Department Carnegie Mellon University

More information

Hardware-Software Codesign. 9. Worst Case Execution Time Analysis

Hardware-Software Codesign. 9. Worst Case Execution Time Analysis Hardware-Software Codesign 9. Worst Case Execution Time Analysis Lothar Thiele 9-1 System Design Specification System Synthesis Estimation SW-Compilation Intellectual Prop. Code Instruction Set HW-Synthesis

More information

Time Triggered and Event Triggered; Off-line Scheduling

Time Triggered and Event Triggered; Off-line Scheduling Time Triggered and Event Triggered; Off-line Scheduling Real-Time Architectures -TUe Gerhard Fohler 2004 Mälardalen University, Sweden gerhard.fohler@mdh.se Real-time: TT and ET Gerhard Fohler 2004 1 Activation

More information

Offloading Java to Graphics Processors

Offloading Java to Graphics Processors Offloading Java to Graphics Processors Peter Calvert (prc33@cam.ac.uk) University of Cambridge, Computer Laboratory Abstract Massively-parallel graphics processors have the potential to offer high performance

More information

Application of the Computer Capacity to the Analysis of Processors Evolution. BORIS RYABKO 1 and ANTON RAKITSKIY 2 April 17, 2018

Application of the Computer Capacity to the Analysis of Processors Evolution. BORIS RYABKO 1 and ANTON RAKITSKIY 2 April 17, 2018 Application of the Computer Capacity to the Analysis of Processors Evolution BORIS RYABKO 1 and ANTON RAKITSKIY 2 April 17, 2018 arxiv:1705.07730v1 [cs.pf] 14 May 2017 Abstract The notion of computer capacity

More information

Scheduling with Bus Access Optimization for Distributed Embedded Systems

Scheduling with Bus Access Optimization for Distributed Embedded Systems 472 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 8, NO. 5, OCTOBER 2000 Scheduling with Bus Access Optimization for Distributed Embedded Systems Petru Eles, Member, IEEE, Alex

More information

Predicting the Worst-Case Execution Time of the Concurrent Execution. of Instructions and Cycle-Stealing DMA I/O Operations

Predicting the Worst-Case Execution Time of the Concurrent Execution. of Instructions and Cycle-Stealing DMA I/O Operations ACM SIGPLAN Workshop on Languages, Compilers and Tools for Real-Time Systems, La Jolla, California, June 1995. Predicting the Worst-Case Execution Time of the Concurrent Execution of Instructions and Cycle-Stealing

More information

Summary: Issues / Open Questions:

Summary: Issues / Open Questions: Summary: The paper introduces Transitional Locking II (TL2), a Software Transactional Memory (STM) algorithm, which tries to overcomes most of the safety and performance issues of former STM implementations.

More information

3 No-Wait Job Shops with Variable Processing Times

3 No-Wait Job Shops with Variable Processing Times 3 No-Wait Job Shops with Variable Processing Times In this chapter we assume that, on top of the classical no-wait job shop setting, we are given a set of processing times for each operation. We may select

More information

Chapter 5. Quicksort. Copyright Oliver Serang, 2018 University of Montana Department of Computer Science

Chapter 5. Quicksort. Copyright Oliver Serang, 2018 University of Montana Department of Computer Science Chapter 5 Quicsort Copyright Oliver Serang, 08 University of Montana Department of Computer Science Quicsort is famous because of its ability to sort in-place. I.e., it directly modifies the contents of

More information

Predictable paging in real-time systems: an ILP formulation

Predictable paging in real-time systems: an ILP formulation Predictable paging in real-time systems: an ILP formulation Damien Hardy Isabelle Puaut Université Européenne de Bretagne / IRISA, Rennes, France Abstract Conventionally, the use of virtual memory in real-time

More information

Software Optimization Using Hardware Synthesis Techniques Bret Victor,

Software Optimization Using Hardware Synthesis Techniques Bret Victor, EE 219B LOGIC SYNTHESIS, MAY 2000 Software Optimization Using Hardware Synthesis Techniques Bret Victor, bret@eecs.berkeley.edu Abstract Although a myriad of techniques exist in the hardware design domain

More information

Verification and Validation of X-Sim: A Trace-Based Simulator

Verification and Validation of X-Sim: A Trace-Based Simulator http://www.cse.wustl.edu/~jain/cse567-06/ftp/xsim/index.html 1 of 11 Verification and Validation of X-Sim: A Trace-Based Simulator Saurabh Gayen, sg3@wustl.edu Abstract X-Sim is a trace-based simulator

More information

A Lost Cycles Analysis for Performance Prediction using High-Level Synthesis

A Lost Cycles Analysis for Performance Prediction using High-Level Synthesis A Lost Cycles Analysis for Performance Prediction using High-Level Synthesis Bruno da Silva, Jan Lemeire, An Braeken, and Abdellah Touhafi Vrije Universiteit Brussel (VUB), INDI and ETRO department, Brussels,

More information

CIS 1.5 Course Objectives. a. Understand the concept of a program (i.e., a computer following a series of instructions)

CIS 1.5 Course Objectives. a. Understand the concept of a program (i.e., a computer following a series of instructions) By the end of this course, students should CIS 1.5 Course Objectives a. Understand the concept of a program (i.e., a computer following a series of instructions) b. Understand the concept of a variable

More information

REDUCTION IN RUN TIME USING TRAP ANALYSIS

REDUCTION IN RUN TIME USING TRAP ANALYSIS REDUCTION IN RUN TIME USING TRAP ANALYSIS 1 Prof. K.V.N.Sunitha 2 Dr V. Vijay Kumar 1 Professor & Head, CSE Dept, G.Narayanamma Inst.of Tech. & Science, Shaikpet, Hyderabad, India. 2 Dr V. Vijay Kumar

More information

Timing Analysis of Automatically Generated Code by MATLAB/Simulink

Timing Analysis of Automatically Generated Code by MATLAB/Simulink Timing Analysis of Automatically Generated Code by MATLAB/Simulink Rômulo Silva de Oliveira, Marcos Vinicius Linhares, Ricardo Bacha Borges Systems and Automation Department - DAS Federal University of

More information

INTRODUCTION TO ALGORITHMS

INTRODUCTION TO ALGORITHMS UNIT- Introduction: Algorithm: The word algorithm came from the name of a Persian mathematician Abu Jafar Mohammed Ibn Musa Al Khowarizmi (ninth century) An algorithm is simply s set of rules used to perform

More information

An analysis of object-based intelligent image

An analysis of object-based intelligent image An analysis of object-based intelligent image processing and retrieval system Abstract-In order to improve the process of analysis and retrieval of images, it is necessary to examine the execution of such

More information

Simplified design flow for embedded systems

Simplified design flow for embedded systems Simplified design flow for embedded systems 2005/12/02-1- Reuse of standard software components Knowledge from previous designs to be made available in the form of intellectual property (IP, for SW & HW).

More information

Theorem 2.9: nearest addition algorithm

Theorem 2.9: nearest addition algorithm There are severe limits on our ability to compute near-optimal tours It is NP-complete to decide whether a given undirected =(,)has a Hamiltonian cycle An approximation algorithm for the TSP can be used

More information

IMPROVING TIMING ANALYZABILITY THROUGH SOURCE CODE ANALYSIS AND TESTABILITY TRANSFORMATIONS IN REAL-TIME SYSTEMS. David Barrientos Velasco

IMPROVING TIMING ANALYZABILITY THROUGH SOURCE CODE ANALYSIS AND TESTABILITY TRANSFORMATIONS IN REAL-TIME SYSTEMS. David Barrientos Velasco IMPROVING TIMING ANALYZABILITY THROUGH SOURCE CODE ANALYSIS AND TESTABILITY TRANSFORMATIONS IN REAL-TIME SYSTEMS David Barrientos Velasco IMPROVING TIMING ANALYZABILITY THROUGH SOURCE CODE ANALYSIS AND

More information

A Hybrid Recursive Multi-Way Number Partitioning Algorithm

A Hybrid Recursive Multi-Way Number Partitioning Algorithm Proceedings of the Twenty-Second International Joint Conference on Artificial Intelligence A Hybrid Recursive Multi-Way Number Partitioning Algorithm Richard E. Korf Computer Science Department University

More information

How useful is the UML profile SPT without Semantics? 1

How useful is the UML profile SPT without Semantics? 1 How useful is the UML profile SPT without Semantics? 1 Susanne Graf, Ileana Ober VERIMAG 2, avenue de Vignate - F-38610 Gières - France e-mail:{susanne.graf, Ileana.Ober}@imag.fr http://www-verimag.imag.fr/~{graf,iober}

More information

A Lightweight Language for Software Product Lines Architecture Description

A Lightweight Language for Software Product Lines Architecture Description A Lightweight Language for Software Product Lines Architecture Description Eduardo Silva, Ana Luisa Medeiros, Everton Cavalcante, Thais Batista DIMAp Department of Informatics and Applied Mathematics UFRN

More information

CSL373: Lecture 5 Deadlocks (no process runnable) + Scheduling (> 1 process runnable)

CSL373: Lecture 5 Deadlocks (no process runnable) + Scheduling (> 1 process runnable) CSL373: Lecture 5 Deadlocks (no process runnable) + Scheduling (> 1 process runnable) Past & Present Have looked at two constraints: Mutual exclusion constraint between two events is a requirement that

More information

Data-Flow Based Detection of Loop Bounds

Data-Flow Based Detection of Loop Bounds Data-Flow Based Detection of Loop Bounds Christoph Cullmann and Florian Martin AbsInt Angewandte Informatik GmbH Science Park 1, D-66123 Saarbrücken, Germany cullmann,florian@absint.com, http://www.absint.com

More information

Set Manipulation with Boolean Functional Vectors for Symbolic Reachability Analysis

Set Manipulation with Boolean Functional Vectors for Symbolic Reachability Analysis Set Manipulation with Boolean Functional Vectors for Symbolic Reachability Analysis Amit Goel Department of ECE, Carnegie Mellon University, PA. 15213. USA. agoel@ece.cmu.edu Randal E. Bryant Computer

More information

EECS 583 Class 2 Control Flow Analysis LLVM Introduction

EECS 583 Class 2 Control Flow Analysis LLVM Introduction EECS 583 Class 2 Control Flow Analysis LLVM Introduction University of Michigan September 8, 2014 - 1 - Announcements & Reading Material HW 1 out today, due Friday, Sept 22 (2 wks)» This homework is not

More information

Mixed Criticality Scheduling in Time-Triggered Legacy Systems

Mixed Criticality Scheduling in Time-Triggered Legacy Systems Mixed Criticality Scheduling in Time-Triggered Legacy Systems Jens Theis and Gerhard Fohler Technische Universität Kaiserslautern, Germany Email: {jtheis,fohler}@eit.uni-kl.de Abstract Research on mixed

More information

Modeling Event Stream Hierarchies with Hierarchical Event Models

Modeling Event Stream Hierarchies with Hierarchical Event Models Modeling Event Stream Hierarchies with Hierarchical Event Models Jonas Rox, Rolf Ernst Institute of Computer and Communication Network Engineering Technical University of Braunschweig D-38106 Braunschweig

More information

Discrete Optimization. Lecture Notes 2

Discrete Optimization. Lecture Notes 2 Discrete Optimization. Lecture Notes 2 Disjunctive Constraints Defining variables and formulating linear constraints can be straightforward or more sophisticated, depending on the problem structure. The

More information

Compositional Schedulability Analysis of Hierarchical Real-Time Systems

Compositional Schedulability Analysis of Hierarchical Real-Time Systems Compositional Schedulability Analysis of Hierarchical Real-Time Systems Arvind Easwaran, Insup Lee, Insik Shin, and Oleg Sokolsky Department of Computer and Information Science University of Pennsylvania,

More information

Dirk Tetzlaff Technical University of Berlin

Dirk Tetzlaff Technical University of Berlin Software Engineering g for Embedded Systems Intelligent Task Mapping for MPSoCs using Machine Learning Dirk Tetzlaff Technical University of Berlin 3rd Workshop on Mapping of Applications to MPSoCs June

More information

Estimation of worst case latency of periodic tasks in a real time distributed environment

Estimation of worst case latency of periodic tasks in a real time distributed environment Estimation of worst case latency of periodic tasks in a real time distributed environment 1 RAMESH BABU NIMMATOORI, 2 Dr. VINAY BABU A, 3 SRILATHA C * 1 Research Scholar, Department of CSE, JNTUH, Hyderabad,

More information

Static WCET Analysis: Methods and Tools

Static WCET Analysis: Methods and Tools Static WCET Analysis: Methods and Tools Timo Lilja April 28, 2011 Timo Lilja () Static WCET Analysis: Methods and Tools April 28, 2011 1 / 23 1 Methods 2 Tools 3 Summary 4 References Timo Lilja () Static

More information

Intermediate Code Generation

Intermediate Code Generation Intermediate Code Generation In the analysis-synthesis model of a compiler, the front end analyzes a source program and creates an intermediate representation, from which the back end generates target

More information

A Data Centered Approach for Cache Partitioning in Embedded Real- Time Database System

A Data Centered Approach for Cache Partitioning in Embedded Real- Time Database System A Data Centered Approach for Cache Partitioning in Embedded Real- Time Database System HU WEI CHEN TIANZHOU SHI QINGSONG JIANG NING College of Computer Science Zhejiang University College of Computer Science

More information

B. V. Patel Institute of Business Management, Computer &Information Technology, UTU

B. V. Patel Institute of Business Management, Computer &Information Technology, UTU BCA-3 rd Semester 030010304-Fundamentals Of Operating Systems Unit: 1 Introduction Short Answer Questions : 1. State two ways of process communication. 2. State any two uses of operating system according

More information

3 SOLVING PROBLEMS BY SEARCHING

3 SOLVING PROBLEMS BY SEARCHING 48 3 SOLVING PROBLEMS BY SEARCHING A goal-based agent aims at solving problems by performing actions that lead to desirable states Let us first consider the uninformed situation in which the agent is not

More information

Leveraging Transitive Relations for Crowdsourced Joins*

Leveraging Transitive Relations for Crowdsourced Joins* Leveraging Transitive Relations for Crowdsourced Joins* Jiannan Wang #, Guoliang Li #, Tim Kraska, Michael J. Franklin, Jianhua Feng # # Department of Computer Science, Tsinghua University, Brown University,

More information

ITERATIVE MULTI-LEVEL MODELLING - A METHODOLOGY FOR COMPUTER SYSTEM DESIGN. F. W. Zurcher B. Randell

ITERATIVE MULTI-LEVEL MODELLING - A METHODOLOGY FOR COMPUTER SYSTEM DESIGN. F. W. Zurcher B. Randell ITERATIVE MULTI-LEVEL MODELLING - A METHODOLOGY FOR COMPUTER SYSTEM DESIGN F. W. Zurcher B. Randell Thomas J. Watson Research Center Yorktown Heights, New York Abstract: The paper presents a method of

More information

A Real Time GIS Approximation Approach for Multiphase Spatial Query Processing Using Hierarchical-Partitioned-Indexing Technique

A Real Time GIS Approximation Approach for Multiphase Spatial Query Processing Using Hierarchical-Partitioned-Indexing Technique International Journal of Scientific Research in Computer Science, Engineering and Information Technology 2017 IJSRCSEIT Volume 2 Issue 6 ISSN : 2456-3307 A Real Time GIS Approximation Approach for Multiphase

More information

Analyzing Real-Time Systems

Analyzing Real-Time Systems Analyzing Real-Time Systems Reference: Burns and Wellings, Real-Time Systems and Programming Languages 17-654/17-754: Analysis of Software Artifacts Jonathan Aldrich Real-Time Systems Definition Any system

More information

Lecture 12: An Overview of Scheduling Theory

Lecture 12: An Overview of Scheduling Theory Lecture 12: An Overview of Scheduling Theory [RTCS Ch 8] Introduction Execution Time Estimation Basic Scheduling Approaches Static Cyclic Scheduling Fixed Priority Scheduling Rate Monotonic Analysis Earliest

More information

I/O Efficieny of Highway Hierarchies

I/O Efficieny of Highway Hierarchies I/O Efficieny of Highway Hierarchies Riko Jacob Sushant Sachdeva Departement of Computer Science ETH Zurich, Technical Report 531, September 26 Abstract Recently, Sanders and Schultes presented a shortest

More information

Interprocedural Variable Liveness Analysis for Function Signature Recovery

Interprocedural Variable Liveness Analysis for Function Signature Recovery Interprocedural Variable Liveness Analysis for Function Signature Recovery MIGUEL ARAUJO AND AHMED BOUGACHA {maraujo@cs, ahmed.bougacha@sv}.cmu.edu Carnegie Mellon University April 30, 2014 Final Project

More information

Joint Entity Resolution

Joint Entity Resolution Joint Entity Resolution Steven Euijong Whang, Hector Garcia-Molina Computer Science Department, Stanford University 353 Serra Mall, Stanford, CA 94305, USA {swhang, hector}@cs.stanford.edu No Institute

More information

Searching with Partial Information

Searching with Partial Information Searching with Partial Information Above we (unrealistically) assumed that the environment is fully observable and deterministic Moreover, we assumed that the agent knows what the effects of each action

More information

Advanced Topics UNIT 2 PERFORMANCE EVALUATIONS

Advanced Topics UNIT 2 PERFORMANCE EVALUATIONS Advanced Topics UNIT 2 PERFORMANCE EVALUATIONS Structure Page Nos. 2.0 Introduction 4 2. Objectives 5 2.2 Metrics for Performance Evaluation 5 2.2. Running Time 2.2.2 Speed Up 2.2.3 Efficiency 2.3 Factors

More information

Complementary Graph Coloring

Complementary Graph Coloring International Journal of Computer (IJC) ISSN 2307-4523 (Print & Online) Global Society of Scientific Research and Researchers http://ijcjournal.org/ Complementary Graph Coloring Mohamed Al-Ibrahim a*,

More information

PRINCIPLES OF COMPILER DESIGN UNIT I INTRODUCTION TO COMPILERS

PRINCIPLES OF COMPILER DESIGN UNIT I INTRODUCTION TO COMPILERS Objective PRINCIPLES OF COMPILER DESIGN UNIT I INTRODUCTION TO COMPILERS Explain what is meant by compiler. Explain how the compiler works. Describe various analysis of the source program. Describe the

More information

Discrete planning (an introduction)

Discrete planning (an introduction) Sistemi Intelligenti Corso di Laurea in Informatica, A.A. 2017-2018 Università degli Studi di Milano Discrete planning (an introduction) Nicola Basilico Dipartimento di Informatica Via Comelico 39/41-20135

More information

Delay Estimation for Technology Independent Synthesis

Delay Estimation for Technology Independent Synthesis Delay Estimation for Technology Independent Synthesis Yutaka TAMIYA FUJITSU LABORATORIES LTD. 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, JAPAN, 211-88 Tel: +81-44-754-2663 Fax: +81-44-754-2664 E-mail:

More information

Concurrent & Distributed Systems Supervision Exercises

Concurrent & Distributed Systems Supervision Exercises Concurrent & Distributed Systems Supervision Exercises Stephen Kell Stephen.Kell@cl.cam.ac.uk November 9, 2009 These exercises are intended to cover all the main points of understanding in the lecture

More information

Algorithms for Integer Programming

Algorithms for Integer Programming Algorithms for Integer Programming Laura Galli November 9, 2016 Unlike linear programming problems, integer programming problems are very difficult to solve. In fact, no efficient general algorithm is

More information

Certification Authorities Software Team (CAST) Position Paper CAST-25

Certification Authorities Software Team (CAST) Position Paper CAST-25 Certification Authorities Software Team (CAST) Position Paper CAST-25 CONSIDERATIONS WHEN USING A QUALIFIABLE DEVELOPMENT ENVIRONMENT (QDE) IN CERTIFICATION PROJECTS COMPLETED SEPTEMBER 2005 (Rev 0) NOTE:

More information

Dr. Amotz Bar-Noy s Compendium of Algorithms Problems. Problems, Hints, and Solutions

Dr. Amotz Bar-Noy s Compendium of Algorithms Problems. Problems, Hints, and Solutions Dr. Amotz Bar-Noy s Compendium of Algorithms Problems Problems, Hints, and Solutions Chapter 1 Searching and Sorting Problems 1 1.1 Array with One Missing 1.1.1 Problem Let A = A[1],..., A[n] be an array

More information