Digital Design. Chapter 4. Principles Of. Simplification of Boolean Functions

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1 Principles Of Digital Design Chapter 4 Simplification of Boolean Functions Karnaugh Maps Don t Care Conditions Technology Mapping Optimization, Conversions, Decomposing, Retiming

2 Boolean Cubes for n =, 2, 3, and 4 n = n = 2 n = 3 n = 4 Copyright by Daniel D. Gajski 2

3 Boolean Functions and Boolean Cubes Each Boolean n-cube represents a Boolean function of n variables Each vertex represents a minterm Each m-subcube represents 2 m minterms, m < n, with the same n m literals Each m-subcube of -minterm represent a product of n m literals = l l 2 l n m (x n m + x n m + 2 x n + x n m + x n m + 2 x n + + x n m + x n m + 2 x n ) = l l 2 l n m For any Boolean function a prime implicant is a subcube not contained in any other prime implicant As essential prime implicant is a subcube that contains a - minterm that is not included in any other prime implicant Copyright by Daniel D. Gajski 3

4 Representation of Carry and Sum Functions with Boolean Cubes c i x i y i c i + s i Truth Table Carry Function c i + Sum Function s i Copyright by Daniel D. Gajski 4

5 Map Representation (Karnaugh) maps define Boolean functions Map representation is equivalent to truth tables, Boolean expressions and Boolean cube representation Map aid in visually identifying prime implicants and essential prime implicants in each Boolean function Maps are used for manual optimization of Boolean functions Copyright by Daniel D. Gajski 5

6 Boolean Subcubes and Corresponding Karnaugh Maps for n =, 2, 3, and 4 x y x m m n = m 2 m 3 n = 2 xy zw yz x m m m 3 m 2 m m m 3 m 2 m 4 m 5 m 7 m 6 m 4 m 5 m 7 m 6 m 2 m 3 m 5 m 4 n = 3 m m 9 m m n = 4 Copyright by Daniel D. Gajski 6

7 2 variable variable Map x y x y x y x y Subcube x Subcube y xy 2 xy Subcube x Map Organization Example of -subcubes Example: x y AND OR XOR Truth Table x y x y x y Copyright by Daniel D. Gajski AND 7 OR XOR

8 Three variable Map x yz x y z 3 2 x y z x yz x yz xy z xy z xyz xyz Map Organization x yz 3 2 Subcube z Subcube z Subcube x Example of 2-subcubes x yz 3 2 Subcube x y Subcube yz Subcube xz Example of -subcubes Copyright by Daniel D. Gajski

9 Map Representation of Carry and Sum Functions c i x i y i c i + s i c i x i y i Carry Function c i x i y i c i Sum Function s i 7 6 Truth Table Copyright by Daniel D. Gajski 9

10 Four variable Map zw xy 3 2 x y z w x y z w x y zw x y zw x yz w x yz w x yzw x yzw xyz w xyz w xyzw xyzw 9 xy z w xy z w xy zw xy zw Map Organization zw zw xy xy 3 2 Subcube y w 3 2 Subcube x Subcube x y Subcube w Subcube xz Copyright by Daniel D. Gajski Example of 2-subcubes Example of 3-subcubes

11 Representation of Greater-than than and Less-than Functions in Maps x x y y x x y y Greater Less Equal Than Than Truth Table y y x x Greater-than Function G = x y + x y y + x x y L = x y + x x y + x y y Less-than Function Copyright by Daniel D. Gajski

12 Five variable variable Map xy zw v = v = x y z w v x y z wv x y zwv x y zw v x y z w v x y z wv x y zwv x y zw v x yz w v x yz wv x yzwv x yzw v x yz w v x yz wv x yzwv x yzw v xyz w v xyz wv xyzwv xyzw v xyz w v xyz wv xyzwv xyzw v xy z w v xy z wv xy zwv xy zw v xy z w v xy z wv xy zwv xy zw v Map Organization xy zw v = v = x vw xz zw Copyright by Daniel D. Gajski 2 Example of 3-subsubes and 4-subcubes

13 Six variable Map xy zw v = v = xy zw v = v = m 3 2 m m 3 m m 6 m 7 m 9 m m m 5 m 7 m m 2 m 2 m 23 m u = m 2 m 3 m 5 m 4 9 m m 9 m m m 2 m 29 m 3 m m 24 m 25 m 27 m 26 u = x v m 32 m 33 m 35 m m 4 m 49 m 5 m u = m 36 m 37 m 39 m m 44 m 45 m 47 m m 42 m 53 m 55 m m 6 m 6 m 63 m 62 u = xz m 4 m 4 m 43 m m 56 m 57 m 59 m Map Organization z w Example of 4-subcubes Copyright by Daniel D. Gajski 3

14 Boolean Simplification with Map Method Truth table, canonical form or standard form Generate map Determine prime implicants Select essential prime implicants Find minimal cover Standard form Copyright by Daniel D. Gajski 4

15 Boolean Simplification with Map Method Example: Problem: xy Maps method Using the map method, simplify the Boolean function zw F = w y z + wz + xyz + w y 3 2 xy zw Map Organization Prime Implicants in the Map Copyright by Daniel D. Gajski PI List: w z, wz,, yz, w y EPI List: w z, wz Cover List: () w z, wz,, yz (2) w z, wz, w y 5

16 Selection of Prime Implicants Example: Problem: Selection of prime implicants Simplify the Boolean function F = w x yz + w xy + wxz + wx y + w x y z xy zw PI List: w x z, w xy, wxz, wx y, x y z, wy z,, xyz, w yz EPI List: empty Cover List: () w x z, w xy, wxz, wx y (2) x y z, wy z,, xyz, w yz Copyright by Daniel D. Gajski 6

17 Don t Care Conditions Completely specified functions have a value assigned for every minterm Incompletely specified functions do not have values assigned for some minterms which are called don t care minterms (d minterms) or don t care conditions Don t care minterms can be assigned any value during simplifications in order to simplify Boolean expressions Copyright by Daniel D. Gajski 7

18 Don t Care Conditions Example: Problem: Don t care conditions Derive Boolean expressions for the 9 s s complement of a BCD digit x 3 x 2 x x x 3 x 2 x x Digits Nine s Complements Decimal BCD BCD Decimal x 3 x 2 x x x 3 x 2 x x Nine s Complement Table x 3 x 2 x x X X X X X X y 3 = x 3 x 2 x y 2 = x 2 x x x x 3 x 2 X X X X X X 4 X 2 X X X X X X X X X X X Copyright by Daniel D. Gajski y = x y = x Map Representation

19 Technology Mapping for Gate Arrays Gate arrays contain only one type of m-input gate (such as 3-input NOR, 3-input NAND) Technology mapping is a transformation of Boolean expressions into a logic schematic containing only this type of gate Technology mapping consist of three tasks Conversion replaces each operator with an operator representing the gate function given in the gate array Optimization eliminates unnecessary inverters Decomposition replaces a n-input gate with an m-input gate available in the gate array Copyright by Daniel D. Gajski 9

20 Conversion and Optimization Rule : Rule 2: Rule 3: Rule 4: Conversion Rules Rule 5: Conversion Procedure: Optimization Rules Replace AND and OR gates with NAND or NOR gates by using Rules 4, and eliminate double inverters whenever possible Copyright by Daniel D. Gajski 2

21 Translation of Standard Terms to NAND and NOR Schematics Form Type Standard Form Implementation NAND Implementation NOR Implementation Sum of products Product of sums Copyright by Daniel D. Gajski 2

22 Conversion to NAND (NOR) Gates Example: Problem: Conversion to NAND (NOR) gates Derive the NAND and NOR implementations of the carry function x i 2.4 x i.4 x i y i c i 3 2 y i c i c i + y i.4. c i + c i NAND Implementation Map Definition Carry Function c i + c i + = x i y i + x i c i + y i c i c i + = (x i + y i )(x i + c i )(y i + c i ) Standard Forms x i y i x i.4 c i + y i.4. c i + c i 2.4 c i.4 NOR Implementation Copyright by Daniel D. Gajski 22

23 Decomposition of input AND Gate into 3 input 3 AND Gates Level Number Number of Inputs Number of Gates [ / 3] = ( 3([ / 3])) = 4 + (4 3([4 / 3])) = 2 [4 / 3] = [2 / 3] = Input and Gate Computation on Each Level One Possible Decomposition Alternative Decomposition Copyright by Daniel D. Gajski 23

24 Technology Mapping for Gate Arrays Example: Technology mapping for gate arrays Problem: Implement the sum function using 3 input 3 NAND gates c i x i y i c i x i y i s i s i x i y i c i AND OR Implementation Conversion to NAND Network c i x i y i c i x i y i Map Definition Sum Function s i s i s i Copyright by Daniel D. Gajski OR Gate Decomposition 24 Optimized NAND Network

25 Design Retiming g 3 g 2 Example: Design retiming p 2 g Problem: Implement 4 bit 4 carry-look look-ahead function c 4 = g 3 + g 2 + p 2 g + p 2 p g + p 2 p p c NAND gates using 3 input3 NAND p p c p 2 g p 2 p c 4 AND-OR Implementation g 3 g 3 g 2 g 2 p 2 g p 2 g p p p 2 g p 2 c 4 p p p 2 g p 2 c 4 c p c p Decomposition of AND-OR Implementation Performance Optimized Decomposition g 3 g 3 g 2. g 2.. p 2 g. p 2 g. p p p 2 g p c 4 p p p 2 g p c 4 c p. c p. NAND Implementation of Above Delay =.2ns Copyright by Daniel D. Gajski 25 Performance Optimized NAND Implementation Delay = 6.4ns

26 Technology Mapping Procedure for Gate Arrays Start Decompose Convert Eliminate invertors I/O delay OK? no yes Done Retime Copyright by Daniel D. Gajski 26

27 Technology Mapping for Custom Libraries Libraries contain gates with different functions and different delays Technology mapping means covering schematic with library gates Minimize delay on critical paths Minimize cost on non-critical paths Copyright by Daniel D. Gajski 27

28 Technology Mapping for Custom Libraries Example: Technology mapping for custom libraries Problem: Convert the expression w z + z(w + y) y into a logic schematic using any of the gates Convert the expression into a logic schematic using any of the gates defined in the digital logic gates, multiple-input input gates, and complex gates libraries y y.4 w z F w z 2. F AND OR Implementation (Delay = 7.2ns, Cost = 2) Alternative A (Delay = 5.4ns, Cost = 2) y w z F y w z F NAND Implementation (Delay =5.2ns, Cost = 22) Alternative B (Delay = 3.ns, Cost = 2) y w z.4 B.4.4 A.4 F y w z F Copyright by Daniel D. Gajski Two Possible Conversions 2 Cost Optimized Alternative B (Delay = 3.ns, Cost = )

29 Conversion Procedure for Custom Libraries Start Convert to NAND schematic Select a path Select gate Select a library component Record replacement gain no no no All paths considered? Recompute Delay Select maximum gain replacement yes All gates considered? yes All components considered? yes Done Copyright by Daniel D. Gajski 29

30 Chapter Summary Simplification of Boolean functions by Map method (visual) Technology mapping for gate arrays Decomposition Conversion Optimization Retiming Technology mapping for custom libraries by schematic covering with complex gates with Time optimization on circuit paths Cost optimization on non-critical paths Copyright by Daniel D. Gajski 3

Gate-Level Minimization. BME208 Logic Circuits Yalçın İŞLER

Gate-Level Minimization. BME208 Logic Circuits Yalçın İŞLER Gate-Level Minimization BME28 Logic Circuits Yalçın İŞLER islerya@yahoo.com http://me.islerya.com Complexity of Digital Circuits Directly related to the complexity of the algebraic expression we use to