VLSI Testing. Lecture Fall 2003
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1 VLSI Testing Lecture Fall 23
2 Announcement Homework 9 is due next Thursday (/2) Exam II is on Tuesday (/8) in class Review Session: When: Next Monday (/7) afternoon, 4pm 6pm Where: B3, HH 2
3 Outline efects and Faults Reasons for IC malfunctioning Fault Modeling Types of faults (Stuck-At, bridge, Stuck Open) Automatic Test Pattern Generation Path elay Fault esign for Testability 3
4 Why Testing? Manufacturing is imperfect No. of good chips on wafer Y = Total no. of chips Yield (Y) depends on technology, chip area and layout Y decreases as the area of chip is increased efect density () Modern technologies yield a value of -5 defects/cm 2 Yield starts out low (~%) moves up (95%) High quality expectation The earlier you detect a fault, the cheaper it is to fix 4
5 Reasons for IC Malfunction - Contamination, efects and Faults Contamination / Instabilities - Process induced impurities and random fluctuations of process conditions efects - Permanent deformation in IC layer which may but does not have to result in fault Faults - Functional misbehaviors i.e. IC malfunctions 5
6 Reasons for IC Malfunction - efects and Faults B C 3 V M9 M M2 M3 M4 C OUT V Metal Poly Contact N N3 3 A C M N+ N B A M23 M24 M25 M26 M27 M28 GN P N2 N3 GN B C 3 6
7 Reasons for IC Malfunction - efects and Faults B A M M9 M N M3 N3 M2 M4 V C OUT N3 C M25 M24 M23 N2 M26 N4 M27 M28 GN 7
8 Reasons for IC Malfunction - efects and Faults B C 3 V V N M9 M Metal M9 M2 M4 Poly N3 M3 C OUT Contact 3 A C M N+ N B A M25 M27 M28 P N2 N3 GN M23 M24 M26 GN B C 3 8
9 Reasons for IC Malfunction - efects and Faults C out B A C M M9 M M2 M4 M25 M24 M23 M3 M26 M27 M28 V C OUT GN GN A B C efect no N - N3 short yes 9
10 Outline efects and Faults Reasons for IC malfunctioning Fault Modeling Types of faults (Stuck-At, bridge, Stuck Open) Automatic Test Pattern Generation Path elay Fault esign for Testability
11 Test Complexity In n Combinational Logic Out Exhaustive test 2 n + m Q Q Q Q clock Circuit with n = 25 and m = 5 µsec/test Exhaustive test time is over billion years! (Registers make life harder!) Registers m
12 Testing Strategies Functional Test: (go/no go) oes the part work? o this fast & cheap iagnostic Test: What in the chip is broken? Parametric Test: What is: max clock frequency min supply voltage max operating temp 2
13 Test Implementation Runs Test Vectors/Programs on evice Under Test (UT) Goal: Find a SMALL set of test vectors that has a BIG fault coverage Testers Clock rate in the range of GHz Resolutions measured in psec Large very fast memory Cost - 5 million dollars 3
14 Fault Models Modeling physical faults is complex Need models that simplify the behavior of faults a b c d f g h x e 4
15 Stuck-At Fault Stuck-at- a b c d f g h S-A- x e Stuck-at- a b c d f g h S-A- x e 5
16 Bridge & Stuck Open a b c d e f g h x Bridging fault a b c d e f g h x Open fault 6
17 Automatic Test Pattern Generation (ATPG) Given a logic circuit: Generate test program to cover all SA faults The -Algorithm The -Calculus Problem: Reconvergent Fanouts 7
18 -Algorithm Step : Choose a fault to insert Select from a fault dictionary Step 2: Activate (excite) the fault rive the faulty node to the opposite value of the fault Example: for SA-, drive the node to Step 3: Sensitize a path to an output Propagate the fault so that it can be observed at the output pin 8
19 Path Sensitization Goals: etermine input pattern that makes a fault controllable (triggers the fault, and makes its impact visible at the output nodes) Fault enabling Fault propagation sa Out Techniques Used: -algorithm, Podem 9
20 -Algorithm a b c d f g h x = / a b c d e f g h S-A- x value in good ckt = / value in faulty ckt e 2
21 2 -Algorithm A =NOT(A) B A = AB Five value logic simulation
22 -Algorithm Five value logic simulation A B = A + B 22
23 -Algorithm / = a b c d e f g h S-A- x 23
24 -Algorithm / = a b c d f g h x Conflict! Need backtracks Reconvergent Fanout x 24
25 Fault Simulation Test Program Random Number Generator, Genetic Algorithm, etc. Fault Free Circuit Circuit w/ One Fault Compare 25
26 Path elay Fault A defect can affect the speed of a path in the circuit Let s see a Path elay Fault example T a b slow slow c d e slow T+ T 26
27 Path elay Fault Path c-g2-g4-g5-x a b c d e g g2 g3 g4 g5 x 27
28 Outline efects and Faults Reasons for IC malfunctioning Fault Modeling Types of faults (Stuck-At, bridge, Stuck Open) Automatic Test Pattern Generation Path elay Fault esign for Testability 28
29 Scan-based Test ScanIn Modified to support two operation modes ScanOut In Register Combinational Logic A Register Combinational Logic B Out 29
30 Scan Based Methods Logic Logic Logic R R R R Level Sensitive Scan esign (LSS) - IBM Test Mode: OFF Test Mode: ON R L R L R R R 3
31 Boundary Scan (JTAG: IEEE 49.b) Printed-circuit board Logic Packaged IC Scan-in Scan-out si so scan path normal interconnect Bonding Pad Board testing becomes as problematic as chip testing 3
32 Built-In Self-Testing (BIST) (Sub)-Circuit Stimulus Generator Under Test Response Analyzer Test Controller Rapidly becoming more important with increasing chip-complexity and larger modules 32
33 Linear-Feedback Shift Register (LFSR) R R R S S S 2 Pseudo-Random Pattern Generator 33
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