VLSI Testing. Lecture Fall 2003

Size: px
Start display at page:

Download "VLSI Testing. Lecture Fall 2003"

Transcription

1 VLSI Testing Lecture Fall 23

2 Announcement Homework 9 is due next Thursday (/2) Exam II is on Tuesday (/8) in class Review Session: When: Next Monday (/7) afternoon, 4pm 6pm Where: B3, HH 2

3 Outline efects and Faults Reasons for IC malfunctioning Fault Modeling Types of faults (Stuck-At, bridge, Stuck Open) Automatic Test Pattern Generation Path elay Fault esign for Testability 3

4 Why Testing? Manufacturing is imperfect No. of good chips on wafer Y = Total no. of chips Yield (Y) depends on technology, chip area and layout Y decreases as the area of chip is increased efect density () Modern technologies yield a value of -5 defects/cm 2 Yield starts out low (~%) moves up (95%) High quality expectation The earlier you detect a fault, the cheaper it is to fix 4

5 Reasons for IC Malfunction - Contamination, efects and Faults Contamination / Instabilities - Process induced impurities and random fluctuations of process conditions efects - Permanent deformation in IC layer which may but does not have to result in fault Faults - Functional misbehaviors i.e. IC malfunctions 5

6 Reasons for IC Malfunction - efects and Faults B C 3 V M9 M M2 M3 M4 C OUT V Metal Poly Contact N N3 3 A C M N+ N B A M23 M24 M25 M26 M27 M28 GN P N2 N3 GN B C 3 6

7 Reasons for IC Malfunction - efects and Faults B A M M9 M N M3 N3 M2 M4 V C OUT N3 C M25 M24 M23 N2 M26 N4 M27 M28 GN 7

8 Reasons for IC Malfunction - efects and Faults B C 3 V V N M9 M Metal M9 M2 M4 Poly N3 M3 C OUT Contact 3 A C M N+ N B A M25 M27 M28 P N2 N3 GN M23 M24 M26 GN B C 3 8

9 Reasons for IC Malfunction - efects and Faults C out B A C M M9 M M2 M4 M25 M24 M23 M3 M26 M27 M28 V C OUT GN GN A B C efect no N - N3 short yes 9

10 Outline efects and Faults Reasons for IC malfunctioning Fault Modeling Types of faults (Stuck-At, bridge, Stuck Open) Automatic Test Pattern Generation Path elay Fault esign for Testability

11 Test Complexity In n Combinational Logic Out Exhaustive test 2 n + m Q Q Q Q clock Circuit with n = 25 and m = 5 µsec/test Exhaustive test time is over billion years! (Registers make life harder!) Registers m

12 Testing Strategies Functional Test: (go/no go) oes the part work? o this fast & cheap iagnostic Test: What in the chip is broken? Parametric Test: What is: max clock frequency min supply voltage max operating temp 2

13 Test Implementation Runs Test Vectors/Programs on evice Under Test (UT) Goal: Find a SMALL set of test vectors that has a BIG fault coverage Testers Clock rate in the range of GHz Resolutions measured in psec Large very fast memory Cost - 5 million dollars 3

14 Fault Models Modeling physical faults is complex Need models that simplify the behavior of faults a b c d f g h x e 4

15 Stuck-At Fault Stuck-at- a b c d f g h S-A- x e Stuck-at- a b c d f g h S-A- x e 5

16 Bridge & Stuck Open a b c d e f g h x Bridging fault a b c d e f g h x Open fault 6

17 Automatic Test Pattern Generation (ATPG) Given a logic circuit: Generate test program to cover all SA faults The -Algorithm The -Calculus Problem: Reconvergent Fanouts 7

18 -Algorithm Step : Choose a fault to insert Select from a fault dictionary Step 2: Activate (excite) the fault rive the faulty node to the opposite value of the fault Example: for SA-, drive the node to Step 3: Sensitize a path to an output Propagate the fault so that it can be observed at the output pin 8

19 Path Sensitization Goals: etermine input pattern that makes a fault controllable (triggers the fault, and makes its impact visible at the output nodes) Fault enabling Fault propagation sa Out Techniques Used: -algorithm, Podem 9

20 -Algorithm a b c d f g h x = / a b c d e f g h S-A- x value in good ckt = / value in faulty ckt e 2

21 2 -Algorithm A =NOT(A) B A = AB Five value logic simulation

22 -Algorithm Five value logic simulation A B = A + B 22

23 -Algorithm / = a b c d e f g h S-A- x 23

24 -Algorithm / = a b c d f g h x Conflict! Need backtracks Reconvergent Fanout x 24

25 Fault Simulation Test Program Random Number Generator, Genetic Algorithm, etc. Fault Free Circuit Circuit w/ One Fault Compare 25

26 Path elay Fault A defect can affect the speed of a path in the circuit Let s see a Path elay Fault example T a b slow slow c d e slow T+ T 26

27 Path elay Fault Path c-g2-g4-g5-x a b c d e g g2 g3 g4 g5 x 27

28 Outline efects and Faults Reasons for IC malfunctioning Fault Modeling Types of faults (Stuck-At, bridge, Stuck Open) Automatic Test Pattern Generation Path elay Fault esign for Testability 28

29 Scan-based Test ScanIn Modified to support two operation modes ScanOut In Register Combinational Logic A Register Combinational Logic B Out 29

30 Scan Based Methods Logic Logic Logic R R R R Level Sensitive Scan esign (LSS) - IBM Test Mode: OFF Test Mode: ON R L R L R R R 3

31 Boundary Scan (JTAG: IEEE 49.b) Printed-circuit board Logic Packaged IC Scan-in Scan-out si so scan path normal interconnect Bonding Pad Board testing becomes as problematic as chip testing 3

32 Built-In Self-Testing (BIST) (Sub)-Circuit Stimulus Generator Under Test Response Analyzer Test Controller Rapidly becoming more important with increasing chip-complexity and larger modules 32

33 Linear-Feedback Shift Register (LFSR) R R R S S S 2 Pseudo-Random Pattern Generator 33

Digital Integrated Circuits

Digital Integrated Circuits Digital Integrated Circuits Lecture Jaeyong Chung System-on-Chips (SoC) Laboratory Incheon National University Design/manufacture Process Chung EPC655 2 Design/manufacture Process Chung EPC655 3 Layout

More information

Very Large Scale Integration (VLSI)

Very Large Scale Integration (VLSI) Very Large Scale Integration (VLSI) Lecture 10 Dr. Ahmed H. Madian Ah_madian@hotmail.com Dr. Ahmed H. Madian-VLSI 1 Content Manufacturing Defects Wafer defects Chip defects Board defects system defects

More information

CMOS Testing: Part 1. Outline

CMOS Testing: Part 1. Outline CMOS Testing: Part 1 Introduction Fault models Stuck-line (single and multiple) Bridging Stuck-open Test pattern generation Combinational circuit test generation Sequential circuit test generation ECE

More information

Advanced Digital Logic Design EECS 303

Advanced Digital Logic Design EECS 303 Advanced igital Logic esign EECS 33 http://ziyang.eecs.northwestern.edu/eecs33/ Teacher: Robert ick Office: L477 Tech Email: dickrp@northwestern.edu Phone: 847 467 2298 Outline. 2. 2 Robert ick Advanced

More information

UNIT IV CMOS TESTING

UNIT IV CMOS TESTING UNIT IV CMOS TESTING 1. Mention the levels at which testing of a chip can be done? At the wafer level At the packaged-chip level At the board level At the system level In the field 2. What is meant by

More information

CHAPTER 1 INTRODUCTION

CHAPTER 1 INTRODUCTION CHAPTER 1 INTRODUCTION Rapid advances in integrated circuit technology have made it possible to fabricate digital circuits with large number of devices on a single chip. The advantages of integrated circuits

More information

VLSI Test Technology and Reliability (ET4076)

VLSI Test Technology and Reliability (ET4076) VLSI Test Technology and Reliability (ET4076) Lecture 8(2) I DDQ Current Testing (Chapter 13) Said Hamdioui Computer Engineering Lab Delft University of Technology 2009-2010 1 Learning aims Describe the

More information

Contents 1 Basic of Test and Role of HDLs 2 Verilog HDL for Design and Test

Contents 1 Basic of Test and Role of HDLs 2 Verilog HDL for Design and Test 1 Basic of Test and Role of HDLs... 1.1 Design and Test... 1.1.1 RTL Design Process... 1.1.2 Postmanufacturing Test... 1.2 Test Concerns... 1.2.1 Test Methods... 1.2.2 Testability Methods... 1.2.3 Testing

More information

VLSI Test Technology and Reliability (ET4076)

VLSI Test Technology and Reliability (ET4076) VLSI Test Technology and Reliability (ET4076) Lecture 8 (1) Delay Test (Chapter 12) Said Hamdioui Computer Engineering Lab Delft University of Technology 2009-2010 1 Learning aims Define a path delay fault

More information

VLSI Test Technology and Reliability (ET4076)

VLSI Test Technology and Reliability (ET4076) VLSI Test Technology and Reliability (ET4076) Lecture 2 (p2) Fault Modeling (Chapter 4) Said Hamdioui Computer Engineering Lab Delft University of Technology 2009-2010 1 Previous lecture What are the different

More information

VLSI Test Technology and Reliability (ET4076)

VLSI Test Technology and Reliability (ET4076) VLSI Test Technology and Reliability (ET476) Lecture 5 Combinational Circuit Test Generation (Chapter 7) Said Hamdioui Computer Engineering Lab elft University of Technology 29-2 Learning aims of today

More information

Preizkušanje elektronskih vezij

Preizkušanje elektronskih vezij Laboratorij za načrtovanje integriranih vezij Univerza v Ljubljani Fakulteta za elektrotehniko Preizkušanje elektronskih vezij Generacija testnih vzorcev Test pattern generation Overview Introduction Theoretical

More information

Overview ECE 753: FAULT-TOLERANT COMPUTING 1/23/2014. Recap. Introduction. Introduction (contd.) Introduction (contd.)

Overview ECE 753: FAULT-TOLERANT COMPUTING 1/23/2014. Recap. Introduction. Introduction (contd.) Introduction (contd.) ECE 753: FAULT-TOLERANT COMPUTING Kewal K.Saluja Department of Electrical and Computer Engineering Test Generation and Fault Simulation Lectures Set 3 Overview Introduction Basics of testing Complexity

More information

Design and Synthesis for Test

Design and Synthesis for Test TDTS 80 Lecture 6 Design and Synthesis for Test Zebo Peng Embedded Systems Laboratory IDA, Linköping University Testing and its Current Practice To meet user s quality requirements. Testing aims at the

More information

INTERCONNECT TESTING WITH BOUNDARY SCAN

INTERCONNECT TESTING WITH BOUNDARY SCAN INTERCONNECT TESTING WITH BOUNDARY SCAN Paul Wagner Honeywell, Inc. Solid State Electronics Division 12001 State Highway 55 Plymouth, Minnesota 55441 Abstract Boundary scan is a structured design technique

More information

Testing And Testable Design of Digital Systems

Testing And Testable Design of Digital Systems بسم الله الرحمان الرحیم Testing And Testable Design of Digital Systems College of Electrical Engineering Iran University of Science and Technology Karim Mohammadi Faut-Tolerant Digital System Design week-1

More information

ECE 156B Fault Model and Fault Simulation

ECE 156B Fault Model and Fault Simulation ECE 156B Fault Model and Fault Simulation Lecture 6 ECE 156B 1 What is a fault A fault is a hypothesis of what may go wrong in the manufacturing process In fact, a fault model is not trying to model the

More information

Chapter 7. Logic Diagnosis. VLSI EE141 Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 1

Chapter 7. Logic Diagnosis. VLSI EE141 Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 1 Chapter 7 Logic Diagnosis VLSI EE4 Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. Outline Introduction Combinational Logic Diagnosis Scan Chain Diagnosis Logic BIST Diagnosis Conclusion

More information

Automated TestVector Generation. Issues in Test Vector Generation. BIST Approach. Built-In Self Test (BIST) LFSR (cont)

Automated TestVector Generation. Issues in Test Vector Generation. BIST Approach. Built-In Self Test (BIST) LFSR (cont) The oncept of a Fault Testing centers around detection of faults in a circuit. The digital world is made up of interconnected gates Thus, only two things can fail - gates and their interconnections faulty

More information

A Built-in Self-Test for System-on-Chip

A Built-in Self-Test for System-on-Chip A Built-in Self-Test for System-on-Chip Rashid Rashidzadeh University of Windsor Digital 1 Objective : Design an intellectual property (IP) core which enables low speed Automatic Test Equipment (ATE) to

More information

Department of Electrical and Computer Engineering University of Wisconsin Madison. Fall Midterm Examination CLOSED BOOK

Department of Electrical and Computer Engineering University of Wisconsin Madison. Fall Midterm Examination CLOSED BOOK Department of Electrical and Computer Engineering University of Wisconsin Madison ECE 553: Testing and Testable Design of Digital Systems Fall 2013-2014 Midterm Examination CLOSED BOOK Kewal K. Saluja

More information

Computers: Inside and Out

Computers: Inside and Out Computers: Inside and Out Computer Components To store binary information the most basic components of a computer must exist in two states State # 1 = 1 State # 2 = 0 1 Transistors Computers use transistors

More information

VLSI System Testing. Lecture 1 Introduction Class website: people.ee.duke.edu/~krish/teaching/538.html

VLSI System Testing. Lecture 1 Introduction Class website: people.ee.duke.edu/~krish/teaching/538.html ECE 538 VLSI System Testing Krish Chakrabarty Lecture 1: Overview Krish Chakrabarty 1 Lecture 1 Introduction Class website: people.ee.duke.edu/~krish/teaching/538.html VLSI realization process Verification

More information

COEN-4730 Computer Architecture Lecture 12. Testing and Design for Testability (focus: processors)

COEN-4730 Computer Architecture Lecture 12. Testing and Design for Testability (focus: processors) 1 COEN-4730 Computer Architecture Lecture 12 Testing and Design for Testability (focus: processors) Cristinel Ababei Dept. of Electrical and Computer Engineering Marquette University 1 Outline Testing

More information

l Some materials from various sources! n Current course textbook! Soma 1! Soma 3!

l Some materials from various sources! n Current course textbook! Soma 1! Soma 3! Ackwledgements! Test generation algorithms! Mani Soma! l Some materials from various sources! n r. Phil Nigh, IBM! n Principles of Testing Electronic Systems by S. Mourad & Y. Zorian! n Essentials of Electronic

More information

CPE 628 Chapter 4 Test Generation. Dr. Rhonda Kay Gaede UAH. CPE Introduction Conceptual View. UAH Chapter 4

CPE 628 Chapter 4 Test Generation. Dr. Rhonda Kay Gaede UAH. CPE Introduction Conceptual View. UAH Chapter 4 Chapter 4 Test Generation Dr. Rhonda Kay Gaede UAH 1 4.1 Introduction Conceptual View Generate an input vector that can the - circuit from the one Page 2 1 4.1 Introduction Simple Illustration Consider

More information

ENG04057 Teste de Sistema Integrados. Prof. Eric Ericson Fabris (Marcelo Lubaszewski)

ENG04057 Teste de Sistema Integrados. Prof. Eric Ericson Fabris (Marcelo Lubaszewski) ENG04057 Teste de Sistema Integrados Prof. Eric Ericson Fabris (Marcelo Lubaszewski) Março 2011 Slides adapted from ABRAMOVICI, M.; BREUER, M.; FRIEDMAN, A. Digital Systems Testing and Testable Design.

More information

Verification and Testing

Verification and Testing Verification and Testing He s dead Jim... L15 Testing 1 Verification versus Manufacturing Test Design verification determines whether your design correctly implements a specification and hopefully that

More information

Testing Principle Verification Testing

Testing Principle Verification Testing ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTES Test Process and Test Equipment Overview Objective Types of testing Verification testing Characterization testing Manufacturing testing Acceptance

More information

Embedded Quality for Test. Yervant Zorian LogicVision, Inc.

Embedded Quality for Test. Yervant Zorian LogicVision, Inc. Embedded Quality for Test Yervant Zorian LogicVision, Inc. Electronics Industry Achieved Successful Penetration in Diverse Domains Electronics Industry (cont( cont) Met User Quality Requirements satisfying

More information

Digital VLSI Testing Prof. Santanu Chattopadhyay Department of Electronics and EC Engineering India Institute of Technology, Kharagpur.

Digital VLSI Testing Prof. Santanu Chattopadhyay Department of Electronics and EC Engineering India Institute of Technology, Kharagpur. Digital VLSI Testing Prof. Santanu Chattopadhyay Department of Electronics and EC Engineering India Institute of Technology, Kharagpur Lecture 05 DFT Next we will look into the topic design for testability,

More information

Fault-Tolerant Computing

Fault-Tolerant Computing Fault-Tolerant Computing Dealing with Low-Level Impairments Slide 1 About This Presentation This presentation has been prepared for the graduate course ECE 257A (Fault-Tolerant Computing) by Behrooz Parhami,

More information

EECS 579: Built-in Self-Test 3. Regular Circuits

EECS 579: Built-in Self-Test 3. Regular Circuits EECS 579: Built-in Self-Test 3 Outline Implementing BIST by regularization Adder ALU RAM Commercial BIST approaches LOCSD STUMPS CSTP Case Study Bosch AE11 microcontroller John P. Hayes University of Michigan

More information

Circuit Partitioning for Application-Dependent FPGA Testing

Circuit Partitioning for Application-Dependent FPGA Testing Circuit Partitioning for Application-Dependent FPGA Testing by Rui Zhen Feng B.Eng, Hefei University of Technology, 1996 A Thesis Submitted in Partial Fulfillment of the Requirements for the Degree of

More information

Fault Tolerant Computing CS 530 Testing Sequential Circuits

Fault Tolerant Computing CS 530 Testing Sequential Circuits CS 530 Testing Sequential Circuits Yashwant K. Malaiya Colorado State University 1 Why Testing Sequential Circuits is Hard To test a sequential circuit we need to Initialize it into a known state (reset

More information

EE434 ASIC & Digital Systems Testing

EE434 ASIC & Digital Systems Testing EE434 ASIC & Digital Systems Testing Spring 2015 Dae Hyun Kim daehyun@eecs.wsu.edu 1 Introduction VLSI realization process Verification and test Ideal and real tests Costs of testing Roles of testing A

More information

Design for Test of Digital Systems TDDC33

Design for Test of Digital Systems TDDC33 Course Outline Design for Test of Digital Systems TDDC33 Erik Larsson Department of Computer Science Introduction; Manufacturing, Wafer sort, Final test, Board and System Test, Defects, and Faults Test

More information

Impact of DFT Techniques on Wafer Probe

Impact of DFT Techniques on Wafer Probe Impact of DFT Techniques on Wafer Probe Ron Leckie, CEO, INFRASTRUCTURE ron@infras.com Co-author: Charlie McDonald, LogicVision charlie@lvision.com The Embedded Test Company TM Agenda INFRASTRUCTURE Introduction

More information

The Embedded computing platform. Four-cycle handshake. Bus protocol. Typical bus signals. Four-cycle example. CPU bus.

The Embedded computing platform. Four-cycle handshake. Bus protocol. Typical bus signals. Four-cycle example. CPU bus. The Embedded computing platform CPU bus. Memory. I/O devices. CPU bus Connects CPU to: memory; devices. Protocol controls communication between entities. Bus protocol Determines who gets to use the bus

More information

Boundary Scan. Sungho Kang. Yonsei University

Boundary Scan. Sungho Kang. Yonsei University Boundary Scan Sungho Kang Yonsei University Outiline Introduction TAP Controller Instruction Register Test Data Registers Instructions Hardware Test Innovations PCB Test Conclusion 2 Boundary Scan Improve

More information

Lecture 2 VLSI Testing Process and Equipment

Lecture 2 VLSI Testing Process and Equipment Lecture 2 VLSI Testing Process and Equipment Motivation Types of Testing Test Specifications and Plan Test Programming Test Data Analysis Automatic Test Equipment Parametric Testing Summary VLSI Test:

More information

SSoCC'01 4/3/01. Specific BIST Architectures. Gert Jervan Embedded Systems Laboratory (ESLAB) Linköping University

SSoCC'01 4/3/01. Specific BIST Architectures. Gert Jervan Embedded Systems Laboratory (ESLAB) Linköping University Specific BIST Architectures Gert Jervan Embedded Systems Laboratory (ESLAB) Linköping University General Concepts Test-per-scan architectures Multiple scan chains Test-per-clock architectures BIST conclusions

More information

A Study on the Testing of VLSI Systems Using Reduced Power Consumption Methods

A Study on the Testing of VLSI Systems Using Reduced Power Consumption Methods International Journal of Scientific & Engineering Research, Volume 4, Issue 4, April-2013 664 A Study on the Testing of VLSI Systems Using Reduced Power Consumption Methods Debasmita Hazra Abstract- This

More information

VLSI Test Technology and Reliability (ET4076)

VLSI Test Technology and Reliability (ET4076) VLSI Test Technology and Reliability (ET4076) Lecture 4(part 2) Testability Measurements (Chapter 6) Said Hamdioui Computer Engineering Lab Delft University of Technology 2009-2010 1 Previous lecture What

More information

A Research Paper on Designing a TAP(Test Access Port)

A Research Paper on Designing a TAP(Test Access Port) A Research Paper on Designing a TAP(Test Access Port) 1 Mr. VISHWAS K. CHAUDHARY, 2 Mr. MANISH J. PATEL 1, 2 P. G. Students in M.E.(VLSI & ESD) Gujarat Technological University & Seer-Akademi Ahmedabad,

More information

Chapter 9. Design for Testability

Chapter 9. Design for Testability Chapter 9 Design for Testability Testability CUT = Circuit Under Test A design property that allows: cost-effective development of tests to be applied to the CUT determining the status of the CUT (normal

More information

Faults, Testing & Test Generation

Faults, Testing & Test Generation Faults, Testing & Test Generation Smith Text: Chapter 14.1,14.3, 14.4 Mentor Graphics/Tessent: Scan and ATPG Process Guide ATPG and Failure Diagnosis Tools Reference Manual (access via mgcdocs ) ASIC Design

More information

Mixed-Signals Integrated Circuit Testing

Mixed-Signals Integrated Circuit Testing Mixed-Signals Integrated Circuit Testing Salvador MIR TIMA Laboratory 46 Av. Félix Viallet 38031 Grenoble salvador.mir@imag.fr Montpellier, 27 th March 2007 1 Outline 1 2 3 4 5 6 Introduction Analog versus

More information

l Some materials from various sources! Soma 1! l Apply a signal, measure output, compare l 32-bit adder test example:!

l Some materials from various sources! Soma 1! l Apply a signal, measure output, compare l 32-bit adder test example:! Acknowledgements! Introduction and Overview! Mani Soma! l Some materials from various sources! n Dr. Phil Nigh, IBM! n Principles of Testing Electronic Systems by S. Mourad and Y. Zorian! n Essentials

More information

Mentor Graphics Tools for DFT. DFTAdvisor, FastScan and FlexTest

Mentor Graphics Tools for DFT. DFTAdvisor, FastScan and FlexTest Mentor Graphics Tools for DFT DFTAdvisor, FastScan and FlexTest 1 DFT Advisor Synthesis tool capable of doing DRC, Scan Insertion and Test point Synthesis Creates a do file and a test procedure file after

More information

Digital Design Methodology (Revisited) Design Methodology: Big Picture

Digital Design Methodology (Revisited) Design Methodology: Big Picture Digital Design Methodology (Revisited) Design Methodology Design Specification Verification Synthesis Technology Options Full Custom VLSI Standard Cell ASIC FPGA CS 150 Fall 2005 - Lec #25 Design Methodology

More information

About the Instructor

About the Instructor About the Instructor Kwang-Ting (Tim) Cheng PhD, 1988, Univ. of California, Berkeley 1988-1993: AT&T Bell Labs 1993-Present: Professor, Dept. of ECE, Univ. of California, Santa Barbara 1999-2002: Director,

More information

Built-In Self-Test for Programmable I/O Buffers in FPGAs and SoCs

Built-In Self-Test for Programmable I/O Buffers in FPGAs and SoCs Built-In Self-Test for Programmable I/O Buffers in FPGAs and SoCs Sudheer Vemula, Student Member, IEEE, and Charles Stroud, Fellow, IEEE Abstract The first Built-In Self-Test (BIST) approach for the programmable

More information

TESTING AND TESTABLE DESIGN OF DIGITAL SYSTES

TESTING AND TESTABLE DESIGN OF DIGITAL SYSTES TESTING AND TESTABLE DESIGN OF DIGITAL SYSTES Kewal K. Saluja University of Wisconsin - Madison Motivation, Fault Models and some Callenges Overview Motivation Technology, Test cost, and VLSI realization

More information

Testable SOC Design. Sungho Kang

Testable SOC Design. Sungho Kang Testable SOC Design Sungho Kang 2001.10.5 Outline Introduction SOC Test Challenges IEEE P1500 SOC Test Strategies Conclusion 2 SOC Design Evolution Emergence of very large transistor counts on a single

More information

VLSI System Testing. Fault Simulation

VLSI System Testing. Fault Simulation ECE 538 VLSI System Testing Krish Chakrabarty Fault Simulation ECE 538 Krish Chakrabarty Fault Simulation Problem and motivation Fault simulation algorithms Serial Parallel Deductive Concurrent Random

More information

Y. Tsiatouhas. VLSI Systems and Computer Architecture Lab

Y. Tsiatouhas. VLSI Systems and Computer Architecture Lab CMOS INTEGRATED CIRCUIT DESIGN TECHNIQUES University of Ioannina VLSI Testing Dept. of Computer Science and Engineering Y. Tsiatouhas CMOS Integrated Circuit Design Techniques Overview 1. VLSI testing

More information

High Quality, Low Cost Test

High Quality, Low Cost Test Datasheet High Quality, Low Cost Test Overview is a comprehensive synthesis-based test solution for compression and advanced design-for-test that addresses the cost challenges of testing complex designs.

More information

Nanometer technologies enable higher-frequency designs

Nanometer technologies enable higher-frequency designs By Ron Press & Jeff Boyer Easily Implement PLL Clock Switching for At-Speed Test By taking advantage of pattern-generation features, a simple logic design can utilize phase-locked-loop clocks for accurate

More information

DFT-3D: What it means to Design For 3DIC Test? Sanjiv Taneja Vice President, R&D Silicon Realization Group

DFT-3D: What it means to Design For 3DIC Test? Sanjiv Taneja Vice President, R&D Silicon Realization Group I N V E N T I V E DFT-3D: What it means to Design For 3DIC Test? Sanjiv Taneja Vice President, R&D Silicon Realization Group Moore s Law & More : Tall And Thin More than Moore: Diversification Moore s

More information

Outline. Definition. Targeted Defects. Motivation GOAL. Ferhani, RATS/SPRING , Center for Reliable Computing 1

Outline. Definition. Targeted Defects. Motivation GOAL. Ferhani, RATS/SPRING , Center for Reliable Computing 1 RATS (Reliability and Testability Seminar) Diagnosis of Defects Introducing Voltage Dependences between Nodes By François-Fabien Ferhani 5/27/2003 Ferhani, RATS/SPRING03 Outline Introduction Problems &

More information

ECE520 VLSI Design. Lecture 1: Introduction to VLSI Technology. Payman Zarkesh-Ha

ECE520 VLSI Design. Lecture 1: Introduction to VLSI Technology. Payman Zarkesh-Ha ECE520 VLSI Design Lecture 1: Introduction to VLSI Technology Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1 Course Objectives

More information

At-Speed Scan Test with Low Switching Activity

At-Speed Scan Test with Low Switching Activity 21 28th IEEE VLSI Test Symposium At-Speed Scan Test with Low Switching Activity Elham K. Moghaddam Department of ECE, University of Iowa, Iowa City, IA 52242 ekhayatm@engineering.uiowa.edu Janusz Rajski

More information

Delay and Optimization of Random Number Generator

Delay and Optimization of Random Number Generator International Journal of Scientific and Research Publications, Volume 2, Issue 3, March 2012 1 Delay and Optimization of Random Number Generator Atul Kumar Dewangan 1, Nibedita Chakraborty 2, Smriti Dewangan

More information

Net Diagnosis Using Stuck-at and Transition Fault Models. Lixing Zhao

Net Diagnosis Using Stuck-at and Transition Fault Models. Lixing Zhao Net Diagnosis Using Stuck-at and Transition Fault Models by Lixing Zhao A thesis submitted to the Graduate Faculty of Auburn University in partial fulfillment of the requirements for the Degree of Master

More information

Metodologie di progetto HW Il test di circuiti digitali

Metodologie di progetto HW Il test di circuiti digitali Metodologie di progetto HW Il test di circuiti digitali Introduzione Versione del 9/4/8 Metodologie di progetto HW Il test di circuiti digitali Introduction VLSI Realization Process Customer s need Determine

More information

Metodologie di progetto HW Il test di circuiti digitali

Metodologie di progetto HW Il test di circuiti digitali Metodologie di progetto HW Il test di circuiti digitali Introduzione Versione del 9/4/8 Metodologie di progetto HW Il test di circuiti digitali Introduction Pag. 2 VLSI Realization Process Customer s need

More information

Digital VLSI Testing. Week 1 Assignment Solution

Digital VLSI Testing. Week 1 Assignment Solution Digital VLSI Testing Week 1 Assignment Solution Q1. Primary objective of testing is to guarantee (A) Fault-free products (B) Detection of design error (C) Reduction of product cost (D) All of these Ans:

More information

Digital System Test and Testable Design

Digital System Test and Testable Design Digital System Test and Testable Design wwwwwwwwwwww Zainalabedin Navabi Digital System Test and Testable Design Using HDL Models and Architectures Zainalabedin Navabi Worcester Polytechnic Institute Department

More information

Digital Design Methodology

Digital Design Methodology Digital Design Methodology Prof. Soo-Ik Chae Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 1-1 Digital Design Methodology (Added) Design Methodology Design Specification

More information

Faults. Abstract. 1. Introduction. * Nur A. Touba is now with the Department of Electrical and Computer Engineering, University of Texas, Austin, TX

Faults. Abstract. 1. Introduction. * Nur A. Touba is now with the Department of Electrical and Computer Engineering, University of Texas, Austin, TX s Abstract While previous research has focused on deterministic testing of bridging faults, this paper studies pseudo-random testing of bridging faults and describes a means for achieving high fault coverage

More information

IC Testing and Development in Semiconductor Area

IC Testing and Development in Semiconductor Area IC Testing and Development in Semiconductor Area Prepare by Lee Zhang, 2004 Outline 1. Electronic Industry Development 2. Semiconductor Industry Development 4Electronic Industry Development Electronic

More information

Atmel AT94K FPSLIC Architecture Field Programmable Gate Array

Atmel AT94K FPSLIC Architecture Field Programmable Gate Array Embedded Processor Based Built-In Self-Test and Diagnosis of FPGA Core in FPSLIC John Sunwoo (Logic BIST) Srinivas Garimella (RAM BIST) Sudheer Vemula (I/O Cell BIST) Chuck Stroud (Routing BIST) Jonathan

More information

ESE532: System-on-a-Chip Architecture. Today. Wafer Cost. Message. Preclass 1. Implication. Chip Costs from Area Chip Area

ESE532: System-on-a-Chip Architecture. Today. Wafer Cost. Message. Preclass 1. Implication. Chip Costs from Area Chip Area ESE532: System-on-a-Chip Architecture Day 23: November 19, 2018 Estimating Chip Area and Costs Today Chip Costs from Area Chip Area IO Interconnect Rent s Rule Infrastructure Some Areas CACTI for modeling

More information

DESIGN OF RANDOM NUMBER GENERATOR AND ITS DELAY AND POWER OPTIMIZATION A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF

DESIGN OF RANDOM NUMBER GENERATOR AND ITS DELAY AND POWER OPTIMIZATION A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DESIGN OF RANDOM NUMBER GENERATOR AND ITS DELAY AND POWER OPTIMIZATION A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF Bachelor of Technology in Electronics and Communication

More information

SAT-BASED ATPG FOR DIGITAL INTEGRATED CIRCUITS BASED ON MULTIPLE OBSERVATIONS

SAT-BASED ATPG FOR DIGITAL INTEGRATED CIRCUITS BASED ON MULTIPLE OBSERVATIONS SAT-BASED ATPG FOR DIGITAL INTEGRATED CIRCUITS BASED ON MULTIPLE OBSERVATIONS SAT-BASED ATPG FOR DIGITAL INTEGRATED CIRCUITS BASED ON MULTIPLE OBSERVATIONS BY DAVID WING YIN LEUNG, B. ENG. & MGT. (COMPUTER)

More information

Page 1. Outline. A Good Reference and a Caveat. Testing. ECE 254 / CPS 225 Fault Tolerant and Testable Computing Systems. Testing and Design for Test

Page 1. Outline. A Good Reference and a Caveat. Testing. ECE 254 / CPS 225 Fault Tolerant and Testable Computing Systems. Testing and Design for Test Page Outline ECE 254 / CPS 225 Fault Tolerant and Testable Computing Systems Testing and Design for Test Copyright 24 Daniel J. Sorin Duke University Introduction and Terminology Test Generation for Single

More information

Test and Measurement Challenges for 3D IC Development. R. Robertazzi IBM Research

Test and Measurement Challenges for 3D IC Development. R. Robertazzi IBM Research Test and Measurement Challenges for 3D IC Development R. Robertazzi IBM Research PFA Bill Price. Pete Sorce. John Ott. David Abraham. Pavan Samudrala Digital Test Kevin Stawaisz. TEL P12 Prober Glen Lansman,

More information

BA-BIST: Board Test from Inside the IC Out

BA-BIST: Board Test from Inside the IC Out BA-BIST: Board Test from Inside the IC Out Zoë Conroy, Cisco Al Crouch, Asset InterTech inemi BIST Project 1 05/18/2013 About this Presentation Board-Assist (BA-BIST) is enhanced IC BIST functionality

More information

Transition Faults and Transition Path Delay Faults: Test Generation, Path Selection, and Built-In Generation of Functional Broadside Tests

Transition Faults and Transition Path Delay Faults: Test Generation, Path Selection, and Built-In Generation of Functional Broadside Tests Purdue University Purdue e-pubs Open Access Dissertations Theses and Dissertations Fall 2013 Transition Faults and Transition Path Delay Faults: Test Generation, Path Selection, and Built-In Generation

More information

Testing Digital Systems I

Testing Digital Systems I Testing Digital Systems I Lecture 1: Introduction Instructor: M. Tahoori Copyright 2011, M. Tahoori TDS I: Lecture 1 1 Today s Lecture Logistics Course Outline Introduction Copyright 2011, M. Tahoori TDS

More information

Overview ECE 753: FAULT-TOLERANT COMPUTING 1/21/2014. Recap. Fault Modeling. Fault Modeling (contd.) Fault Modeling (contd.)

Overview ECE 753: FAULT-TOLERANT COMPUTING 1/21/2014. Recap. Fault Modeling. Fault Modeling (contd.) Fault Modeling (contd.) ECE 753: FAULT-TOLERANT COMPUTING Kewal K.Saluja Department of Electrical and Computer Engineering Fault Modeling Lectures Set 2 Overview Fault Modeling References Fault models at different levels (HW)

More information

At-Speed On-Chip Diagnosis of Board-Level Interconnect Faults

At-Speed On-Chip Diagnosis of Board-Level Interconnect Faults At-Speed On-Chip Diagnosis of Board-Level Interconnect Faults Artur Jutman Tallinn University of Technology artur@pld.ttu.ee Abstract This article describes a novel approach to fault diagnosis suitable

More information

Evaluation of FPGA Resources for Built-In Self-Test of Programmable Logic Blocks

Evaluation of FPGA Resources for Built-In Self-Test of Programmable Logic Blocks Evaluation of FPGA Resources for Built-In Self-Test of Programmable Logic Blocks Charles Stroud, Ping Chen, Srinivasa Konala, Dept. of Electrical Engineering University of Kentucky and Miron Abramovici

More information

ADVANCED DIGITAL IC DESIGN. Digital Verification Basic Concepts

ADVANCED DIGITAL IC DESIGN. Digital Verification Basic Concepts 1 ADVANCED DIGITAL IC DESIGN (SESSION 6) Digital Verification Basic Concepts Need for Verification 2 Exponential increase in the complexity of ASIC implies need for sophisticated verification methods to

More information

UMBC. space and introduced backtrace. Fujiwara s FAN efficiently constrained the backtrace to speed up search and further limited the search space.

UMBC. space and introduced backtrace. Fujiwara s FAN efficiently constrained the backtrace to speed up search and further limited the search space. ATPG Algorithms Characteristics of the three main algorithms: Roth s -Algorithm (-ALG) defined the calculus and algorithms for ATPG using -cubes. Goel s POEM used path propagation constraints to limit

More information

! Design Methodologies. " Hierarchy, Modularity, Regularity, Locality. ! Implementation Methodologies. " Custom, Semi-Custom (cell-based, array-based)

! Design Methodologies.  Hierarchy, Modularity, Regularity, Locality. ! Implementation Methodologies.  Custom, Semi-Custom (cell-based, array-based) ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 23: April 12, 2016 VLSI Design and Variation Lecture Outline Design Methodologies Hierarchy, Modularity, Regularity, Locality Implementation

More information

Semiconductor IC Test and Design-for-Test Fundamentals

Semiconductor IC Test and Design-for-Test Fundamentals Semiconductor IC Test and Design-for-Test Fundamentals By Al Crouch, Chief Scientist, Inovys Corporation The Semiconductor Industry seeks to reduce the cost of manufacturing its product by continuously

More information

The Boundary - Scan Handbook

The Boundary - Scan Handbook The Boundary - Scan Handbook By Kenneth P. Parker Agilent Technologies * KLUWER ACADEMIC PUBLISHERS Boston / Dordrecht / London TABLE OF CONTENTS List of Figures xiii List of Tables xvi List of Design-for-Test

More information

VLSI System Testing. Introduction

VLSI System Testing. Introduction ECE 538 VLSI System Testing Krish Chakraarty Test Generation: Part ECE 538 Krish Chakraarty Introduction Classification of test generation methods Fault tale analysis Boolean difference method Propagation,

More information

Lecture 28 IEEE JTAG Boundary Scan Standard

Lecture 28 IEEE JTAG Boundary Scan Standard Lecture 28 IEEE 49. JTAG Boundary Scan Standard Motivation Bed-of-nails tester System view of boundary scan hardware Elementary scan cell Test Access Port (TAP) controller Boundary scan instructions Summary

More information

Compaction mechanism to reduce test pattern counts and segmented delay fault testing for path delay faults

Compaction mechanism to reduce test pattern counts and segmented delay fault testing for path delay faults University of Iowa Iowa Research Online Theses and Dissertations Spring 2013 Compaction mechanism to reduce test pattern counts and segmented delay fault testing for path delay faults Sharada Jha University

More information

Focus On Structural Test: AC Scan

Focus On Structural Test: AC Scan Focus On Structural Test: AC Scan Alfred L. Crouch Chief Scientist Inovys Corporation al.crouch@inovys.com The DFT Equation The Problem What is Driving Modern Test Technology? 300mm Wafers Volume Silicon/Test

More information

Testability Optimizations for A Time Multiplexed CPLD Implemented on Structured ASIC Technology

Testability Optimizations for A Time Multiplexed CPLD Implemented on Structured ASIC Technology ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY Volume 14, Number 4, 2011, 392 398 Testability Optimizations for A Time Multiplexed CPLD Implemented on Structured ASIC Technology Traian TULBURE

More information

Static Compaction Techniques to Control Scan Vector Power Dissipation

Static Compaction Techniques to Control Scan Vector Power Dissipation Static Compaction Techniques to Control Scan Vector Power Dissipation Ranganathan Sankaralingam, Rama Rao Oruganti, and Nur A. Touba Computer Engineering Research Center Department of Electrical and Computer

More information

P1149.1A Extensions to IEEE-STD

P1149.1A Extensions to IEEE-STD AN-890 Fairchild Semiconductor Application Note February 1994 Revised May 2001 P1149.1A Extensions to IEEE-STD-1149.1-1990 Abstract Since publication of IEEE-1149.1-1990/ANSI 1, 2, 3, extensions and requests

More information

CPE/EE 422/522. Introduction to Xilinx Virtex Field-Programmable Gate Arrays Devices. Dr. Rhonda Kay Gaede UAH. Outline

CPE/EE 422/522. Introduction to Xilinx Virtex Field-Programmable Gate Arrays Devices. Dr. Rhonda Kay Gaede UAH. Outline CPE/EE 422/522 Introduction to Xilinx Virtex Field-Programmable Gate Arrays Devices Dr. Rhonda Kay Gaede UAH Outline Introduction Field-Programmable Gate Arrays Virtex Virtex-E, Virtex-II, and Virtex-II

More information

AN OPTIMAL APPROACH FOR TESTING EMBEDDED MEMORIES IN SOCS

AN OPTIMAL APPROACH FOR TESTING EMBEDDED MEMORIES IN SOCS International Journal of Engineering Inventions ISSN: 2278-7461, www.ijeijournal.com Volume 1, Issue 8 (October2012) PP: 76-80 AN OPTIMAL APPROACH FOR TESTING EMBEDDED MEMORIES IN SOCS B.Prathap Reddy

More information

A Review paper on the Memory Built-In Self-Repair with Redundancy Logic

A Review paper on the Memory Built-In Self-Repair with Redundancy Logic International Journal of Engineering and Applied Sciences (IJEAS) A Review paper on the Memory Built-In Self-Repair with Redundancy Logic Er. Ashwin Tilak, Prof. Dr.Y.P.Singh Abstract The Present review

More information

ISSN (PRINT): , (ONLINE): , VOLUME-3, ISSUE-8,

ISSN (PRINT): , (ONLINE): , VOLUME-3, ISSUE-8, LOW POWER VLSI TESTING OVERVIEW Asha GH Associate Professor, Dept of E & C Engineering, Malnad College of Engineering. Hassan. India Email: ashaghmce@yahoo.com, gha@mcehassan.ac.in Abstract An unintended

More information