System Synthesis of Digital Systems
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1 System Synthesis Introduction 1 System Synthesis of Digital Systems Petru Eles, Zebo Peng System Synthesis Introduction 2 Literature: Introduction P. Eles, K. Kuchcinski and Z. Peng "System Synthesis with VHDL" Kluwer Academic Publisher, December Digital System Synthesis 2. Lecture Topics. Specification s and the Abstraction Hierarchy 4. The YChart 5. Synthesis Steps Examination: 6. High Level Synthesis Term paper Seminar presentation
2 System Synthesis Introduction System Synthesis Introduction 4 What s About? Why Is This an Issue? It s about (automatic) synthesis of digital systems. A digital system (for this course) Consists of programmable processors and dedicated hardware (application specific integrated circuits ASICs). Performs a welldefined task. In this course there will be more emphasis on the specification and synthesis of the hardware part (the ASIC). Complexity: new computer aided methodologies are needed in the context of increasing complexity (SoC). Verification: starting from a (formal) system specification which is validated, and performing well defined design steps (transformations) with verifiable outputs. Time to market: only efficient tools and reuse can bring design productivity up to the expected level.
3 System Synthesis Introduction 6 System Synthesis (cont d) System specification Simulation System Synthesis Introduction 5 Arch. Selection & Partitioning System Synthesis Partitioned model Hardw./Softw. Cosimulation Input: an implementation independent specification of the system; this includes: functionality and constraints. Scheduling The synthesis tasks: To select the architecture; To partition functionality over the components of the architecture; To schedule activities To generate behavioral modules corresponding to the hardware and software domain of the implementation, including interface modules. The behavioral modules resulted from the previous steps are further synthesised into the actual hardware and/or software implementation. Software model Part. model& Schedule Communication Synthesis Hardw./Softw. Cosimulation Hardw./Softw. Cosimulation Hardware model Software Generation Hardware Synthesis Software blocks Hardw./Softw. Cosimulation Hardware blocks Emulation& Prototyping Product Fabrication
4 System Synthesis Introduction 8 Lecture Topics and Schedule System Synthesis Introduction 7 Partitioning Simulation Verification System Synthesis (cont d) Hardware synthesis System specification Compilation Internal design representation Communic. synthesis Behavioral modules Software synthesis IMPLEMENTATION Architecture selection Estimation Scheduling Architecture model Component library (IP, COTS) 1. Introduction and Course Overview. System Synthesis and HighLevel Synthesis. Thursday March 2, VHDL Basics and Simulation Mechanism. Thursday April 6, HighLevel Synthesis. Thursday April 1, Basics of Transformational Approach. Thursday April 20, Optimization Heuristics for Synthesis. Thursday April 27, SystemLevel Synthesis and Hardware Software Partitioning I. Thursday May 11, SystemLevel Synthesis and Hardware Software Partitioning II. Thursday May 18, Synthesis of Advanced Features. Wednesday May 1, HighLevel Synthesis for Testability. Thursday June 8, Presentation of Term Papers. Thursday June 15, 10??.
5 System Synthesis Introduction 10 Digital Systems The Abstraction Hierarchy System Synthesis Introduction 9 Digital Systems Specification s Functional : emphasis is on behavior (input output functionality), without any reference to the particular way in which this behavior is implemented. System level: The specification is given as a set of subsystems (modules/processes) which are loosely interacting (e.g. by exchanging messages). The basic structural elements are processors, communication channels, ASICs, memories. Structural : the specification is in terms of hierarchy of interconnected functional components. Physical/Geometrical : the specification is in terms of physical placement in space and physical characteristics without any elements to functionality. Algorithmic level (behavioral level): The specification is given as an algorithm describing the functionality. repeat xl = x + dx; ul = u ( x u dx) ( y dx); yl = y + u dx; c = xl < a; x = xl; u = ul; y = yl; until (c); The basic structural elements are controller and netlist.
6 System Synthesis Introduction 11 The Abstraction Hierarchy (cont d) Registertransfer level: Operations described as transfer of values between registers and functional units. System Synthesis Introduction 12 a dx x y u r1 r2 validate control multiplex. The Abstraction Hierarchy (cont d) Logic level: Operations are described as boolean equations. The basic structural elements are gates and their interconnections. Circuit level: Differential equations define relations between signal voltage, current response, etc. The system is described in terms of transistors, resistors, capacitors. ALU control ALU c The basic structural elements are registers, ALUs, multiplexers and controller.
7 System Synthesis Introduction 14 YChart System Synthesis Introduction 1 Behavioral System level Algorithmic level Structural YChart A representation proposed by Gajski, in order to capture specification domains, abstraction levels and their interrelation. Specification domains are represented as the three axes; In each domain, the specification can be at different abstraction levels. These levels are represented as points on the respective axes. The Ychart also tries to capture the relation between different design activities (synthesis, analysis, refinement, etc.) System Spec. Algorithm Reg.Transf. Spec. Boolean Equ. Transistor functions RT level Logic level Circuit level CPU, Memory Controller, Netlist ALU, Reg., MUX Gate, Flipflop Transistor Transistor layouts StandardCell MacroCell Block/Chip Chip, Board, MCM Physical/Geometrical
8 System Synthesis Introduction 15 System Synthesis Introduction 16 YChart and Design Activities TopDown Synthesis in the Y_Chart Behavioral Synthesis Analysis Structural Behavioral 1 2 Structural System Spec. Algorithm CPU, Memory Controller, Netlist Refinement Optimization Reg.Transf. Spec. 4 ALU, Reg., MUX Abstraction Generation Boolean Equ. Transistor functions 5 Gate, Flipflop Transistor Extraction 1: System level synthesis 2: High level synthesis : RT level synthesis 4: Logic synthesis 5: Physical design Transistor layouts StandardCell MacroCell Physical/Geometrical Block/Chip Chip, Board, MCM Physical/Geometrical
9 System Synthesis Introduction 17 System Synthesis Introduction 18 Synthesis Steps Synthesis Steps (cont d) Synthesis: Transformation of a representation in the behavioral domain to a representation of the same design in the structural domain (at the same abstraction level). The structural description which results after a synthesis step is formulated as an interconnection of abstract components. Each such component is functionally specified at the following, lower abstraction level. These functional specifications are the input for the following synthesis step. System synthesis Input: System level specification (interacting processes) + design constraints Output: Behavioral elements to be synthesised to hardware and software + System architecture + Process schedule and mapping High level (behavioral) synthesis Input: Algorithmic description Output: RT level description of the controller (FSM) + netlist (data path)
10 System Synthesis Introduction 19 System Synthesis Introduction 20 Synthesis Steps (cont d) High Level Synthesis RT level synthesis Input: RT level description of the controller (FSM) + netlist Output: Blocks of combinational and memory elements Logic synthesis Input: Blocks of combinational and memory elements (as boolean functions) Output: gatelevel netlist Physical design Input: gatelevel netlist Output: geometrical layout for a given technology Behavioural description Compilation Design representation Scheduling Allocation Binding RT level implementation
11 System Synthesis Introduction 21 System Synthesis Introduction 22 From Algorithm to Design Representation u = u ( x u dx) ( y dx); x = x + dx; y = y + u dx; c = x < a; 0 Allocation and Binding Allocate: 4 multipliers and two ALUs. Bind as follows: 0 x udx ydx udx x+dx < 4 5 n n <
12 System Synthesis Introduction 2 System Synthesis Introduction 24 Scheduling Schedule the operations into clock cycles. Scheduling (cont d) A schedule of the same graph, considering one multiplier and one ALU. 0 TIME TIME TIME 2 2 < 11 TIME 2 TIME TIME n 9 < 11 TIME TIME 4 TIME 5 TIME We considered each operation to take one clock cycle. TIME n
13 System Synthesis Introduction 25 System Synthesis Introduction 26 The Netlist repeat xl = x + dx; ul = u ( x u dx) ( y dx); yl = y + u dx; c = xl < a; x = xl; u = ul; y = yl; until (c); The Controller Suppose the following schedule (1 multiplier, 1 ALU): 0 v 1 : x > r v 10 : x+dx > r1,x + ALU a dx x y u r1 r2 validate control multiplex. control ALU c v 2 : udx > r1 v 11 : r1<a > c v v 6 v 4 v 7 v 8 v 5 : r2r1 > r2 : dx > r2 : ur2 > r1 : r2y > r2 : udx > r2 : r1r2 > u < v 9 : y+r2 > y + 9 n
14 System Synthesis Introduction 27 The Controller (cont d) One state for each clock cycle In each state the signals are generated which are needed in order to execute the operations scheduled for that cycle (see schedule). clk, c clk, c s 7 9 clk s 1 1,10 s 2 2,11 clk s clk s 4 6,4 clk s 6 5,8 clk s 5 7 clk
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