Gate Level Minimization Map Method


 Marcia Turner
 2 years ago
 Views:
Transcription
1 Gate Level Minimization Map Method Complexity of hardware implementation is directly related to the complexity of the algebraic expression Truth table representation of a function is unique Algebraically there can be many different but equivalent forms Boolean expressions may be simplified by algebraic means Awkward because it lacks specific rules to predict each succeeding step in the manipulative process Map method is a simple, straightforward procedure for minimizing Boolean functions Karnaugh map or Kmap 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 1
2 Gate Level Minimization Map Method Map Method Kmap is a diagram made up of squares, with each square representing one minterm of the function that is to be minimized Presents a visual diagram of all possible ways a function may be expressed in standard form By recognizing various patterns one can derive alternative algebraic expressions from which the simplest can be selected The simplified expressions are always in one of the two standard forms: sum of products or product of sums Assume that simplest algebraic expression has the minimum number of terms with the smallest possible number of literals in each term Should generate a circuit with a minimum number of gates and the minimum number of inputs to each gate 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 2
3 TwoVariable KMapK There are four minterms for two variables Map (a) consists of four squares, one for each minterm Map (b) shows the relationship between the squares and the two variables x and y 0 and 1 marked in each row and column designate the values of variables x is primed in row 0 and unprimed in row 1 y is primed in column 0 and unprimed in column Roberto Muscedere Images 2013 Pearson Education Inc. 3
4 TwoVariable KMapK If we mark the squares whose minterms belong to a given function, the twovariable map represents any one of the 16 Boolean functions of two variables Function xy shown (a) xy = m 3 1 is placed inside m 3 minterm square Function x + y shown in (b) 1's placed in minterm squares m 1 + m 2 + m 3 = x'y + xy' + xy = x + y 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 4
5 ThreeVariable KMapK Eight minterms for three binary variables Minterms are arranged similar to the Gray code, that is only one bit changes in value from one adjacent column to the next Map in (b) is marked with numbers in each row and each column to show the relationship between the squares and the three variables ie. m 5 corresponds to row 1 and column 01 Get which is 5 10 when concatenated Any two adjacent squares in the map differ by only one variable, which is primed in one square and unprimed in the other Note m 0 & m 2, and m 4 & m 6 are adjacent 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 5
6 ThreeVariable KMap: K Ex. 1 Given: F(x, y, z) = (2, 3, 4, 5) Mark a 1 in each minterm square (010, 011, 100, and 101) Find possible adjacent squares (shaded rectangles) The upper right rectangle represents by x'y The lower left rectangle represents by xy' Sum of four minterms can be replaced by a sum of only two product terms: F = x'y + xy' 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 6
7 ThreeVariable KMap: K Ex. 2 Given: F(x, y, z) = (3, 4, 6, 7) Minterms are marked with 1's Two adjacent squares are combined in the third column to give the term yz The remaining two squares with 1's are also adjacent by wrapping, resulting in the term xz' Simplified function: F = yz + xz' 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 7
8 ThreeVariable KMap: K Ex. 3 Given: F(x, y, z) = (0, 2, 4, 5, 6) Minterms are marked with 1's Combine the four adjacent squares in the first and last columns to give the term z' m 5 is combined with an adjacent square that has already been used Desirable because the two adjacent squares gives fewer literals (xy') compared to xy'z Simplified function: F = z' + xy' 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 8
9 ThreeVariable KMap: K Ex. 4 Given: F = A'C + A'B + AB'C + BC Express as sum of minterms: A'C = m 1 + m 3 A'B = m 3 + m 2 AB'C = m 5 BC = m 3 + m 7 Remove duplicates: F (A, B, C) = (1, 2, 3, 5, 7) Minimal sumofproducts expression from map: F = C + A'B 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 9
10 FourVariable KMapK Four binary variables (w,x,y,z) 16 squares NOTE numbering! One square One term, four literals Two adjacent squares One term, three literals Four adjacent squares One term, two literals Eight adjacent squares One term, one literal 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 10
11 FourVariable KMap: K Ex. 1 F (w, x, y, z) = (0,1,2,4,5,6,8,9,12,13,14) Fill map Eight adjacent squares on left form the term y' Three 1's on right can wrap to left to form terms w'z' and xz' Simplified function: F = y' + w'z' + xz' 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 11
12 FourVariable KMap: K Ex. 2 Given: F = A'B'C' + B'CD' + A'BCD' + AB'C' Find minterms: A'B'C' = m 0 + m 1 B'CD' = m 2 + m 10 A'BCD' = m 6 AB'C' = m 8 + m 9 New function: F (A, B, C) = (0,1,2,6,8,9,10) The simplified function: F = B'D' + B'C' + A'CD' 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 12
13 Prime Implicants Prime implicant is a product term obtained by combining the maximum possible number of adjacent squares in the map It cannot be combined with another term to eliminate a variable If a minterm in a square is covered by only one prime implicant, that prime implicant is said to be essential 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 13
14 Given: F(A, B, C, D) = (0, 2, 3, 5, 7, 8, 9, 10, 11, 13, 15) Minterms marked on partial map m 3, m 9, and m 11 are omitted for now Partial map shows two essential prime implicants with only two literals Prime Implicants 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 14
15 Prime Implicants m 3, m 9, and m 11 are handled with more prime implicants: m 3 can be covered with either CD or B'C m 9 can be covered with either AD or AB' m 11 is covered with any one of the above four prime implicants BD and B'D' are prime implicants since m 0 and m 5 are covered once by them Four possible functions: F = BD + B'D' + CD + AD = BD + B'D' + CD + AB' = BD + B'D' + B'C + AD = BD + B'D' + B'C + AB' 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 15
16 AB CDE 00 FiveVariable KMapK D m 0 m 1 m 3 m 2 m 6 m 7 m 5 m 4 A m 8 m 9 m 11 m 10 m 14 m 15 m 13 m 12 m 24 m 25 m 27 m 26 m 30 m 31 m 29 m 28 m 16 m 17 m 19 m 18 m 22 m 23 m 21 m 20 B E E C 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 16
17 SixVariable KMapK E DEF ABC m 0 m 1 m 3 m 2 m 6 m 7 m 5 m m 8 m 9 m 11 m 10 m 14 m 15 m 13 m 12 m 24 m 25 m 27 m 26 m 30 m 31 m 29 m 28 C B m 16 m 17 m 19 m 18 m 22 m 23 m 21 m 20 m 48 m 49 m 51 m 50 m 54 m 55 m 53 m m 56 m 57 m 59 m 58 m 62 m 63 m 61 m 60 C A 101 m 40 m 41 m 43 m 42 m 46 m 47 m 45 m m 32 m 33 m 35 m 34 m 38 m 39 m 37 m 36 F F 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 17 D
18 Productof ofsums Simplification F (A, B, C, D) = (0, 1, 2, 5, 8, 9, 10) Mark 1's, simplify: F = B'D' + B'C' + A'C'D Mark 0's, simplify: F' = AB + CD + BD' DeMorgan's theorem: F = (A'+B')(C'+D')(B'+D) 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 18
19 Productof ofsums Simplification Standard forms: Sumofproducts: a group of AND gates and a single OR gate Productofsums: a group of OR gates and a single AND gate Assumed that the complement of input variables are available Either forms two levels of gates (twolevel implementation) First has 3 inputs on one of the AND gates 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 19
20 Productof ofsums Simplification Sum of minterms: F(x, y, z) = (1, 3, 4, 6) F = x'z + xz' Product of maxterms: F(x, y, z) = (0, 2, 5, 7) F' = xz + x'z' F = (x' + z')(x + z) To fill a map with a function expressed in productofsums form: Use the complement of the function to find the squares that are to be marked by 0's Mark the remaining squares with 1's 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 20
21 Don'tCare Conditions Sum of the minterms specifies the conditions under which the function is equal to 1 (0 for the rest of the minterms) Assumes all the combinations are valid It is possible that some combinations are not defined Eg. 4bit BCD only has 10 out of 16 states valid minterms may have don'tcare conditions incompletely specified functions Use don'tcare conditions to further simplify the Boolean expression Can be either a 0 or 1, use X to distinguish In choosing adjacent squares set X's to be whatever creates simplest function 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 21
22 Don'tCare Conditions 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 22
23 NAND Implementation NAND gate is a universal gate since any logic circuit can be implemented with it Complement is a oneinput NAND gate Can also be a twoinput NAND gate with inputs shorted AND is two NAND gates OR is a NAND gate with complemented inputs 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 23
24 NAND Implementation Obtain simplified Boolean function and then convert the function to NAND logic Sumofproducts Switch AND OR circuits to NAND Use alternative graphic symbols for the NAND gate: ANDinvert InvertOR 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 24
25 NAND 2Level 2 Implementation: Ex Roberto Muscedere Images 2013 Pearson Education Inc. 25
26 NAND 2Level 2 Implementation: Ex. 2 Given: F(x, y, z) = (1, 2, 3, 4, 5, 7) Simplified: F = xy' + x'y + z 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 26
27 F = A (CD + B) + BC' MultiLevel NAND Implementation: Ex. 1 In general: 1. Convert all AND to ANDinvert 2. Convert all OR to invertor 3. Check bubbles; insert inverters or complement literals if necessary 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 27
28 MultiLevel NAND Implementation: Ex. 2 F = (AB' + A'B)(C + D') 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 28
29 NOR Implementation NOR gate is also a universal gate since any logic circuit can be implemented with it Complement is a oneinput NOR gate Can also be a twoinput NOR gate with inputs shorted OR is two NOR gates AND is a NOR gate with complemented inputs 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 29
30 NOR Implementation Obtain simplified Boolean function and then convert the function to NOR logic Productofsums Switch ORAND circuits to NOR Use alternative graphic symbols for the NOR gate: ORinvert InvertAND 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 30
31 NOR Implementation: Ex. 1 F = (A + B)(C + D)E F = (AB' + A'B)(C + D') 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 31
32 ExclusiveOR Denoted by: x y = xy' + x'y Equal to 1 if x is not equal to y ExclusiveNOR (equivalence; XNOR) (x y)' = xy + x'y' Equal to 1 if x is equal to y Both are commutative and associative Can be implemented with standard gates 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 32
33 XOR: Odd Function A B C = (AB' + A'B)C' + (AB + A'B')C = AB'C' + A'BC' + ABC + A'B'C = (1, 2, 4, 7) A B C D = (AB' + A'B) (CD' + C'D) = (AB' + A'B)(CD + C'D') + (AB + A'B')(CD' + C'D) = (1, 2, 4, 7, 8, 11, 13, 14) XOR is an odd function since it is 1 whenever the sum of the inputs is odd Complement of F is an even function XOR/XNOR function cannot be reduced 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 33
34 XOR: Parity Generation/Checking Generate even (including parity bit) parity: P = x y z Check even parity: C = x y z P Same circuit if P = Roberto Muscedere Images 2013 Pearson Education Inc. 34
Chapter 3. GateLevel Minimization. Outlines
Chapter 3 GateLevel Minimization Introduction The Map Method FourVariable Map FiveVariable Map Outlines Product of Sums Simplification Don tcare Conditions NAND and NOR Implementation Other TwoLevel
More informationGateLevel Minimization
GateLevel Minimization ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2011 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines The Map Method
More informationGateLevel Minimization
MEC520 디지털공학 GateLevel Minimization JeeHwan Ryu School of Mechanical Engineering GateLevel MinimizationThe Map Method Truth table is unique Many different algebraic expression Boolean expressions may
More informationGateLevel Minimization
GateLevel Minimization ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2017 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines The Map Method
More informationGate Level Minimization
Gate Level Minimization By Dr. M. Hebaishy Digital Logic Design Ch Simplifying Boolean Equations Example : Y = AB + AB Example 2: = B (A + A) T8 = B () T5 = B T Y = A(AB + ABC) = A (AB ( + C ) ) T8 =
More information數位系統 Digital Systems 朝陽科技大學資工系. Speaker: FuwYi Yang 楊伏夷. 伏夷非征番, 道德經察政章 (Chapter 58) 伏者潛藏也道紀章 (Chapter 14) 道無形象, 視之不可見者曰夷
數位系統 Digital Systems Department of Computer Science and Information Engineering, Chaoyang University of Technology 朝陽科技大學資工系 Speaker: FuwYi Yang 楊伏夷 伏夷非征番, 道德經察政章 (Chapter 58) 伏者潛藏也道紀章 (Chapter 14) 道無形象,
More informationChapter 2 Combinational Logic Circuits
Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Overview Part Gate Circuits and Boolean Equations Binary Logic and Gates Boolean Algebra Standard
More informationGet Free notes at ModuleI One s Complement: Complement all the bits.i.e. makes all 1s as 0s and all 0s as 1s Two s Complement: One s complement+1 SIGNED BINARY NUMBERS Positive integers (including zero)
More informationChapter 2 Combinational
Computer Engineering 1 (ECE290) Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization HOANG Trang 2008 Pearson Education, Inc. Overview Part 1 Gate Circuits and Boolean Equations Binary Logic
More informationBoolean Algebra and Logic Gates
Boolean Algebra and Logic Gates Binary logic is used in all of today's digital computers and devices Cost of the circuits is an important factor Finding simpler and cheaper but equivalent circuits can
More informationA B AB CD Objectives:
Objectives:. Four variables maps. 2. Simplification using prime implicants. 3. "on t care" conditions. 4. Summary.. Four variables Karnaugh maps Minterms A A m m m3 m2 A B C m4 C A B C m2 m8 C C m5 C m3
More informationSimplification of Boolean Functions
Simplification of Boolean Functions Contents: Why simplification? The Map Method Two, Three, Four and Five variable Maps. Simplification of two, three, four and five variable Boolean function by Map method.
More informationIT 201 Digital System Design Module II Notes
IT 201 Digital System Design Module II Notes BOOLEAN OPERATIONS AND EXPRESSIONS Variable, complement, and literal are terms used in Boolean algebra. A variable is a symbol used to represent a logical quantity.
More informationChapter 2. Boolean Expressions:
Chapter 2 Boolean Expressions: A Boolean expression or a function is an expression which consists of binary variables joined by the Boolean connectives AND and OR along with NOT operation. Any Boolean
More informationGateLevel Minimization. BME208 Logic Circuits Yalçın İŞLER
GateLevel Minimization BME28 Logic Circuits Yalçın İŞLER islerya@yahoo.com http://me.islerya.com Complexity of Digital Circuits Directly related to the complexity of the algebraic expression we use to
More information2.1 Binary Logic and Gates
1 EED2003 Digital Design Presentation 2: Boolean Algebra Asst. Prof.Dr. Ahmet ÖZKURT Asst. Prof.Dr Hakkı T. YALAZAN Based on the Lecture Notes by Jaeyoung Choi choi@comp.ssu.ac.kr Fall 2000 2.1 Binary
More informationUNIT II. Circuit minimization
UNIT II Circuit minimization The complexity of the digital logic gates that implement a Boolean function is directly related to the complexity of the algebraic expression from which the function is implemented.
More information2008 The McGrawHill Companies, Inc. All rights reserved.
28 The McGrawHill Companies, Inc. All rights reserved. 28 The McGrawHill Companies, Inc. All rights reserved. All or Nothing Gate Boolean Expression: A B = Y Truth Table (ee next slide) or AB = Y 28
More informationDigital Logic Design. Outline
Digital Logic Design GateLevel Minimization CSE32 Fall 2 Outline The Map Method 2,3,4 variable maps 5 and 6 variable maps (very briefly) Product of sums simplification Don t Care conditions NAND and NOR
More informationGateLevel Minimization
GateLevel Minimization Mano & Ciletti Chapter 3 By Suleyman TOSUN Ankara University Outline Intro to GateLevel Minimization The Map Method 2345 variable map methods ProductofSums Method Don t care
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 3 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter
More informationAssignment (36) Boolean Algebra and Logic Simplification  General Questions
Assignment (36) Boolean Algebra and Logic Simplification  General Questions 1. Convert the following SOP expression to an equivalent POS expression. 2. Determine the values of A, B, C, and D that make
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 3 Following the slides of Dr. Ahmed H. Madian ذو الحجة 1438 ه Winter
More informationCombinational Logic Circuits
Chapter 3 Combinational Logic Circuits 12 Hours 24 Marks 3.1 Standard representation for logical functions Boolean expressions / logic expressions / logical functions are expressed in terms of logical
More informationCombinational Logic Circuits
Chapter 2 Combinational Logic Circuits J.J. Shann (Slightly trimmed by C.P. Chung) Chapter Overview 21 Binary Logic and Gates 22 Boolean Algebra 23 Standard Forms 24 TwoLevel Circuit Optimization
More informationSimplification of Boolean Functions
COM111 Introduction to Computer Engineering (Fall 20062007) NOTES 5  page 1 of 5 Introduction Simplification of Boolean Functions You already know one method for simplifying Boolean expressions: Boolean
More informationDKT 122/3 DIGITAL SYSTEM 1
Company LOGO DKT 122/3 DIGITAL SYSTEM 1 BOOLEAN ALGEBRA (PART 2) Boolean Algebra Contents Boolean Operations & Expression Laws & Rules of Boolean algebra DeMorgan s Theorems Boolean analysis of logic circuits
More informationExperiment 4 Boolean Functions Implementation
Experiment 4 Boolean Functions Implementation Introduction: Generally you will find that the basic logic functions AND, OR, NAND, NOR, and NOT are not sufficient to implement complex digital logic functions.
More informationLSN 4 Boolean Algebra & Logic Simplification. ECT 224 Digital Computer Fundamentals. Department of Engineering Technology
LSN 4 Boolean Algebra & Logic Simplification Department of Engineering Technology LSN 4 Key Terms Variable: a symbol used to represent a logic quantity Compliment: the inverse of a variable Literal: a
More informationCSCI 220: Computer Architecture I Instructor: Pranava K. Jha. Simplification of Boolean Functions using a Karnaugh Map
CSCI 22: Computer Architecture I Instructor: Pranava K. Jha Simplification of Boolean Functions using a Karnaugh Map Q.. Plot the following Boolean function on a Karnaugh map: f(a, b, c, d) = m(, 2, 4,
More information1. Mark the correct statement(s)
1. Mark the correct statement(s) 1.1 A theorem in Boolean algebra: a) Can easily be proved by e.g. logic induction b) Is a logical statement that is assumed to be true, c) Can be contradicted by another
More informationChapter 2 Combinational Logic Circuits
Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Charles Kime & Thomas Kaminski 2008 Pearson Education, Inc. (Hyperlinks are active in View Show
More informationCHAPTER2 STRUCTURE OF BOOLEAN FUNCTION USING GATES, KMap and QuineMcCluskey
CHAPTER2 STRUCTURE OF BOOLEAN FUNCTION USING GATES, KMap and QuineMcCluskey 2. Introduction Logic gates are connected together to produce a specified output for certain specified combinations of input
More informationPoints Addressed in this Lecture. Standard form of Boolean Expressions. Lecture 4: Logic Simplication & Karnaugh Map
Points Addressed in this Lecture Lecture 4: Logic Simplication & Karnaugh Map Professor Peter Cheung Department of EEE, Imperial College London Standard form of Boolean Expressions SumofProducts (SOP),
More informationCombinational Logic & Circuits
WeekI Combinational Logic & Circuits Spring' 232  Logic Design Page Overview Binary logic operations and gates Switching algebra Algebraic Minimization Standard forms Karnaugh Map Minimization Other
More informationUnitIV Boolean Algebra
UnitIV Boolean Algebra Boolean Algebra Chapter: 08 Truth table: Truth table is a table, which represents all the possible values of logical variables/statements along with all the possible results of
More informationSpecifying logic functions
CSE4: Components and Design Techniques for Digital Systems Specifying logic functions Instructor: Mohsen Imani Slides from: Prof.Tajana Simunic and Dr.Pietro Mercati We have seen various concepts: Last
More informationExperiment 3: Logic Simplification
Module: Logic Design Name:... University no:.. Group no:. Lab Partner Name: Mr. Mohamed ElSaied Experiment : Logic Simplification Objective: How to implement and verify the operation of the logical functions
More informationChapter 3 Simplification of Boolean functions
3.1 Introduction Chapter 3 Simplification of Boolean functions In this chapter, we are going to discuss several methods for simplifying the Boolean function. What is the need for simplifying the Boolean
More informationChapter 2 Boolean algebra and Logic Gates
Chapter 2 Boolean algebra and Logic Gates 2. Introduction In working with logic relations in digital form, we need a set of rules for symbolic manipulation which will enable us to simplify complex expressions
More informationUNIT4 BOOLEAN LOGIC. NOT Operator Operates on single variable. It gives the complement value of variable.
UNIT4 BOOLEAN LOGIC Boolean algebra is an algebra that deals with Boolean values((true and FALSE). Everyday we have to make logic decisions: Should I carry the book or not?, Should I watch TV or not?
More informationDigital Logic Lecture 7 Gate Level Minimization
Digital Logic Lecture 7 Gate Level Minimization By Ghada AlMashaqbeh The Hashemite University Computer Engineering Department Outline Introduction. Kmap principles. Simplification using Kmaps. Don tcare
More informationCode No: 07A3EC03 Set No. 1
Code No: 07A3EC03 Set No. 1 II B.Tech I Semester Regular Examinations, November 2008 SWITCHING THEORY AND LOGIC DESIGN ( Common to Electrical & Electronic Engineering, Electronics & Instrumentation Engineering,
More informationIncompletely Specified Functions with Don t Cares 2Level Transformation Review Boolean Cube KarnaughMap Representation and Methods Examples
Lecture B: Logic Minimization Incompletely Specified Functions with Don t Cares 2Level Transformation Review Boolean Cube KarnaughMap Representation and Methods Examples Incompletely specified functions
More informationCS8803: Advanced Digital Design for Embedded Hardware
CS883: Advanced Digital Design for Embedded Hardware Lecture 2: Boolean Algebra, Gate Network, and Combinational Blocks Instructor: Sung Kyu Lim (limsk@ece.gatech.edu) Website: http://users.ece.gatech.edu/limsk/course/cs883
More informationLiteral Cost F = BD + A B C + A C D F = BD + A B C + A BD + AB C F = (A + B)(A + D)(B + C + D )( B + C + D) L = 10
Circuit Optimization Goal: To obtain the simplest implementation for a given function Optimization is a more formal approach to simplification that is performed using a specific procedure or algorithm
More informationX Y Z F=X+Y+Z
This circuit is used to obtain the compliment of a value. If X = 0, then X = 1. The truth table for NOT gate is : X X 0 1 1 0 2. OR gate : The OR gate has two or more input signals but only one output
More informationQUESTION BANK FOR TEST
CSCI 2121 Computer Organization and Assembly Language PRACTICE QUESTION BANK FOR TEST 1 Note: This represents a sample set. Please study all the topics from the lecture notes. Question 1. Multiple Choice
More informationENGINEERS ACADEMY. 7. Given Boolean theorem. (a) A B A C B C A B A C. (b) AB AC BC AB BC. (c) AB AC BC A B A C B C.
Digital Electronics Boolean Function QUESTION BANK. The Boolean equation Y = C + C + C can be simplified to (a) (c) A (B + C) (b) AC (d) C. The Boolean equation Y = (A + B) (A + B) can be simplified to
More informationSWITCHING THEORY AND LOGIC CIRCUITS
SWITCHING THEORY AND LOGIC CIRCUITS COURSE OBJECTIVES. To understand the concepts and techniques associated with the number systems and codes 2. To understand the simplification methods (Boolean algebra
More informationSlide Set 5. for ENEL 353 Fall Steve Norman, PhD, PEng. Electrical & Computer Engineering Schulich School of Engineering University of Calgary
Slide Set 5 for ENEL 353 Fall 207 Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary Fall Term, 207 SN s ENEL 353 Fall 207 Slide Set 5 slide
More informationDigital Design. Chapter 4. Principles Of. Simplification of Boolean Functions
Principles Of Digital Design Chapter 4 Simplification of Boolean Functions Karnaugh Maps Don t Care Conditions Technology Mapping Optimization, Conversions, Decomposing, Retiming Boolean Cubes for n =,
More informationChapter 2: Combinational Systems
Uchechukwu Ofoegbu Chapter 2: Combinational Systems Temple University Adapted from Alan Marcovitz s Introduction to Logic and Computer Design Riddle Four switches can be turned on or off. One is the switch
More informationCombinational Circuits
Combinational Circuits Combinational circuit consists of an interconnection of logic gates They react to their inputs and produce their outputs by transforming binary information n input binary variables
More informationReview: Standard forms of expressions
Karnaugh maps Last time we saw applications of Boolean logic to circuit design. The basic Boolean operations are AND, OR and NOT. These operations can be combined to form complex expressions, which can
More informationDIGITAL CIRCUIT LOGIC UNIT 7: MULTILEVEL GATE CIRCUITS NAND AND NOR GATES
DIGITAL CIRCUIT LOGIC UNIT 7: MULTILEVEL GATE CIRCUITS NAND AND NOR GATES 1 iclicker Question 13 Considering the KMap, f can be simplified as (2 minutes): A) f = b c + a b c B) f = ab d + a b d AB CD
More informationCombinational Logic Circuits Part III Theoretical Foundations
Combinational Logic Circuits Part III Theoretical Foundations Overview Simplifying Boolean Functions Algebraic Manipulation Karnaugh Map Manipulation (simplifying functions of 2, 3, 4 variables) Systematic
More informationCMPE223/CMSE222 Digital Logic
CMPE223/CMSE222 Digital Logic Optimized Implementation of Logic Functions: Strategy for Minimization, Minimum ProductofSums Forms, Incompletely Specified Functions Terminology For a given term, each
More informationCombinational Circuits Digital Logic (Materials taken primarily from:
Combinational Circuits Digital Logic (Materials taken primarily from: http://www.facstaff.bucknell.edu/mastascu/elessonshtml/eeindex.html http://www.cs.princeton.edu/~cos126 ) Digital Systems What is a
More informationModule 7. Karnaugh Maps
1 Module 7 Karnaugh Maps 1. Introduction 2. Canonical and Standard forms 2.1 Minterms 2.2 Maxterms 2.3 Canonical Sum of Product or SumofMinterms (SOM) 2.4 Canonical product of sum or ProductofMaxterms(POM)
More information2.6 BOOLEAN FUNCTIONS
2.6 BOOLEAN FUNCTIONS Binary variables have two values, either 0 or 1. A Boolean function is an expression formed with binary variables, the two binary operators AND and OR, one unary operator NOT, parentheses
More informationStandard Forms of Expression. Minterms and Maxterms
Standard Forms of Expression Minterms and Maxterms Standard forms of expressions We can write expressions in many ways, but some ways are more useful than others A sum of products (SOP) expression contains:
More informationContents. Chapter 3 Combinational Circuits Page 1 of 34
Chapter 3 Combinational Circuits Page of 34 Contents Contents... 3 Combinational Circuits... 2 3. Analysis of Combinational Circuits... 2 3.. Using a Truth Table... 2 3..2 Using a Boolean unction... 4
More informationBawar Abid Abdalla. Assistant Lecturer Software Engineering Department Koya University
Logic Design First Stage Lecture No.6 Boolean Algebra Bawar Abid Abdalla Assistant Lecturer Software Engineering Department Koya University Outlines Boolean Operations Laws of Boolean Algebra Rules of
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Supplementary Examinations, February 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science
More informationGateLevel Minimization. section instructor: Ufuk Çelikcan
GateLevel Minimization section instructor: Ufuk Çelikcan Compleity of Digital Circuits Directly related to the compleity of the algebraic epression we use to build the circuit. Truth table may lead to
More informationAnnouncements. Chapter 2  Part 1 1
Announcements If you haven t shown the grader your proof of prerequisite, please do so by 11:59 pm on 09/05/2018 (Wednesday). I will drop students that do not show us the prerequisite proof after this
More informationSummary. Boolean Addition
Summary Boolean Addition In Boolean algebra, a variable is a symbol used to represent an action, a condition, or data. A single variable can only have a value of or 0. The complement represents the inverse
More informationS1 Teknik Telekomunikasi Fakultas Teknik Elektro FEH2H3 2016/2017
S1 Teknik Telekomunikasi Fakultas Teknik Elektro FEH2H3 2016/2017 Karnaugh Map Karnaugh maps Last time we saw applications of Boolean logic to circuit design. The basic Boolean operations are AND, OR and
More informationLecture 4: Implementation AND, OR, NOT Gates and Complement
EE210: Switching Systems Lecture 4: Implementation AND, OR, NOT Gates and Complement Prof. YingLi Tian Feb. 13, 2018 Department of Electrical Engineering The City College of New York The City University
More informationBinary logic. Dr.AbuArqoub
Binary logic Binary logic deals with variables like (a, b, c,, x, y) that take on two discrete values (, ) and with operations that assume logic meaning ( AND, OR, NOT) Truth table is a table of all possible
More informationBOOLEAN ALGEBRA. Logic circuit: 1. From logic circuit to Boolean expression. Derive the Boolean expression for the following circuits.
COURSE / CODE DIGITAL SYSTEMS FUNDAMENTAL (ECE 421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE 422) BOOLEAN ALGEBRA Boolean Logic Boolean logic is a complete system for logical operations. It is used in countless
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2006 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems
More informationChapter 3. Boolean Algebra and Digital Logic
Chapter 3 Boolean Algebra and Digital Logic Chapter 3 Objectives Understand the relationship between Boolean logic and digital computer circuits. Learn how to design simple logic circuits. Understand how
More informationSwitching Circuits & Logic Design
Switching Circuits & Logic Design JieHong Roland Jiang 江介宏 Department of Electrical Engineering National Taiwan University Fall 23 5 Karnaugh Maps Kmap Walks and Gray Codes http://asicdigitaldesign.wordpress.com/28/9/26/kmapswalksandgraycodes/
More informationLOGIC CIRCUITS. Kirti P_Didital Design 1
LOGIC CIRCUITS Kirti P_Didital Design 1 Introduction The digital system consists of two types of circuits, namely (i) Combinational circuits and (ii) Sequential circuit A combinational circuit consists
More informationDepartment of Electrical and Computer Engineering University of Wisconsin  Madison. ECE/CS 352 Digital System Fundamentals.
Department of Electrical and Computer Engineering University of Wisconsin  Madison ECE/C 352 Digital ystem Fundamentals Quiz #2 Thursday, March 7, 22, 7:158:3PM 1. (15 points) (a) (5 points) NAND, NOR
More information4 KARNAUGH MAP MINIMIZATION
4 KARNAUGH MAP MINIMIZATION A Karnaugh map provides a systematic method for simplifying Boolean expressions and, if properly used, will produce the simplest SOP or POS expression possible, known as the
More informationCh. 5 : Boolean Algebra &
Ch. 5 : Boolean Algebra & Reduction elektronik@fisika.ui.ac.id Objectives Should able to: Write Boolean equations for combinational logic applications. Utilize Boolean algebra laws and rules for simplifying
More informationECE380 Digital Logic
ECE38 Digital Logic Optimized Implementation of Logic Functions: Strategy for Minimization, Minimum ProductofSums Forms, Incompletely Specified Functions Dr. D. J. Jackson Lecture 8 Terminology For
More informationMUX using TriState Buffers. Chapter 2  Part 2 1
MUX using TriState Buffers Chapter 2  Part 2 Systematic Simplification A Prime Implicant is a product term obtained by combining the maximum possible number of adjacent squares in the map into a rectangle
More informationUniversity of Technology
University of Technology Lecturer: Dr. Sinan Majid Course Title: microprocessors 4 th year Lecture 5 & 6 Minimization with Karnaugh Maps Karnaugh maps lternate way of representing oolean function ll rows
More informationTWOLEVEL COMBINATIONAL LOGIC
TWOLEVEL COMBINATIONAL LOGIC OVERVIEW Canonical forms Tolevel simplification Boolean cubes Karnaugh maps QuineMcClusky (Tabulation) Method Don't care terms Canonical and Standard Forms Minterms and
More informationBawar Abid Abdalla. Assistant Lecturer Software Engineering Department Koya University
Logic Design First Stage Lecture No.5 Boolean Algebra Bawar Abid Abdalla Assistant Lecturer Software Engineering Department Koya University Boolean Operations Laws of Boolean Algebra Rules of Boolean Algebra
More informationClass Subject Code Subject Prepared By Lesson Plan for Time: Lesson. No 1.CONTENT LIST: Introduction to UnitI 2. SKILLS ADDRESSED: Listening I year, 02 sem CS6201 Digital Principles & System Design S.Seedhanadevi
More informationCprE 281: Digital Logic
CprE 28: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Minimization CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev Administrative
More informationNH 67, Karur Trichy Highways, Puliyur C.F, Karur District DEPARTMENT OF INFORMATION TECHNOLOGY CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN
NH 67, Karur Trichy Highways, Puliyur C.F, 639 114 Karur District DEPARTMENT OF INFORMATION TECHNOLOGY CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT 1 BOOLEAN ALGEBRA AND LOGIC GATES Review of binary
More informationLecture 5. Chapter 2: Sections 47
Lecture 5 Chapter 2: Sections 47 Outline Boolean Functions What are Canonical Forms? Minterms and Maxterms Index Representation of Minterms and Maxterms SumofMinterm (SOM) Representations ProductofMaxterm
More informationKarnaugh Map (KMap) Karnaugh Map. Karnaugh Map Examples. Ch. 2.4 Ch. 2.5 Simplification using Kmap
Karnaugh Map (KMap) Ch. 2.4 Ch. 2.5 Simplification using Kmap A graphical map method to simplify Boolean function up to 6 variables A diagram made up of squares Each square represents one minterm (or
More informationChapter 4. Combinational Logic. Dr. AbuArqoub
Chapter 4 Combinational Logic Introduction N Input Variables Combinational Logic Circuit M Output Variables 2 Design Procedure The problem is stated 2 The number of available input variables & required
More informationDigital Logic Design (CEN120) (3+1)
Digital Logic Design (CEN120) (3+1) ASSISTANT PROFESSOR Engr. Syed Rizwan Ali, MS(CAAD)UK, PDG(CS)UK, PGD(PM)IR, BS(CE)PK HEC Certified Master Trainer (MTFPDP) PEC Certified Professional Engineer (COM/2531)
More informationLecture (05) Boolean Algebra and Logic Gates
Lecture (05) Boolean Algebra and Logic Gates By: Dr. Ahmed ElShafee ١ Minterms and Maxterms consider two binary variables x and y combined with an AND operation. Since eachv ariable may appear in either
More informationComputer Science. Unit4: Introduction to Boolean Algebra
Unit4: Introduction to Boolean Algebra Learning Objective At the end of the chapter students will: Learn Fundamental concepts and basic laws of Boolean algebra. Learn about Boolean expression and will
More informationR.M.D. ENGINEERING COLLEGE R.S.M. Nagar, Kavaraipettai
L T P C R.M.D. ENGINEERING COLLEGE R.S.M. Nagar, Kavaraipettai 601206 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC8392 UNIT  I 3 0 0 3 OBJECTIVES: To present the Digital fundamentals, Boolean
More information2. BOOLEAN ALGEBRA 2.1 INTRODUCTION
2. BOOLEAN ALGEBRA 2.1 INTRODUCTION In the previous chapter, we introduced binary numbers and binary arithmetic. As you saw in binary arithmetic and in the handling of floatingpoint numbers, there is
More information3.4 QUINE MCCLUSKEY METHOD 73. f(a, B, C, D, E)¼AC ĒþB CD þ BCDþĀBD.
3.4 QUINE MCCLUSKEY METHOD 73 FIGURE 3.22 f(a, B, C, D, E)¼B CD þ BCD. FIGURE 3.23 f(a, B, C, D, E)¼AC ĒþB CD þ BCDþĀBD. A¼1map are, 1, and 1, respectively, whereas the corresponding entries in the A¼0
More informationPhiladelphia University Faculty of Information Technology Department of Computer Science. Computer Logic Design. By Dareen Hamoudeh.
Philadelphia University Faculty of Information Technology Department of Computer Science Computer Logic Design By Dareen Hamoudeh Dareen Hamoudeh 1 Canonical Forms (Standard Forms of Expression) Minterms
More informationEEE130 Digital Electronics I Lecture #4_1
EEE130 Digital Electronics I Lecture #4_1  Boolean Algebra and Logic Simplification  By Dr. Shahrel A. Suandi 46 Standard Forms of Boolean Expressions There are two standard forms: Sumofproducts form
More informationVariable, Complement, and Literal are terms used in Boolean Algebra.
We have met gate logic and combination of gates. Another way of representing gate logic is through Boolean algebra, a way of algebraically representing logic gates. You should have already covered the
More information