Crosstalk Noise Avoidance in Asynchronous Circuits

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1 Crosstalk Noise Avoidance in Asynchronous Circuits Alexander Taubin (University of Aizu) Alex Kondratyev (University of Aizu) J. Cortadella (Univ. Politecnica Catalunya) Luciano Lavagno (University of Udine)

2 Outline Noise in DSM and asynchronous circuits Crosstalk noise and faults Behavioral Model: Signal Transition Graphs Different scenarios for noise avoidance Sensitization of gates to the noise Improving logical and temporal separations Conclusions

3 Moving to Deep Submicron Current Technology Design for Deep Submicron (DSM) Design for Power Speed Testing Power Speed Testing Low noise For DSM noise immunity is of importance similar to power,speed, etc.!

4 Why self-timing is good for noise Absence of clock reduces [Cogency 97]: Simultaneously switching noise High frequency components (400%) Electro-Magnetic Interference -EMI (order or magnitude) Does not help in reducing crosstalk noise

5 Crosstalk noise No crosstalk under sufficiently large spacing C sub

6 Moving to DSM - closer packing - nonuniform scaling - lower noise margins - higher speed of voltage changes C c C c Coupling noise from 2 aggressors > 30% Vdd [Gal 95] C sub

7 Design flow Specification Convergence? Efficiency? Synthesis Gate netlist Layout Adjacency constraints Physical design Simulation Crosstalk noise reduction - large number of iterations between layout and analysis step

8 Design flow Design for low noise Specification Kirkpatrick, Sangiovanni-Vincentelli (for synchronous logic) Helps the layout tool by solving part of problems at logic level Synthesis Gate netlist + constraints Layout Noise analysis Adjacency constraints Physical design Simulation Constraint propagation

9 Design flow Presented work Specification Reshuffling, timing,... More help for the layout tool by solving part of problems at behaviour level Local transformations are only possible at the behavior level Adjacency constraints Uniform approach for sequential and combinational circuits Synthesis Layout Simulation Gate netlist + constraints Physical design Noise analysis

10 Type of faults due to crosstalk. I Transient fault Aggressor Victim Aggressor

11 Type of faults due to crosstalk. II Delay fault Aggressor Victim Crosstalk noise comes from concurrent switchings

12 Coupling noise Two adjacent aggressors to the middle victim (with 2min. spacing) J.Cong 97 Noise (% Vdd) Technology (nm) two aggressors two skewed aggressors one aggressor

13 Methodology for low-noise asynchronous circuit design Analysis of noise-critical sets of signals (noise generation and propagation conditions) Improving logical and temporal separations Logic optimization for low noise Clustering for reduction of crosstalk noise

14 Clustering: Global and Local Levels of Interconnections Global: long wires - long cross coupling Local: short distance (< 3mm) but high density (starting from 0.18µm suffer from crosstalk [Sylvester at al 98])

15 Analysis Aim Extraction of signal isolation (insensitivity to crosstalk noise) from specification The measurement: percentage of signal pairs isolated from noise About 50% of signal isolation is need to have reasonable impact to final circuit area [Kirkpatrick Sangiovanni-Vincentelli 96]

16 Noise Generation Conditions Specific cases of several signals switching the same time Can be checked by concurrency relations between signal transitions

17 Behaviour specifications x y z x y z z+ x- x+ y+ z- y- Signal Transition Graph (STG)

18 xyz 000 x+ x+ z+ y+ y- x- z- y- x- 001 y+ z+ y+ 100 y z- x- 111 z+ 010

19 Concurrency in State Graphs a and b are concurrent a b b a

20 Analysis of noise sources State graph Concurrency analyzer Transient faults Delay faults

21 Pessimistic scenario: All transient and delay faults are dangerous Noise avoidance at behaviour level change of spec signal reshuffling and concurrency reduction usage of timing assumptions

22 ([FHSWLRQVFRPLQJIURPVSHHGLQGHSHQGHQFH No fork - no delay fault 'HOD\RIZLUHZPLJKWEH LQFOXGHGLQWRGHOD\RIJDWH< Y w X Slow environment hypothesis ZWULJJHUVRQO\LQSXWHYHQW DV\PPHWULFLVRFKURQLFIRUN Y YLFWLPZLUH w Environment

23

24 y+ z+ y- xyz 0*10 x+ 11*0* y- 11*1 100* 001* z- 00*0 1*01 x- z+ y z x Environment 1*1*1 - potential transient fault for victim wire z 11*0* - potential delay faults for wires z and y Not dangerous - exception 2

25 Can we do better? Noise propagation conditions Not every pulse propagates through a circuit 0 x 0 Sensitization conditions F df/dx = 1 )LOWHULQJWUDQVLHQWIDXOWVE\VHQVLWL]DWLRQFRQGLWLRQV

26 Assumptions behind sensitization analysis 6HQVLWL]DWLRQLVH[DFWLIJDWHLQSXWVNHHSYDOXHVVXIILFLHQWO\ORQJ (i.e. for fundamental mode only) Enabled inputs cannot prevent noise propagation Discard enabled inputs from sensitization conditions (static sensitization)

27 Timing conditions for static sensitization x F 0 0 0

28 Timing conditions for static sensitization x F 0 1 0

29 Timing conditions for static sensitization x F delay_wire(x) < 2wire_delays + gate_delay &DQDOZD\VEHHQVXUHGE\GHOD\SDGGLQJ

30 Refining timing conditions DSr+ LDTACK+ LDS+ DTACK- DSr+ DTACK- LDS- LDS- LDS- DSr+ DTACK- IDXOW VRXUFH D+ DTACK+ LDTACK- LDTACK- LDTACK- DSr- D- Traverse SG from state Sens=0 until hit the space Sens=1 Estimate delays of the paths from Sens=0 to Sens=1

31 Analysis of delay faults w1 Y w2 victim wire X Dangerous case: w1 is trigger for Y, w2 is context for X Delay fault is negligible if context arrives in time

32 Timing conditions for delay faults w1 is context to Y sensitization to w1 is 0 w1 has some slack before sensitization to w1 becomes 1 Minimal slack value: delay_wire(w1) < 2delay_wire + gate_delay (refinement is possible)

33 Transformations for noise avoidance: Concurrency reduction DSr+ LDS+ DSr+ LDS- LDS- LDS DSr+

34 Transformations for noise avoidance: Concurrency reduction DSr+ LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK- DTACK-

35 Transformations for noise avoidance: Relative Timing Assumptions For concurrent events: (a b) and (a before b) concurrency reduction for firing and enabling (some states become unreachable) Used by the tool to derive a circuit and timing constraints Timing constraints must be met in physical design flow

36 Experimental results noise area concurrency isolation initial pessimistic optimistic 30 benchmarks * Behavior transformations preserve I/O interface

37 Conclusion Noise might be avoided at behavioural level Requires significant reduction of concurrency Needs correlation with logic and layout levels Smoothly incorporates into the design flow

38 Future tasks Layout approximations (for better guidance) Consideration of performance (for cost function) Experiments with noise isolation within the hierarchical approches - to tackle realistic design problems

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