Power and Thermal Models. for RAMP2

Transcription

1 Power and Thermal Models for 2 Jose Renau Department of Computer Engineering, University of California Santa Cruz

2 Motivation Performance not the only first order design parameter Energy consumption & thermal issues platforms lack power and thermal statistics Jose Renau 2

3 Issues provides speed, we need fast power/thermal models Power Models Compute power on the FPGA or desktop? Most power models are for complex CPUs Need simple/validated CPUs models (IR setup to validate) Thermal Models Complex thermal models difficult to map to FPGAs We need more detailed thermal model: SOI, PCB... Shared infrastructure across platforms Jose Renau 3

4 2 Integration Thermal Sensor visible to OS/CPU Target (MP Modeled) 9 1 Activity rate generation (adjust clock gate) 8 Pass temperature and power? 7 Set Thermal Sensor 6 Pass temperature (every ~ few ms) Host (FPGA) SESCTherm (Desktop) FEM Solver (GPU) Activity rate transfer (once every ~1ms) 2 Estimate Dyn Power Compute Leakage with current temperature 3 Pass total power 4 Compute temperature 5 Jose Renau 4

5 Activity Rate Generation Similar approach to Wattch A counter for each resource Increase after each use Account for clock gating Not everything is 100% clock gated SESC uses ~80 counters for each CPU Large 32bit counters only require 320 Bytes per CPU Jose Renau 5

6 Activity Rate Transfer ~80 counters per CPU Slow temperature transients Temperature (C) RF D$ FP0 Clock MC I$ Time (s) 3 4 ~1ms is enough Trivial encoding :(32 bit x 80)/ 1ms = 320 KBytes/s per CPU AR (1/256) just requires 80 KBytes/s per CPU Additional optimizations are possible (floorplan block clustering~10kb/s) Jose Renau 6

7 Outline Motivation 2 Integration SESCTherm (Thermal Model) Thermal Sensors Q/A Jose Renau 7

8 SESCTherm: Thermal Model Finite element analysis of thermal processes Conduction, convention, and radiation Similar to HotSpot but.. Different transistor densities through die Supports multiple cooling solutions Package / die material layers (SOI, Al/Cu, etc) Highly extendable and scalable 3D chips ready Can be used stand alone or coupled with our architectural simulator (SESC) Jose Renau 8

9 SESCTherm Model 61 Figure 2.12: Sample Layer Stack for Flip-Chip Pin Grid Array-Type Package Assembly Jose Renau 9

10 Board+Densities+Package+SOI Jose Renau 10

11 SOI Modeling Jose Renau 11

12 SESCTherm Validation IR Infrastructure used to validate SESCTherm Current: a simple flip-chip (no package) Future: a 40nm TSMC testchip with full package Jose Renau 12

13 SESCTherm Validation Jose Renau 13

14 Current Simulation Speed 250um resolution (100mm^2 chip) ( times slower than real time) Jose Renau 14

15 Faster Thermal Model Difficult to implement using FPGAs Floating point requirements Continuous parameter update (temperature dependence) GPUs Use 32bit FP (done) Port to CUDA the sparse matrix solver (done) Currently, only 2x speedup Optimize the CUDA port (work in progress) Objective Detailed thermal simulation ~10 slower than native Jose Renau 15

16 SESCTherm Video AMD Athlon simulated thermal map 2 seconds native simulation Video ~x16 slower than native (~MASC perf. 2 goal) Currently, it requires 3 minutes to compute Jose Renau 16

17 Power Models Configurable floorplan Inst. Pick Clock Distribution ALUs DTLB Memory Controller 1 L1I 0 2 Bus 1 L1D 0 FP0 FRF LSQ SSE Clock Fetch Sched ROB IRF FPSched Power model for each processor block P ower = P dyn +P leak0 T 2 e (P leak1/t ) (1 e Pleak2/T ) Dynamic Leakage Jose Renau 17

18 Feedback Loop Temperature affects: Leakage Mostly quadratic effect Material properties Resistance/Capacitance linear Thermal sensor model CPU/OS Jose Renau 18

19 Thermal Sensor CPU/OS response to temperature uses thermal sensors Not as trivial as we thought E.g.: A commercial GPU thermal sensor is over 1mm 65nm Sampling rate and accuracy not so good Self-heating, calibration, leakage bias, etc... Where should sensors be placed? What is ideal # of sensors on die? Several sensor models Ideal Internal Temp Sensor Jose Renau 19

20 2 Integration Thermal Sensor visible to OS/CPU Target (MP Modeled) 9 1 Activity rate generation (adjust clock gate) 8 Pass temperature and power? 7 Set Thermal Sensor 6 Pass temperature (every ~ few ms) Host (FPGA) SESCTherm (Desktop) FEM Solver (GPU) Activity rate transfer (once every ~1ms) 2 Estimate Dyn Power Compute Leakage with current temperature 3 Pass total power 4 Compute temperature 5 Jose Renau 20

21 Questions? Power/Thermal Models for 2 Jose Renau renau@soe.ucsc.edu 21

22 Backup Slides Power/Thermal Models for 2 Jose Renau renau@soe.ucsc.edu 22

23 Our Experimental Setup Infrared Camera Oil Flow Voltage/ Power Logger Chip being measured Real-time Infrared Imaging Oil Cooling & Pump System Jose Renau 23