Synthesis 1. 1 Figures in this chapter taken from S. H. Gerez, Algorithms for VLSI Design Automation, Wiley, Typeset by FoilTEX 1

Size: px
Start display at page:

Download "Synthesis 1. 1 Figures in this chapter taken from S. H. Gerez, Algorithms for VLSI Design Automation, Wiley, Typeset by FoilTEX 1"

Transcription

1 Synthesis 1 1 Figures in this chapter taken from S. H. Gerez, Algorithms for VLSI Design Automation, Wiley, Typeset by FoilTEX 1

2 Introduction Logic synthesis is automatic generation of circuitry starting from bit-level descriptions. Behaviour of circuit is usually specified in Verilog or VHDL. Logic synthesis has two parts 1. Converting a behavioural (or algorithmic) description to a structural description. This is called High-level synthesis 2. The sub-optimal logic obtained from high-level synthesis is optimized High-level synthesis is beyond this course. We shall focus on minimizing circuit logic. Typeset by FoilTEX 2

3 Problem description Consider a boolean function f : B m B n m is the number of inputs n is the number of outputs B = { 0, 1 } This does not have don t cares. Including them we have f : B m Y n Y = { 0, 1, d } B m can be subdivided into on-set, off-set, dc-set on-set all elements in B m for which f is 1 off-set all elements in B m for which f is 0 dc-set all elements in B m for which f is d Example of elements in B 3 are (0, 1, 0), (0, 0, 0), (1, 1, 0),... etc. Typeset by FoilTEX 3

4 Problem description Consider the term. This can be shown on a cube. x 2 (a) (b) (c) The term is an example of a minterm. Each variable or its complement is called a literal. If a term has m distinct literals, it is called a minterm., are not minterms. These are called cubes. Any function f can be specified by a sum of minterms (also called sum of products) eg. f = Typeset by FoilTEX 4

5 Problem description f = This function can be represented on a cube as shown (a) (b) (c) The sum of minterms is a canonical form and is unique. This is used as a base reference for comparison later. Storing the canonical representation is an issue as it has 2 m minterms for m inputs. To minimize logic, think in terms of cubes. If a cube has at least one point in the on-set or dc-set it is called an implicant. An implicant not in any other implicant is called a prime implicants. Logic optimization is reduction of the function f to its prime implicants. This is what Karnaugh maps do. Typeset by FoilTEX 5

6 Logic Minimization- Quine McCluskey algorithm y = ā b c d + āb cd + ābcd + a b c d + a b cd + a bc d + a bcd + abc d + abcd Decimal Binary abcd Minterm ā b c d āb cd ābcd a b c d a b cd a bc d a bcd abc d abcd 0, 8 X000 A 5, 7 01X1 B 7, 15 X111 C 8, 9 100X 9, 11 10X1 10, X 10, 14 1X10 14, X 8,9 10,11 10XX D 10,11 14,15 1X1X E Typeset by FoilTEX 6

7 Quine McCluskey - Prime Implicants Minterm A B C D E X000 01X1 X111 10XX 1X1X C is redundant. y = b c d + ābd + a b + ac Typeset by FoilTEX 7

8 Concept of Restriction Binary decision diagrams f xi substitute 1 for x i in f(,,..., x n ). i.e. f xi = f(,,..., 1,..., x n ) Similarly, f xi = f(,,..., 0,..., x n ) These are positive and negative cofactors. Here we are restricting x i to certain values. Now f = x i f xi + x i f xi Note that this can be applied recursively throughout until logic 1 or 0 is left as a cofactor. Typeset by FoilTEX 8

9 Example f = f = f x1 + f x1 f x1 = + + f x1 = + + f = ( + + ) + ( + + ) = ( ( + ) + ( )) + ( ( ) + ( + )) = ( ( 1 + 1) + ( 1 + 0))+ ( ( 0 + 1) + ( 1 + 1)) Typeset by FoilTEX 9

10 Example f = This is an OBDD (Ordered Binary Decision Diagram). Dotted path represents positive cofactors; solid line path represents negative cofactors. Root vertex has no edges incident on it and leaf vertices have no edges diverging from them. A set of terminations will change an OBDD to an ROBDD (Reduced Ordered Binary Decision Diagram) Typeset by FoilTEX 10

11 ROBDD Transformations 1. Replace all identical leaf vertices with one vertex and redirect all edges to the new vertex 2. Process vertices from top to bottom. If two vertices are identical and their subtrees are identical. Remove one of them and redirect the connection of one to the other. 3. If a vertex has the same positive and negative cofactors, the vertex is redundant. Remove the vertex and connect directly to the child vertex. Implementation of these steps on an OBDD gives an ROBDD. Typeset by FoilTEX 11

12 Example 0 1 (a) 0 1 (b) 0 1 (c) Typeset by FoilTEX 12

13 ROBDDs Size of an ROBDD is based on the ordering we choose. chosen, and. As an exercise try, and. In this case we have eg. f = ( )( x 4 ) x 4 x 4 x 4 x (a) (b) To minimize the size of an ROBDD, we have to try all combinations of ordering. This is an NP-complete problem. For a given ordering an ROBDD is unique for a given function. It can thus be used as a canonical form to compare. Typeset by FoilTEX 13

14 ROBDDs can be ordered in two ways ROBDDs 1. Static 2. Dynamic A suite of methods are available to decide before generating an ROBDD to estimate what might be the best ordering. These are usually not helpful since often the expressions are changed; variables are removed and added. Dynamic methods are also present to determine the best order for the ROBDD dynamically. They are based on the fact that Swapping two adjacent vertices in the ROBDD introduces only local changes Typeset by FoilTEX 14

15 Example v a v a v a v a x k x l x k x l x l x l x k x k x l x l x k v b v c v d v e v b v d v c v e v b v c v d v b v d v c (a) (b) Typeset by FoilTEX 15

16 Heuristics for minimizing ROBDDs Brute force method 1. Select a variable and move through all points that can be taken. 2. Find the position where it can give minimum size. 3. Fix its position; pick another variable and repeat from step Iterate till all variables are assigned positions This will not give you the best ordering but something to work with. Note: Smallest ROBDD does not mean minimum logic. Complex methods exist that try to minimize logic. For example: f = x i f 1 + x i f 0 + f d Typeset by FoilTEX 16

17 f 0 f xi ; f 1 f xi ; f d f xi f xi This algorithm tries to find a solution such that f d is largest. Details of these methods will not be covered. Typeset by FoilTEX 17

Quine-McCluskey Algorithm

Quine-McCluskey Algorithm Quine-McCluskey Algorithm Useful for minimizing equations with more than 4 inputs. Like K-map, also uses combining theorem Allows for automation Chapter Edward McCluskey (99-06) Pioneer in Electrical

More information

Unit 4: Formal Verification

Unit 4: Formal Verification Course contents Unit 4: Formal Verification Logic synthesis basics Binary-decision diagram (BDD) Verification Logic optimization Technology mapping Readings Chapter 11 Unit 4 1 Logic Synthesis & Verification

More information

CSCI 220: Computer Architecture I Instructor: Pranava K. Jha. Simplification of Boolean Functions using a Karnaugh Map

CSCI 220: Computer Architecture I Instructor: Pranava K. Jha. Simplification of Boolean Functions using a Karnaugh Map CSCI 22: Computer Architecture I Instructor: Pranava K. Jha Simplification of Boolean Functions using a Karnaugh Map Q.. Plot the following Boolean function on a Karnaugh map: f(a, b, c, d) = m(, 2, 4,

More information

Introduction. The Quine-McCluskey Method Handout 5 January 24, CSEE E6861y Prof. Steven Nowick

Introduction. The Quine-McCluskey Method Handout 5 January 24, CSEE E6861y Prof. Steven Nowick CSEE E6861y Prof. Steven Nowick The Quine-McCluskey Method Handout 5 January 24, 2013 Introduction The Quine-McCluskey method is an exact algorithm which finds a minimum-cost sum-of-products implementation

More information

VLSI System Design Part II : Logic Synthesis (1) Oct Feb.2007

VLSI System Design Part II : Logic Synthesis (1) Oct Feb.2007 VLSI System Design Part II : Logic Synthesis (1) Oct.2006 - Feb.2007 Lecturer : Tsuyoshi Isshiki Dept. Communications and Integrated Systems, Tokyo Institute of Technology isshiki@vlsi.ss.titech.ac.jp

More information

3.4 QUINE MCCLUSKEY METHOD 73. f(a, B, C, D, E)¼AC ĒþB CD þ BCDþĀBD.

3.4 QUINE MCCLUSKEY METHOD 73. f(a, B, C, D, E)¼AC ĒþB CD þ BCDþĀBD. 3.4 QUINE MCCLUSKEY METHOD 73 FIGURE 3.22 f(a, B, C, D, E)¼B CD þ BCD. FIGURE 3.23 f(a, B, C, D, E)¼AC ĒþB CD þ BCDþĀBD. A¼1map are, 1, and 1, respectively, whereas the corresponding entries in the A¼0

More information

1/28/2013. Synthesis. The Y-diagram Revisited. Structural Behavioral. More abstract designs Physical. CAD for VLSI 2

1/28/2013. Synthesis. The Y-diagram Revisited. Structural Behavioral. More abstract designs Physical. CAD for VLSI 2 Synthesis The Y-diagram Revisited Structural Behavioral More abstract designs Physical CAD for VLSI 2 1 Structural Synthesis Behavioral Physical CAD for VLSI 3 Structural Processor Memory Bus Behavioral

More information

Karnaugh Map (K-Map) Karnaugh Map. Karnaugh Map Examples. Ch. 2.4 Ch. 2.5 Simplification using K-map

Karnaugh Map (K-Map) Karnaugh Map. Karnaugh Map Examples. Ch. 2.4 Ch. 2.5 Simplification using K-map Karnaugh Map (K-Map) Ch. 2.4 Ch. 2.5 Simplification using K-map A graphical map method to simplify Boolean function up to 6 variables A diagram made up of squares Each square represents one minterm (or

More information

Specifying logic functions

Specifying logic functions CSE4: Components and Design Techniques for Digital Systems Specifying logic functions Instructor: Mohsen Imani Slides from: Prof.Tajana Simunic and Dr.Pietro Mercati We have seen various concepts: Last

More information

Module -7. Karnaugh Maps

Module -7. Karnaugh Maps 1 Module -7 Karnaugh Maps 1. Introduction 2. Canonical and Standard forms 2.1 Minterms 2.2 Maxterms 2.3 Canonical Sum of Product or Sum-of-Minterms (SOM) 2.4 Canonical product of sum or Product-of-Maxterms(POM)

More information

CHAPTER-2 STRUCTURE OF BOOLEAN FUNCTION USING GATES, K-Map and Quine-McCluskey

CHAPTER-2 STRUCTURE OF BOOLEAN FUNCTION USING GATES, K-Map and Quine-McCluskey CHAPTER-2 STRUCTURE OF BOOLEAN FUNCTION USING GATES, K-Map and Quine-McCluskey 2. Introduction Logic gates are connected together to produce a specified output for certain specified combinations of input

More information

A B AB CD Objectives:

A B AB CD Objectives: Objectives:. Four variables maps. 2. Simplification using prime implicants. 3. "on t care" conditions. 4. Summary.. Four variables Karnaugh maps Minterms A A m m m3 m2 A B C m4 C A B C m2 m8 C C m5 C m3

More information

Larger K-maps. So far we have only discussed 2 and 3-variable K-maps. We can now create a 4-variable map in the

Larger K-maps. So far we have only discussed 2 and 3-variable K-maps. We can now create a 4-variable map in the EET 3 Chapter 3 7/3/2 PAGE - 23 Larger K-maps The -variable K-map So ar we have only discussed 2 and 3-variable K-maps. We can now create a -variable map in the same way that we created the 3-variable

More information

Synthesis of 2-level Logic Heuristic Method. Two Approaches

Synthesis of 2-level Logic Heuristic Method. Two Approaches Synthesis of 2-level Logic Heuristic Method Lecture 8 Exact Two Approaches Find all primes Find a complete sum Find a minimum cover (covering problem) Heuristic Take an initial cover of cubes Repeat Expand

More information

Switching Circuits & Logic Design

Switching Circuits & Logic Design Switching Circuits & Logic Design Jie-Hong Roland Jiang 江介宏 Department of Electrical Engineering National Taiwan University Fall 23 5 Karnaugh Maps K-map Walks and Gray Codes http://asicdigitaldesign.wordpress.com/28/9/26/k-maps-walks-and-gray-codes/

More information

Combinational Logic Circuits

Combinational Logic Circuits Chapter 3 Combinational Logic Circuits 12 Hours 24 Marks 3.1 Standard representation for logical functions Boolean expressions / logic expressions / logical functions are expressed in terms of logical

More information

Chapter 3 Simplification of Boolean functions

Chapter 3 Simplification of Boolean functions 3.1 Introduction Chapter 3 Simplification of Boolean functions In this chapter, we are going to discuss several methods for simplifying the Boolean function. What is the need for simplifying the Boolean

More information

TWO-LEVEL COMBINATIONAL LOGIC

TWO-LEVEL COMBINATIONAL LOGIC TWO-LEVEL COMBINATIONAL LOGIC OVERVIEW Canonical forms To-level simplification Boolean cubes Karnaugh maps Quine-McClusky (Tabulation) Method Don't care terms Canonical and Standard Forms Minterms and

More information

Slide Set 5. for ENEL 353 Fall Steve Norman, PhD, PEng. Electrical & Computer Engineering Schulich School of Engineering University of Calgary

Slide Set 5. for ENEL 353 Fall Steve Norman, PhD, PEng. Electrical & Computer Engineering Schulich School of Engineering University of Calgary Slide Set 5 for ENEL 353 Fall 207 Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary Fall Term, 207 SN s ENEL 353 Fall 207 Slide Set 5 slide

More information

CS8803: Advanced Digital Design for Embedded Hardware

CS8803: Advanced Digital Design for Embedded Hardware CS883: Advanced Digital Design for Embedded Hardware Lecture 2: Boolean Algebra, Gate Network, and Combinational Blocks Instructor: Sung Kyu Lim (limsk@ece.gatech.edu) Website: http://users.ece.gatech.edu/limsk/course/cs883

More information

Advanced Digital Logic Design EECS 303

Advanced Digital Logic Design EECS 303 Advanced Digital Logic Design EECS 303 http://ziyang.eecs.northwestern.edu/eecs303/ Teacher: Robert Dick Office: L477 Tech Email: dickrp@northwestern.edu Phone: 847 467 2298 Outline 1. 2. 2 Robert Dick

More information

Two-Level Logic Optimization ( Introduction to Computer-Aided Design) School of EECS Seoul National University

Two-Level Logic Optimization ( Introduction to Computer-Aided Design) School of EECS Seoul National University Two-Level Logic Optimization (4541.554 Introduction to Computer-Aided Design) School of EECS Seoul National University Minimization of Two-Level Functions Goals: Minimize cover cardinality Minimize number

More information

EECS 219C: Formal Methods Binary Decision Diagrams (BDDs) Sanjit A. Seshia EECS, UC Berkeley

EECS 219C: Formal Methods Binary Decision Diagrams (BDDs) Sanjit A. Seshia EECS, UC Berkeley EECS 219C: Formal Methods Binary Decision Diagrams (BDDs) Sanjit A. Seshia EECS, UC Berkeley Boolean Function Representations Syntactic: e.g.: CNF, DNF (SOP), Circuit Semantic: e.g.: Truth table, Binary

More information

Contents. Chapter 3 Combinational Circuits Page 1 of 34

Contents. Chapter 3 Combinational Circuits Page 1 of 34 Chapter 3 Combinational Circuits Page of 34 Contents Contents... 3 Combinational Circuits... 2 3. Analysis of Combinational Circuits... 2 3.. Using a Truth Table... 2 3..2 Using a Boolean unction... 4

More information

Combinational Logic Circuits Part III -Theoretical Foundations

Combinational Logic Circuits Part III -Theoretical Foundations Combinational Logic Circuits Part III -Theoretical Foundations Overview Simplifying Boolean Functions Algebraic Manipulation Karnaugh Map Manipulation (simplifying functions of 2, 3, 4 variables) Systematic

More information

Giovanni De Micheli. Integrated Systems Centre EPF Lausanne

Giovanni De Micheli. Integrated Systems Centre EPF Lausanne Two-level Logic Synthesis and Optimization Giovanni De Micheli Integrated Systems Centre EPF Lausanne This presentation can be used for non-commercial purposes as long as this note and the copyright footers

More information

Combinational Logic & Circuits

Combinational Logic & Circuits Week-I Combinational Logic & Circuits Spring' 232 - Logic Design Page Overview Binary logic operations and gates Switching algebra Algebraic Minimization Standard forms Karnaugh Map Minimization Other

More information

Simplification of Boolean Functions

Simplification of Boolean Functions COM111 Introduction to Computer Engineering (Fall 2006-2007) NOTES 5 -- page 1 of 5 Introduction Simplification of Boolean Functions You already know one method for simplifying Boolean expressions: Boolean

More information

Chapter 2 Combinational Logic Circuits

Chapter 2 Combinational Logic Circuits Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Overview Part Gate Circuits and Boolean Equations Binary Logic and Gates Boolean Algebra Standard

More information

Unit-IV Boolean Algebra

Unit-IV Boolean Algebra Unit-IV Boolean Algebra Boolean Algebra Chapter: 08 Truth table: Truth table is a table, which represents all the possible values of logical variables/statements along with all the possible results of

More information

ICS 252 Introduction to Computer Design

ICS 252 Introduction to Computer Design ICS 252 Introduction to Computer Design Logic Optimization Eli Bozorgzadeh Computer Science Department-UCI Hardware compilation flow HDL RTL Synthesis netlist Logic synthesis library netlist Physical design

More information

Outcomes. Unit 9. Logic Function Synthesis KARNAUGH MAPS. Implementing Combinational Functions with Karnaugh Maps

Outcomes. Unit 9. Logic Function Synthesis KARNAUGH MAPS. Implementing Combinational Functions with Karnaugh Maps .. Outcomes Unit I can use Karnaugh maps to synthesize combinational functions with several outputs I can determine the appropriate size and contents of a memory to implement any logic function (i.e. truth

More information

Logic Synthesis and Verification

Logic Synthesis and Verification Logic Synthesis and Verification Jie-Hong Roland Jiang 江介宏 Department of Electrical Engineering National Taiwan University Fall 2012 1 SOPs and Incompletely Specified Functions Reading: Logic Synthesis

More information

Gate Level Minimization

Gate Level Minimization Gate Level Minimization By Dr. M. Hebaishy Digital Logic Design Ch- Simplifying Boolean Equations Example : Y = AB + AB Example 2: = B (A + A) T8 = B () T5 = B T Y = A(AB + ABC) = A (AB ( + C ) ) T8 =

More information

Combinational Logic Circuits

Combinational Logic Circuits Chapter 2 Combinational Logic Circuits J.J. Shann (Slightly trimmed by C.P. Chung) Chapter Overview 2-1 Binary Logic and Gates 2-2 Boolean Algebra 2-3 Standard Forms 2-4 Two-Level Circuit Optimization

More information

2.6 BOOLEAN FUNCTIONS

2.6 BOOLEAN FUNCTIONS 2.6 BOOLEAN FUNCTIONS Binary variables have two values, either 0 or 1. A Boolean function is an expression formed with binary variables, the two binary operators AND and OR, one unary operator NOT, parentheses

More information

Gate Level Minimization Map Method

Gate Level Minimization Map Method Gate Level Minimization Map Method Complexity of hardware implementation is directly related to the complexity of the algebraic expression Truth table representation of a function is unique Algebraically

More information

CSE241 VLSI Digital Circuits UC San Diego

CSE241 VLSI Digital Circuits UC San Diego CSE241 VLSI Digital Circuits UC San Diego Winter 2003 Lecture 05: Logic Synthesis Cho Moon Cadence Design Systems January 21, 2003 CSE241 L5 Synthesis.1 Kahng & Cichy, UCSD 2003 Outline Introduction Two-level

More information

ECE 5745 Complex Digital ASIC Design Topic 12: Synthesis Algorithms

ECE 5745 Complex Digital ASIC Design Topic 12: Synthesis Algorithms ECE 5745 Complex Digital ASIC Design Topic 12: Synthesis Algorithms Christopher Batten School of Electrical and Computer Engineering Cornell University http://www.csl.cornell.edu/courses/ece5745 RTL to

More information

User s Manual. Ronwaldo A. Collado Diosdado Y. Tejoso Jr. CMSC 130 Logistic Design and Digital Computer Circuits Second Semester, A. Y.

User s Manual. Ronwaldo A. Collado Diosdado Y. Tejoso Jr. CMSC 130 Logistic Design and Digital Computer Circuits Second Semester, A. Y. The Quine-McCluskey Method, also known as the Tabulation Method is a specific step-by-step method that is ensured to generate a simplified standard-form expression for a function. Ronwaldo A. Collado Diosdado

More information

UNIT II. Circuit minimization

UNIT II. Circuit minimization UNIT II Circuit minimization The complexity of the digital logic gates that implement a Boolean function is directly related to the complexity of the algebraic expression from which the function is implemented.

More information

Chapter 3. Gate-Level Minimization. Outlines

Chapter 3. Gate-Level Minimization. Outlines Chapter 3 Gate-Level Minimization Introduction The Map Method Four-Variable Map Five-Variable Map Outlines Product of Sums Simplification Don t-care Conditions NAND and NOR Implementation Other Two-Level

More information

DKT 122/3 DIGITAL SYSTEM 1

DKT 122/3 DIGITAL SYSTEM 1 Company LOGO DKT 122/3 DIGITAL SYSTEM 1 BOOLEAN ALGEBRA (PART 2) Boolean Algebra Contents Boolean Operations & Expression Laws & Rules of Boolean algebra DeMorgan s Theorems Boolean analysis of logic circuits

More information

Binary Decision Diagrams (BDD)

Binary Decision Diagrams (BDD) Binary Decision Diagrams (BDD) Contents Motivation for Decision diagrams Binary Decision Diagrams ROBDD Effect of Variable Ordering on BDD size BDD operations Encoding state machines Reachability Analysis

More information

ECE 5775 (Fall 17) High-Level Digital Design Automation. Binary Decision Diagrams Static Timing Analysis

ECE 5775 (Fall 17) High-Level Digital Design Automation. Binary Decision Diagrams Static Timing Analysis ECE 5775 (Fall 17) High-Level Digital Design Automation Binary Decision Diagrams Static Timing Analysis Announcements Start early on Lab 1 (CORDIC design) Fixed-point design should not have usage of DSP48s

More information

ECE260B CSE241A Winter Logic Synthesis

ECE260B CSE241A Winter Logic Synthesis ECE260B CSE241A Winter 2007 Logic Synthesis Website: /courses/ece260b-w07 ECE 260B CSE 241A Static Timing Analysis 1 Slides courtesy of Dr. Cho Moon Introduction Why logic synthesis? Ubiquitous used almost

More information

Points Addressed in this Lecture. Standard form of Boolean Expressions. Lecture 4: Logic Simplication & Karnaugh Map

Points Addressed in this Lecture. Standard form of Boolean Expressions. Lecture 4: Logic Simplication & Karnaugh Map Points Addressed in this Lecture Lecture 4: Logic Simplication & Karnaugh Map Professor Peter Cheung Department of EEE, Imperial College London Standard form of Boolean Expressions Sum-of-Products (SOP),

More information

IT 201 Digital System Design Module II Notes

IT 201 Digital System Design Module II Notes IT 201 Digital System Design Module II Notes BOOLEAN OPERATIONS AND EXPRESSIONS Variable, complement, and literal are terms used in Boolean algebra. A variable is a symbol used to represent a logical quantity.

More information

ESE535: Electronic Design Automation. Today. EDA Use. Problem PLA. Programmable Logic Arrays (PLAs) Two-Level Logic Optimization

ESE535: Electronic Design Automation. Today. EDA Use. Problem PLA. Programmable Logic Arrays (PLAs) Two-Level Logic Optimization ESE535: Electronic Design Automation Day 18: March 25, 2013 Two-Level Logic-Synthesis Today Two-Level Logic Optimization Problem Behavioral (C, MATLAB, ) Arch. Select Schedule RTL FSM assign Definitions

More information

CMPE223/CMSE222 Digital Logic

CMPE223/CMSE222 Digital Logic CMPE223/CMSE222 Digital Logic Optimized Implementation of Logic Functions: Strategy for Minimization, Minimum Product-of-Sums Forms, Incompletely Specified Functions Terminology For a given term, each

More information

Literal Cost F = BD + A B C + A C D F = BD + A B C + A BD + AB C F = (A + B)(A + D)(B + C + D )( B + C + D) L = 10

Literal Cost F = BD + A B C + A C D F = BD + A B C + A BD + AB C F = (A + B)(A + D)(B + C + D )( B + C + D) L = 10 Circuit Optimization Goal: To obtain the simplest implementation for a given function Optimization is a more formal approach to simplification that is performed using a specific procedure or algorithm

More information

Assignment (3-6) Boolean Algebra and Logic Simplification - General Questions

Assignment (3-6) Boolean Algebra and Logic Simplification - General Questions Assignment (3-6) Boolean Algebra and Logic Simplification - General Questions 1. Convert the following SOP expression to an equivalent POS expression. 2. Determine the values of A, B, C, and D that make

More information

4 KARNAUGH MAP MINIMIZATION

4 KARNAUGH MAP MINIMIZATION 4 KARNAUGH MAP MINIMIZATION A Karnaugh map provides a systematic method for simplifying Boolean expressions and, if properly used, will produce the simplest SOP or POS expression possible, known as the

More information

University of Technology

University of Technology University of Technology Lecturer: Dr. Sinan Majid Course Title: microprocessors 4 th year Lecture 5 & 6 Minimization with Karnaugh Maps Karnaugh maps lternate way of representing oolean function ll rows

More information

ECE380 Digital Logic

ECE380 Digital Logic ECE38 Digital Logic Optimized Implementation of Logic Functions: Strategy for Minimization, Minimum Product-of-Sums Forms, Incompletely Specified Functions Dr. D. J. Jackson Lecture 8- Terminology For

More information

ELCT201: DIGITAL LOGIC DESIGN

ELCT201: DIGITAL LOGIC DESIGN ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 3 Following the slides of Dr. Ahmed H. Madian ذو الحجة 1438 ه Winter

More information

Chapter 2 Combinational

Chapter 2 Combinational Computer Engineering 1 (ECE290) Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization HOANG Trang 2008 Pearson Education, Inc. Overview Part 1 Gate Circuits and Boolean Equations Binary Logic

More information

Department of Electrical and Computer Engineering University of Wisconsin - Madison. ECE/CS 352 Digital System Fundamentals.

Department of Electrical and Computer Engineering University of Wisconsin - Madison. ECE/CS 352 Digital System Fundamentals. Department of Electrical and Computer Engineering University of Wisconsin - Madison ECE/C 352 Digital ystem Fundamentals Quiz #2 Thursday, March 7, 22, 7:15--8:3PM 1. (15 points) (a) (5 points) NAND, NOR

More information

Chapter 2. Boolean Expressions:

Chapter 2. Boolean Expressions: Chapter 2 Boolean Expressions: A Boolean expression or a function is an expression which consists of binary variables joined by the Boolean connectives AND and OR along with NOT operation. Any Boolean

More information

Design of Framework for Logic Synthesis Engine

Design of Framework for Logic Synthesis Engine Design of Framework for Logic Synthesis Engine Tribikram Pradhan 1, Pramod Kumar 2, Anil N S 3, Amit Bakshi 4 1 School of Information technology and Engineering, VIT University, Vellore 632014, Tamilnadu,

More information

Combinational Circuits Digital Logic (Materials taken primarily from:

Combinational Circuits Digital Logic (Materials taken primarily from: Combinational Circuits Digital Logic (Materials taken primarily from: http://www.facstaff.bucknell.edu/mastascu/elessonshtml/eeindex.html http://www.cs.princeton.edu/~cos126 ) Digital Systems What is a

More information

Gate-Level Minimization. BME208 Logic Circuits Yalçın İŞLER

Gate-Level Minimization. BME208 Logic Circuits Yalçın İŞLER Gate-Level Minimization BME28 Logic Circuits Yalçın İŞLER islerya@yahoo.com http://me.islerya.com Complexity of Digital Circuits Directly related to the complexity of the algebraic expression we use to

More information

Switching Theory And Logic Design UNIT-II GATE LEVEL MINIMIZATION

Switching Theory And Logic Design UNIT-II GATE LEVEL MINIMIZATION Switching Theory And Logic Design UNIT-II GATE LEVEL MINIMIZATION Two-variable k-map: A two-variable k-map can have 2 2 =4 possible combinations of the input variables A and B. Each of these combinations,

More information

Gate-Level Minimization

Gate-Level Minimization Gate-Level Minimization ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2017 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines The Map Method

More information

Chapter 2 Combinational Logic Circuits

Chapter 2 Combinational Logic Circuits Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Charles Kime & Thomas Kaminski 2008 Pearson Education, Inc. (Hyperlinks are active in View Show

More information

SEE1223: Digital Electronics

SEE1223: Digital Electronics SEE223: Digital Electronics 3 Combinational Logic Design Zulkifil Md Yusof Dept. of Microelectronics and Computer Engineering The aculty of Electrical Engineering Universiti Teknologi Malaysia Karnaugh

More information

Digital Design. Chapter 4. Principles Of. Simplification of Boolean Functions

Digital Design. Chapter 4. Principles Of. Simplification of Boolean Functions Principles Of Digital Design Chapter 4 Simplification of Boolean Functions Karnaugh Maps Don t Care Conditions Technology Mapping Optimization, Conversions, Decomposing, Retiming Boolean Cubes for n =,

More information

ECE260B CSE241A Winter Logic Synthesis

ECE260B CSE241A Winter Logic Synthesis ECE260B CSE241A Winter 2005 Logic Synthesis Website: / courses/ ece260bw05 ECE 260B CSE 241A Static Timing Analysis 1 Slides courtesy of Dr. Cho Moon Introduction Why logic synthesis? Ubiquitous used almost

More information

DIGITAL TECHNICS. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute 2. LECTURE: LOGIC NETWORK MINIMIZATION 2016/2017

DIGITAL TECHNICS. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute 2. LECTURE: LOGIC NETWORK MINIMIZATION 2016/2017 27.2.2. DIGITAL TECHNICS Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 2. LECTURE: LOGIC NETWORK MINIMIZATION 26/27 2. LECTURE: CONTENTS. Canonical forms of Boolean functions

More information

2.1 Binary Logic and Gates

2.1 Binary Logic and Gates 1 EED2003 Digital Design Presentation 2: Boolean Algebra Asst. Prof.Dr. Ahmet ÖZKURT Asst. Prof.Dr Hakkı T. YALAZAN Based on the Lecture Notes by Jaeyoung Choi choi@comp.ssu.ac.kr Fall 2000 2.1 Binary

More information

Graduate Institute of Electronics Engineering, NTU. CH5 Karnaugh Maps. Lecturer: 吳安宇教授 Date:2006/10/20 ACCESS IC LAB

Graduate Institute of Electronics Engineering, NTU. CH5 Karnaugh Maps. Lecturer: 吳安宇教授 Date:2006/10/20 ACCESS IC LAB CH5 Karnaugh Maps Lecturer: 吳安宇教授 Date:2006/0/20 CCESS IC L Problems in lgebraic Simplification The procedures are difficult to apply in a systematic way. It is difficult to tell when you have arrived

More information

CS470: Computer Architecture. AMD Quad Core

CS470: Computer Architecture. AMD Quad Core CS470: Computer Architecture Yashwant K. Malaiya, Professor malaiya@cs.colostate.edu AMD Quad Core 1 Architecture Layers Building blocks Gates, flip-flops Functional bocks: Combinational, Sequential Instruction

More information

ELCT201: DIGITAL LOGIC DESIGN

ELCT201: DIGITAL LOGIC DESIGN ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 3 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter

More information

Binary recursion. Unate functions. If a cover C(f) is unate in xj, x, then f is unate in xj. x

Binary recursion. Unate functions. If a cover C(f) is unate in xj, x, then f is unate in xj. x Binary recursion Unate unctions! Theorem I a cover C() is unate in,, then is unate in.! Theorem I is unate in,, then every prime implicant o is unate in. Why are unate unctions so special?! Special Boolean

More information

(Refer Slide Time 6:48)

(Refer Slide Time 6:48) Digital Circuits and Systems Prof. S. Srinivasan Department of Electrical Engineering Indian Institute of Technology Madras Lecture - 8 Karnaugh Map Minimization using Maxterms We have been taking about

More information

UNIT-4 BOOLEAN LOGIC. NOT Operator Operates on single variable. It gives the complement value of variable.

UNIT-4 BOOLEAN LOGIC. NOT Operator Operates on single variable. It gives the complement value of variable. UNIT-4 BOOLEAN LOGIC Boolean algebra is an algebra that deals with Boolean values((true and FALSE). Everyday we have to make logic decisions: Should I carry the book or not?, Should I watch TV or not?

More information

Summary. Boolean Addition

Summary. Boolean Addition Summary Boolean Addition In Boolean algebra, a variable is a symbol used to represent an action, a condition, or data. A single variable can only have a value of or 0. The complement represents the inverse

More information

Gate-Level Minimization

Gate-Level Minimization MEC520 디지털공학 Gate-Level Minimization Jee-Hwan Ryu School of Mechanical Engineering Gate-Level Minimization-The Map Method Truth table is unique Many different algebraic expression Boolean expressions may

More information

Motivation. CS389L: Automated Logical Reasoning. Lecture 5: Binary Decision Diagrams. Historical Context. Binary Decision Trees

Motivation. CS389L: Automated Logical Reasoning. Lecture 5: Binary Decision Diagrams. Historical Context. Binary Decision Trees Motivation CS389L: Automated Logical Reasoning Lecture 5: Binary Decision Diagrams Işıl Dillig Previous lectures: How to determine satisfiability of propositional formulas Sometimes need to efficiently

More information

LSN 4 Boolean Algebra & Logic Simplification. ECT 224 Digital Computer Fundamentals. Department of Engineering Technology

LSN 4 Boolean Algebra & Logic Simplification. ECT 224 Digital Computer Fundamentals. Department of Engineering Technology LSN 4 Boolean Algebra & Logic Simplification Department of Engineering Technology LSN 4 Key Terms Variable: a symbol used to represent a logic quantity Compliment: the inverse of a variable Literal: a

More information

Experiment 3: Logic Simplification

Experiment 3: Logic Simplification Module: Logic Design Name:... University no:.. Group no:. Lab Partner Name: Mr. Mohamed El-Saied Experiment : Logic Simplification Objective: How to implement and verify the operation of the logical functions

More information

A graphical method of simplifying logic

A graphical method of simplifying logic 4-5 Karnaugh Map Method A graphical method of simplifying logic equations or truth tables. Also called a K map. Theoretically can be used for any number of input variables, but practically limited to 5

More information

ON AN OPTIMIZATION TECHNIQUE USING BINARY DECISION DIAGRAM

ON AN OPTIMIZATION TECHNIQUE USING BINARY DECISION DIAGRAM ON AN OPTIMIZATION TECHNIQUE USING BINARY DECISION DIAGRAM Debajit Sensarma # 1, Subhashis Banerjee #1, Krishnendu Basuli #1,Saptarshi Naskar #2, Samar Sen Sarma #3 #1 West Bengal State University, West

More information

Digital Logic Design. Outline

Digital Logic Design. Outline Digital Logic Design Gate-Level Minimization CSE32 Fall 2 Outline The Map Method 2,3,4 variable maps 5 and 6 variable maps (very briefly) Product of sums simplification Don t Care conditions NAND and NOR

More information

Karnaugh Maps. Kiril Solovey. Tel-Aviv University, Israel. April 8, Kiril Solovey (TAU) Karnaugh Maps April 8, / 22

Karnaugh Maps. Kiril Solovey. Tel-Aviv University, Israel. April 8, Kiril Solovey (TAU) Karnaugh Maps April 8, / 22 Karnaugh Maps Kiril Solovey Tel-Aviv University, Israel April 8, 2013 Kiril Solovey (TAU) Karnaugh Maps April 8, 2013 1 / 22 Reminder: Canonical Representation Sum of Products Function described for the

More information

CprE 281: Digital Logic

CprE 281: Digital Logic CprE 28: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Minimization CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev Administrative

More information

BCNF. Yufei Tao. Department of Computer Science and Engineering Chinese University of Hong Kong BCNF

BCNF. Yufei Tao. Department of Computer Science and Engineering Chinese University of Hong Kong BCNF Yufei Tao Department of Computer Science and Engineering Chinese University of Hong Kong Recall A primary goal of database design is to decide what tables to create. Usually, there are two principles:

More information

10EC33: DIGITAL ELECTRONICS QUESTION BANK

10EC33: DIGITAL ELECTRONICS QUESTION BANK 10EC33: DIGITAL ELECTRONICS Faculty: Dr.Bajarangbali E Examination QuestionS QUESTION BANK 1. Discuss canonical & standard forms of Boolean functions with an example. 2. Convert the following Boolean function

More information

9/10/2016. ECE 120: Introduction to Computing. The Domain of a Boolean Function is a Hypercube. List All Implicants for One Variable A

9/10/2016. ECE 120: Introduction to Computing. The Domain of a Boolean Function is a Hypercube. List All Implicants for One Variable A University of Illinois at Urbana-Champaign Dept. of Electrical and Computer Engineering ECE 120: Introduction to Computing To Simplify, Write Function as a Sum of Prime Implicants One way to simplify a

More information

Gate-Level Minimization. section instructor: Ufuk Çelikcan

Gate-Level Minimization. section instructor: Ufuk Çelikcan Gate-Level Minimization section instructor: Ufuk Çelikcan Compleity of Digital Circuits Directly related to the compleity of the algebraic epression we use to build the circuit. Truth table may lead to

More information

Slides for Lecture 15

Slides for Lecture 15 Slides for Lecture 5 ENEL 353: Digital Circuits Fall 203 Term Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary October, 203 ENEL 353 F3 Section

More information

Switching Circuits Simplifications Using Binary Coded Octal Minterms

Switching Circuits Simplifications Using Binary Coded Octal Minterms Vol. 2, No. 2, pp. 45-51, 2017 OI: http://ijoaem.org/00202-04 Switching Circuits Simplifications Using Binary Coded Octal Minterms Sahadev Roy Abstract In this paper, a simple approach for detection of

More information

2008 The McGraw-Hill Companies, Inc. All rights reserved.

2008 The McGraw-Hill Companies, Inc. All rights reserved. 28 The McGraw-Hill Companies, Inc. All rights reserved. 28 The McGraw-Hill Companies, Inc. All rights reserved. All or Nothing Gate Boolean Expression: A B = Y Truth Table (ee next slide) or AB = Y 28

More information

Definitions. 03 Logic networks Boolean algebra. Boolean set: B 0,

Definitions. 03 Logic networks Boolean algebra. Boolean set: B 0, 3. Boolean algebra 3 Logic networks 3. Boolean algebra Definitions Boolean functions Properties Canonical forms Synthesis and minimization alessandro bogliolo isti information science and technology institute

More information

Experiment 4 Boolean Functions Implementation

Experiment 4 Boolean Functions Implementation Experiment 4 Boolean Functions Implementation Introduction: Generally you will find that the basic logic functions AND, OR, NAND, NOR, and NOT are not sufficient to implement complex digital logic functions.

More information

COPYRIGHTED MATERIAL INDEX

COPYRIGHTED MATERIAL INDEX INDEX Absorption law, 31, 38 Acyclic graph, 35 tree, 36 Addition operators, in VHDL (VHSIC hardware description language), 192 Algebraic division, 105 AND gate, 48 49 Antisymmetric, 34 Applicable input

More information

Combinational hazards

Combinational hazards Combinational hazards We break down combinational hazards into two major categories, logic hazards and function hazards. A logic hazard is characterized by the fact that it can be eliminated by proper

More information

Gate-Level Minimization

Gate-Level Minimization Gate-Level Minimization ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2011 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines The Map Method

More information

1. Mark the correct statement(s)

1. Mark the correct statement(s) 1. Mark the correct statement(s) 1.1 A theorem in Boolean algebra: a) Can easily be proved by e.g. logic induction b) Is a logical statement that is assumed to be true, c) Can be contradicted by another

More information

Software Implementation of Break-Up Algorithm for Logic Minimization

Software Implementation of Break-Up Algorithm for Logic Minimization vol. 2, no. 6. 2, pp. 141-145, 2017 DOI: https://doi.org/10.24999/ijoaem/02060034 Software Implementation of Break-Up Algorithm for Logic Minimization Koustuvmoni Bharadwaj and Sahadev Roy Abstract In

More information