An Innovative Simulation Workflow for Debugging High-Speed Digital Designs using Jitter Separation

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1 An Innovative Simulation Workflow for Debugging High-Speed Digital Designs using Jitter Separation C. Chastang, A. Amédéo V. Poisson, P. Grison, F. Demuynck C. Gautier, F. Costa Thales Communications & Security Agilent Technologie EEsof EDA SATiE CNRS, ENS Cachan SPI th IEEE Workshop on Signal and Power Integrity Paris

2 2 / Introduction What is jitter separation? Presentation of the test case Simulation settings Comparison simulations vs measurements Conclusion

3 3 / Introduction What is jitter separation? Presentation of the test case Simulation settings Comparison simulations vs measurements Conclusion

4 4 / Introduction Complex designs become more and more difficult to handle A4 size board HD Components 4000 components 50 BGA (1500 pins) HD Interconnections 4000 Nets 14 layers µvias (3+X+3) Etching 120µm Increase of frequency: DDR2 / LVDS : 400MHz Gigabit Ethernet Links High-Speed Links 3,125Gb/s 1 cm A lot of voltage levels Decrease voltage magin 1.2V / 1.8V / 2.5V / 3.3V / More and more enhanced features embedded in the digital boards Miniaturization of the products High-Speed serial links enable to continue to increase the performance and the miniaturization of the digital board.

5 5 / Introduction Multi-gigabits links help to exchange a large amount of information on a small area. Some famous multi-gigabit protocols: PCI express: from 2,5 to 8 Gbps SATA: from 1,5 to 6 Gbps 10GBASE-KR: Gbps Multi-gigabit links vs Parallel Buses: Protocol Requested area Max data rate Efficiency AGP 8x 512w 2 GB/s 4 MB/s/w PCIe x 224w 32 GB/s 143 MB/s/w PCIe 3.0 is x35 more efficient than AGP! HSD links transmit much more data than parallel buses on the same area

6 6 / Introduction HSD links make easier to route the board thanks to lower density but: Use of HSD links requires severe design constraints due to the increase of: Losses Reflections Crosstalk Knowledge in many fields is required to handle HSD designs: Digital electronic High-Frequency Signal processing Materials & Thermal SI analysis becomes a new full-time job.

7 7 / Introduction Goals of the study Ensure that multi-gigabit links will work at the first use of the electronic board. Find a powerful simulation workflow to quickly identify the cause of signal integrity degradation thanks to Jitter separation. Choose the simulation tools Compare EM softwares and find the optimal settings of each test case Correctly setup the circuit simulator taking into account IBIS AMI models Find the right balance between computational time vs accuracy Validate the workflow thanks to measurements

8 8 / Introduction Simulation workflow with IBIS AMI models Geometry Import S Parameters extraction PCB/EDA software Electromagnetic Solver S Parameters Results S Parameters (Black box) Circuit co-simulation with IBIS AMI models Eye Diagram, BER, Jitter

9 9 / Introduction Difficult topics to solve EM Simulations: Setup an accurate model Behaviour of the frequency dependant FR4 Complexity of the EM model, number and size of the objects (µvias, pads, ) Time needed to set up the EM model and calculate S parameters Circuit Simulations HSPICE model: time consuming, do not consider complex digital circuit (CDR, ) IBIS AMI model: very fast (10 6 bits/mn), presence of CDR, EQ circuits but: Unable to mix IBIS AMI models with HSPICE and classic IBIS models Unable to take into account the PDN for SSN simulations The accuracy of the simulation can be validated thanks to measurements + jitter separation.

10 10 / Introduction What is jitter separation? Presentation of the test case Simulation settings Comparison simulations vs measurements Conclusion

11 11 / What is Jitter Separation? Jitter Separation theory Jitter is the undesired deviation from true periodicity of an assumed periodic signal. Jitter Separation (based on algorithms continuously improved) Power supply noise Crosstalk Lossy media Discontinuities Quantify each jitter element = quickly identify the sources of the signal degradation.

12 12 / Introduction What is jitter separation? Presentation of the test case Simulation settings Comparison simulations vs measurements Conclusion

13 13 / Presentation of the test case Why this test case? Models not available, unusual routing, diff pair + single-ended coupling, We must be able to detect the signal integrity problems using simulations. Differential pair MGH_DIA Length: 190 mm Width of the trace: w=130 µm Spacing between P & N channels: s=150 µm Single-ended SSN_SIGA Length: 160 mm Width of the trace: w=130 µm Embedded microstrip on layers 2 & 3 Embedded microstrip on layers 2 & 3 Stratix II GX Coupling length: 7 cm Plated Through Holes

14 14 / Presentation of the test case Test case Spacing between MGH_DIA2_P and SSN_SIGA_79: 120 µm (< s) MGH_DIA2_P between 2 power planes (VCCH et VCCINT) TOP 225 µm 150 µm 80 µm 250 µm Cut view SSN_SIGA_61 SSN_SIGA_79 SSN_SIGA_72 SSN_SIGA_79 MGH_DIA2_P MGH_DIA2_N Top view

15 15 / Introduction What is jitter separation? Presentation of the test case Simulation settings Comparison simulations vs measurements Conclusion

16 16 / Simulation settings S Parameters extraction with Agilent s Momentum Momentum EM model Simplified stack-up Settings: Bandwidth range: DC 10 GHz (meshing at 5 GHz) RF mode Thales Communications

17 17 / Simulation settings S Parameters extraction with Agilent s Momentum Coupling between MGH_DIA2_P and SSN_SIGA_79 NEXT (3D FEM) NEXT (Hybrid) FEXT (Hybrid) FEXT (3D FEM) Momentum gives better eye diagram compared to measurement than hybrid solvers. Hybrid solvers are not able to correctly take into account this topology.

18 18 / Simulation settings Circuit simulation setup with Agilent s ADS IBIS AMI model of Stratix II GX is not available Generic IBIS AMI models available in ADS library are used. Addition of the Stratix IV packages at the generic IBIS AMI output (*.s4p). Ability to mix IBIS AMI and IBIS models By using generic IBIS AMI models By modifying the IBIS netlist 10 6 simulated bits Circuit simulation setting done in about 30 minutes.

19 19 / Introduction What is jitter separation? Presentation of the test case Simulation settings Comparison simulations vs measurements Conclusion

20 20 / Comparison simulations vs measurements MGH_DIA2 without single-ended aggressor (MGH_DIA1 active) Data rate: 1 Gbps Pattern: PRBS7 VOD: 800 mv Jitter Separation processed with Agilent s Infiniiview Simulation Measurement Agilent DSA-X 93204A 33 GHz Crosstalk due to MGH_DIA1 RJ is abnormally high -> the setting of the SERDES clock is wrong Despite the inability of simulating the PJ, the correlation is quite good.

21 21 / Comparison simulations vs measurements MGH_DIA2 with SSN_SIGA_79 at 50 MHz (MGH_DIA1 active) Data rate: 1 Gbps Pattern: PRBS7 VOD: 800 mv Jitter Separation processed with Agilent s Infiniiview Simulation Measurement Agilent DSA-X 93204A 33 GHz The BUJ has tremendously increased due to SSN_SIGA_79 crosstalk Good correlation between simulations and measurements.

22 22 / Comparison simulations vs measurements Synthesis The jitter separation is a very powerful tool: with only 1 simulation or 1 measurement per multi-gigabit link, we are able to: Find the source of the signal integrity degradation. Define a suitable solution in order to improve signal and power integrity. This study enabled to: Implement a complete simulation workflow Mix IBIS and IBIS AMI models Correlate simulations and measurements Reach the limitations of the IBIS AMI standard (Power Distribution Network) Jitter separation and IBIS AMI standard have to continue to be improved.

23 23 / Introduction What is jitter separation? Presentation of the test case Simulation settings Comparison simulations vs measurements Conclusion

24 24 / Classic simulation workflow without jitter separation Update Allegro BRD Potential aggressors Momentum ADS (1 eye diagram per HSD Link) - No aggressor - No pre-emphasis / no equalization OK Virtual compliance + margins NOK Crosstalk Pre-emphasis / Equalization NOK Virtual compliance + margins OK Virtual compliance + margins OK Design OK NOK PI problems of HSD links are not taken into account in this simulation workflow.

25 25 / New simulation workflow with jitter separation BRD Allegro Potential Aggressors Momentum Problem identified Solution without modification of routing Solution with modification of routing S Parameters ADS - Crosstalk - Power Distribution Network - (Pre-emphasis / Equalization) NOK Update Virtual compliance + margins NOK OK Infiniiview (Jitter Separation) Identify Signal Integrity Problems Design OK RJ PJ ISI BUJ Verify the declaration of the clock Modify the PDN (value of the capacitors) Add pre-emphasis or equalization Increase the rise time or decrease the frequency of the signal Change the component Modify the PDN (plane, location of the capacitors) Optimize the channel (traces, vias, stubs, connectors, ) Isolate the traces (spacing, plane, gnd vias, ) This new simulation workflow is simpler.

26 26 / Conclusion Conclusion Agilent Technologies offers a complete simulation workflow from EM simulation to jitter separation to quickly identify the source of the signal degradation. Future work Follow the evolution of the IBIS AMI standard Effect of the power distribution network on the multi-gigabit links? Continue to improve design rules and methodology. Establish a method to find precisely the location of the signal or power integrity problems on the electronic board. Improve jitter separation algorithmes in presence of coding and equalization. Validate the simulation tools for data rate > 20 Gbps

27 27 / Thank you for your attention

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