An Innovative Simulation Workflow for Debugging High-Speed Digital Designs using Jitter Separation
|
|
- Darren Allison
- 5 years ago
- Views:
Transcription
1 An Innovative Simulation Workflow for Debugging High-Speed Digital Designs using Jitter Separation C. Chastang, A. Amédéo V. Poisson, P. Grison, F. Demuynck C. Gautier, F. Costa Thales Communications & Security Agilent Technologie EEsof EDA SATiE CNRS, ENS Cachan SPI th IEEE Workshop on Signal and Power Integrity Paris
2 2 / Introduction What is jitter separation? Presentation of the test case Simulation settings Comparison simulations vs measurements Conclusion
3 3 / Introduction What is jitter separation? Presentation of the test case Simulation settings Comparison simulations vs measurements Conclusion
4 4 / Introduction Complex designs become more and more difficult to handle A4 size board HD Components 4000 components 50 BGA (1500 pins) HD Interconnections 4000 Nets 14 layers µvias (3+X+3) Etching 120µm Increase of frequency: DDR2 / LVDS : 400MHz Gigabit Ethernet Links High-Speed Links 3,125Gb/s 1 cm A lot of voltage levels Decrease voltage magin 1.2V / 1.8V / 2.5V / 3.3V / More and more enhanced features embedded in the digital boards Miniaturization of the products High-Speed serial links enable to continue to increase the performance and the miniaturization of the digital board.
5 5 / Introduction Multi-gigabits links help to exchange a large amount of information on a small area. Some famous multi-gigabit protocols: PCI express: from 2,5 to 8 Gbps SATA: from 1,5 to 6 Gbps 10GBASE-KR: Gbps Multi-gigabit links vs Parallel Buses: Protocol Requested area Max data rate Efficiency AGP 8x 512w 2 GB/s 4 MB/s/w PCIe x 224w 32 GB/s 143 MB/s/w PCIe 3.0 is x35 more efficient than AGP! HSD links transmit much more data than parallel buses on the same area
6 6 / Introduction HSD links make easier to route the board thanks to lower density but: Use of HSD links requires severe design constraints due to the increase of: Losses Reflections Crosstalk Knowledge in many fields is required to handle HSD designs: Digital electronic High-Frequency Signal processing Materials & Thermal SI analysis becomes a new full-time job.
7 7 / Introduction Goals of the study Ensure that multi-gigabit links will work at the first use of the electronic board. Find a powerful simulation workflow to quickly identify the cause of signal integrity degradation thanks to Jitter separation. Choose the simulation tools Compare EM softwares and find the optimal settings of each test case Correctly setup the circuit simulator taking into account IBIS AMI models Find the right balance between computational time vs accuracy Validate the workflow thanks to measurements
8 8 / Introduction Simulation workflow with IBIS AMI models Geometry Import S Parameters extraction PCB/EDA software Electromagnetic Solver S Parameters Results S Parameters (Black box) Circuit co-simulation with IBIS AMI models Eye Diagram, BER, Jitter
9 9 / Introduction Difficult topics to solve EM Simulations: Setup an accurate model Behaviour of the frequency dependant FR4 Complexity of the EM model, number and size of the objects (µvias, pads, ) Time needed to set up the EM model and calculate S parameters Circuit Simulations HSPICE model: time consuming, do not consider complex digital circuit (CDR, ) IBIS AMI model: very fast (10 6 bits/mn), presence of CDR, EQ circuits but: Unable to mix IBIS AMI models with HSPICE and classic IBIS models Unable to take into account the PDN for SSN simulations The accuracy of the simulation can be validated thanks to measurements + jitter separation.
10 10 / Introduction What is jitter separation? Presentation of the test case Simulation settings Comparison simulations vs measurements Conclusion
11 11 / What is Jitter Separation? Jitter Separation theory Jitter is the undesired deviation from true periodicity of an assumed periodic signal. Jitter Separation (based on algorithms continuously improved) Power supply noise Crosstalk Lossy media Discontinuities Quantify each jitter element = quickly identify the sources of the signal degradation.
12 12 / Introduction What is jitter separation? Presentation of the test case Simulation settings Comparison simulations vs measurements Conclusion
13 13 / Presentation of the test case Why this test case? Models not available, unusual routing, diff pair + single-ended coupling, We must be able to detect the signal integrity problems using simulations. Differential pair MGH_DIA Length: 190 mm Width of the trace: w=130 µm Spacing between P & N channels: s=150 µm Single-ended SSN_SIGA Length: 160 mm Width of the trace: w=130 µm Embedded microstrip on layers 2 & 3 Embedded microstrip on layers 2 & 3 Stratix II GX Coupling length: 7 cm Plated Through Holes
14 14 / Presentation of the test case Test case Spacing between MGH_DIA2_P and SSN_SIGA_79: 120 µm (< s) MGH_DIA2_P between 2 power planes (VCCH et VCCINT) TOP 225 µm 150 µm 80 µm 250 µm Cut view SSN_SIGA_61 SSN_SIGA_79 SSN_SIGA_72 SSN_SIGA_79 MGH_DIA2_P MGH_DIA2_N Top view
15 15 / Introduction What is jitter separation? Presentation of the test case Simulation settings Comparison simulations vs measurements Conclusion
16 16 / Simulation settings S Parameters extraction with Agilent s Momentum Momentum EM model Simplified stack-up Settings: Bandwidth range: DC 10 GHz (meshing at 5 GHz) RF mode Thales Communications
17 17 / Simulation settings S Parameters extraction with Agilent s Momentum Coupling between MGH_DIA2_P and SSN_SIGA_79 NEXT (3D FEM) NEXT (Hybrid) FEXT (Hybrid) FEXT (3D FEM) Momentum gives better eye diagram compared to measurement than hybrid solvers. Hybrid solvers are not able to correctly take into account this topology.
18 18 / Simulation settings Circuit simulation setup with Agilent s ADS IBIS AMI model of Stratix II GX is not available Generic IBIS AMI models available in ADS library are used. Addition of the Stratix IV packages at the generic IBIS AMI output (*.s4p). Ability to mix IBIS AMI and IBIS models By using generic IBIS AMI models By modifying the IBIS netlist 10 6 simulated bits Circuit simulation setting done in about 30 minutes.
19 19 / Introduction What is jitter separation? Presentation of the test case Simulation settings Comparison simulations vs measurements Conclusion
20 20 / Comparison simulations vs measurements MGH_DIA2 without single-ended aggressor (MGH_DIA1 active) Data rate: 1 Gbps Pattern: PRBS7 VOD: 800 mv Jitter Separation processed with Agilent s Infiniiview Simulation Measurement Agilent DSA-X 93204A 33 GHz Crosstalk due to MGH_DIA1 RJ is abnormally high -> the setting of the SERDES clock is wrong Despite the inability of simulating the PJ, the correlation is quite good.
21 21 / Comparison simulations vs measurements MGH_DIA2 with SSN_SIGA_79 at 50 MHz (MGH_DIA1 active) Data rate: 1 Gbps Pattern: PRBS7 VOD: 800 mv Jitter Separation processed with Agilent s Infiniiview Simulation Measurement Agilent DSA-X 93204A 33 GHz The BUJ has tremendously increased due to SSN_SIGA_79 crosstalk Good correlation between simulations and measurements.
22 22 / Comparison simulations vs measurements Synthesis The jitter separation is a very powerful tool: with only 1 simulation or 1 measurement per multi-gigabit link, we are able to: Find the source of the signal integrity degradation. Define a suitable solution in order to improve signal and power integrity. This study enabled to: Implement a complete simulation workflow Mix IBIS and IBIS AMI models Correlate simulations and measurements Reach the limitations of the IBIS AMI standard (Power Distribution Network) Jitter separation and IBIS AMI standard have to continue to be improved.
23 23 / Introduction What is jitter separation? Presentation of the test case Simulation settings Comparison simulations vs measurements Conclusion
24 24 / Classic simulation workflow without jitter separation Update Allegro BRD Potential aggressors Momentum ADS (1 eye diagram per HSD Link) - No aggressor - No pre-emphasis / no equalization OK Virtual compliance + margins NOK Crosstalk Pre-emphasis / Equalization NOK Virtual compliance + margins OK Virtual compliance + margins OK Design OK NOK PI problems of HSD links are not taken into account in this simulation workflow.
25 25 / New simulation workflow with jitter separation BRD Allegro Potential Aggressors Momentum Problem identified Solution without modification of routing Solution with modification of routing S Parameters ADS - Crosstalk - Power Distribution Network - (Pre-emphasis / Equalization) NOK Update Virtual compliance + margins NOK OK Infiniiview (Jitter Separation) Identify Signal Integrity Problems Design OK RJ PJ ISI BUJ Verify the declaration of the clock Modify the PDN (value of the capacitors) Add pre-emphasis or equalization Increase the rise time or decrease the frequency of the signal Change the component Modify the PDN (plane, location of the capacitors) Optimize the channel (traces, vias, stubs, connectors, ) Isolate the traces (spacing, plane, gnd vias, ) This new simulation workflow is simpler.
26 26 / Conclusion Conclusion Agilent Technologies offers a complete simulation workflow from EM simulation to jitter separation to quickly identify the source of the signal degradation. Future work Follow the evolution of the IBIS AMI standard Effect of the power distribution network on the multi-gigabit links? Continue to improve design rules and methodology. Establish a method to find precisely the location of the signal or power integrity problems on the electronic board. Improve jitter separation algorithmes in presence of coding and equalization. Validate the simulation tools for data rate > 20 Gbps
27 27 / Thank you for your attention
Integrating ADS into a High Speed Package Design Process
Integrating ADS into a High Speed Package Design Process Page 1 Group/Presentation Title Agilent Restricted Month ##, 200X Agenda High Speed SERDES Package Design Requirements Performance Factor and Design
More informationElectrical optimization and simulation of your PCB design
Electrical optimization and simulation of your PCB design Steve Gascoigne Senior Consultant at Mentor Graphics Zagreb, 10. lipnja 2015. Copyright CADCAM Group 2015 The Challenge of Validating a Design..
More informationBoard Design Guidelines for PCI Express Architecture
Board Design Guidelines for PCI Express Architecture Cliff Lee Staff Engineer Intel Corporation Member, PCI Express Electrical and Card WGs The facts, techniques and applications presented by the following
More informationApplication Note. PCIE-EM Series Final Inch Designs in PCI Express Applications Generation GT/s
PCIE-EM Series Final Inch Designs in PCI Express Applications Generation 3-8.0 GT/s Copyrights and Trademarks Copyright 2015, Inc. COPYRIGHTS, TRADEMARKS, and PATENTS Final Inch is a trademark of, Inc.
More informationQ2 QMS/QFS 16mm Stack Height Final Inch Designs In PCI Express Applications Generation Gbps. Revision Date: February 13, 2009
Q2 QMS/QFS 16mm Stack Height Final Inch Designs In PCI Express Applications Generation 2 5.0 Gbps Revision Date: February 13, 2009 Copyrights and Trademarks Copyright 2009 Samtec, Inc. Developed in conjunction
More informationApplication Note. PCIE-RA Series Final Inch Designs in PCI Express Applications Generation GT/s
PCIE-RA Series Final Inch Designs in PCI Express Applications Generation 3-8.0 GT/s Copyrights and Trademarks Copyright 2012, Inc. COPYRIGHTS, TRADEMARKS, and PATENTS Final Inch is a trademark of, Inc.
More informationAllegro Sigrity SI Streamlining the creation of high-speed interconnect on digital PCBs and IC packages
Streamlining the creation of high-speed interconnect on digital PCBs and IC packages The Cadence Allegro Sigrity signal integrity (SI) integrated high-speed design and analysis environment streamlines
More informationExplore your design space including IBIS AMI models with Advanced Channel Simulation
Explore your design space including IBIS AMI models with Advanced Channel Simulation Heidi Barnes Vincent Poisson Presenter: May, 2013 Agenda How good is my PHY? Channel Simulation Options Spice (Circuit
More informationAMI Applications in High-speed Serial Channel Analysis and Measurement Correlation
AMI Applications in High-speed Serial Channel Analysis and Measurement Correlation Jia Wei, Sunanbing, Zhu ShunLin Jia.wei@zte.com.cn, sun.anbing@zte.com.cn, Zhu.shunlin@zte.com.cn High-Speed System Lab,ZTE
More informationOptimization of Modern Memory
System Design, Verificationand and Optimization of Modern Memory Interfaces (DDR3) Santa Clara, Aug 23 rd 2011 Robert Myoung Sr. Application Engineer 1 Agenda Introduction ECAD Geometry Translation SI/PI
More informationAdvanced SI Analysis Layout Driven Assembly. Tom MacDonald RF/SI Applications Engineer II
Advanced SI Analysis Layout Driven Assembly 1 Tom MacDonald RF/SI Applications Engineer II Abstract As the voracious appetite for technology continually grows, so too does the need for fast turn around
More informationSEAM-RA/SEAF-RA Series Final Inch Designs in PCI Express Applications Generation GT/s
SEAM-RA/SEAF-RA Series Final Inch Designs in PCI Express Applications Generation 3-8.0 GT/s Copyrights and Trademarks Copyright 2011 Samtec, Inc. Developed in conjunction with Teraspeed Consulting Group
More informationMECT Series Final Inch Designs in SFP+ Applications. Revision Date: August 20, 2009
MECT Series Final Inch Designs in SFP+ Applications Revision Date: August 20, 2009 Copyrights and Trademarks Copyright 2009 Samtec, Inc. Developed in conjunction with Teraspeed Consulting Group LLC COPYRIGHTS,
More informationPCIEC PCI Express Jumper High Speed Designs in PCI Express Applications Generation GT/s
PCIEC PCI Express Jumper High Speed Designs in PCI Express Applications Generation 3-8.0 GT/s Mated with PCIE-RA Series PCB Connectors Copyrights and Trademarks Copyright 2015, Inc. COPYRIGHTS, TRADEMARKS,
More informationWhat s New in HyperLynx 8.0
What s New in HyperLynx 8.0 Copyright Mentor Graphics Corporation 2009 All Rights Reserved. Mentor Graphics, Board Station XE Flow, ViewDraw, Falcon Framework, IdeaStation, ICX and Tau are registered trademarks
More informationA Modular Platform for Accurate Multi- Gigabit Serial Channel Validation
A Modular Platform for Accurate Multi- Gigabit Serial Channel Validation Presenter: Andrew Byers Ansoft Corporation High Performance Electronics: Technical Challenges Faster data rates in increasingly
More informationHigh-Speed DDR4 Memory Designs and Power Integrity Analysis
High-Speed DDR4 Memory Designs and Power Integrity Analysis Cuong Nguyen Field Application Engineer cuong@edadirect.com www.edadirect.com 2014 1 PCB Complexity is Accelerating Use of Advanced Technologies
More informationRiseUp RU8-DP-DV Series 19mm Stack Height Final Inch Designs in PCI Express Applications. Revision Date: March 18, 2005
RiseUp RU8-DP-DV Series 19mm Stack Height Final Inch Designs in PCI Express Applications Revision Date: March 18, 2005 Copyrights and Trademarks Copyright 2005 Samtec, Inc. Developed in conjunction with
More information5 GT/s and 8 GT/s PCIe Compared
5 GT/s and 8 GT/s PCIe Compared Bent Hessen-Schmidt SyntheSys Research, Inc. Copyright 2008, PCI-SIG, All Rights Reserved 1 Disclaimer The material included in this presentation reflects current thinking
More informationAdvanced Jitter Analysis with Real-Time Oscilloscopes
with Real-Time Oscilloscopes August 10, 2016 Min-Jie Chong Product Manager Agenda Review of Jitter Decomposition Assumptions and Limitations Spectral vs. Tail Fit Method with Crosstalk Removal Tool Scope
More informationSignal Integrity Analysis for 56G-PAM4 Channel of 400G Switch
Signal Integrity Analysis for 56G-PAM4 Channel of 400G Switch Sophia Feng/Vincent Wen of Celestica sopfeng@celestica.com Asian IBIS Summit Shanghai, PRC November 13, 2017 Agenda Background 200GBASE-KR4
More informationThe Fast Track to PCIe 5.0
WHITE PAPER The Fast Track to PCIe 5.0 Doubling the Throughput of PCIe 4.0 to 32 GT/s Data center operators need to embrace next-generation technologies to support the response times and high bandwidth
More informationQ Pairs QTE/QSE-DP Final Inch Designs In PCI Express Applications 16 mm Stack Height
Application Note Q Pairs QTE/QSE-DP Final Inch Designs In PCI Express Applications 16 mm Stack Height Copyrights and Trademarks Copyright 2004 Samtec, Inc. Developed in conjunction with Teraspeed Consulting
More informationDisplayPort 1.4 Webinar
DisplayPort 1.4 Webinar Test Challenges and Solution Yogesh Pai Product Manager - Tektronix 1 Agenda DisplayPort Basics Transmitter Testing Challenges DisplayPort Type-C Updates Receiver Testing Q and
More informationEDA365. DesignCon Impact of Backplane Connector Pin Field on Trace Impedance and Vertical Field Crosstalk
DesignCon 2007 Impact of Backplane Connector Pin Field on Trace Impedance and Vertical Field Crosstalk Ravi Kollipara, Rambus, Inc. ravik@rambus.com, (650) 947-5298 Ben Chia, Rambus, Inc. Dan Oh, Rambus,
More informationSimulation Strategies for Massively Parallel Supercomputer Design
Simulation Strategies for Massively Parallel Supercomputer Design Authored by: Ansoft Corporation Special Thanks to: Cray Presentation #2 Ansoft 2003 / Global Seminars: Delivering Performance Introduction
More informationTektronix Innovation Forum
Tektronix Innovation Forum Enabling Innovation in the Digital Age DisplayPort 1.2 Spec Updates and overview of Physical layer conformance testing Presenter: John Calvin DisplayPort 1.2 Spec Updates Agenda
More informationPackage on Board Simulation with 3-D Electromagnetic Simulation
White Paper Package on Board Simulation with 3-D Electromagnetic Simulation For many years, designers have taken into account the effect of package parasitics in simulation, from using simple first-order
More informationMC92610, Gbaud Reference Design Platform An 8-Slot Full-Mesh or Fabric Backplane Reference Design
Freescale Semiconductor White Paper BR1570 Rev. 1, 03/2005 MC92610, 3.125 Gbaud Reference Design Platform An 8-Slot Full-Mesh or Fabric Backplane Reference Design by: SerDes Applications Team Abstract
More informationAgilent Technologies Advanced Signal Integrity
Agilent Technologies Advanced Signal Integrity Measurements for Next Generation High Speed Serial Standards Last Update 2012/04/24 (YS) Appendix VNA or TDR Scope? ENA Option TDR Overview USB 3.0 Cable/Connector
More informationSignal Integrity for High Speed Digital Design Introduction
Signal Integrity for High Speed Digital Design Introduction Gustaaf Sutorius Application Engineer Agenda Signal Integrity for High Speed Digital Design : introduction 1. Introduction Agilent 2. Typical
More informationIBIS-AMI Model Simulations Over Six EDA Platforms
IBIS-AMI Model Simulations Over Six EDA Platforms Romi Mayder, romi.mayder@xilinx.com Ivan Madrigal, ivan.madrigal@xilinx.com Brandon Jiao, brandon.jiao@xilinx.com Hongtao Zhang, hongtao.zhang@xilinx.com
More informationUsing ADS to Post Process Simulated and Measured Models. Presented by Leon Wu March 19, 2012
Using ADS to Post Process Simulated and Measured Models Presented by Leon Wu March 19, 2012 Presentation Outline Connector Models From Simulation Connector Models From Measurement The Post processing,
More informationPCI Express Electrical Basics
PCI Express Electrical Basics Dean Gonzales Advanced Micro Devices Copyright 2015, PCI-SIG, All Rights Reserved 1 Topics PCI Express Overview Enhancements for 8GT/s Target Channels for the Specification
More informationSignal Integrity Comparisons Between Stratix II and Virtex-4 FPGAs
White Paper Introduction Signal Integrity Comparisons Between Stratix II and Virtex-4 FPGAs Signal integrity has become a critical issue in the design of high-speed systems. Poor signal integrity can mean
More informationAN INTRODUCTION TO HYPERLYNX SI/PI TECHNOLOGY
AN INTRODUCTION TO HYPERLYNX SI/PI TECHNOLOGY BY STEVE KAUFER, MENTOR H I G H S P E E D D E S I G N W H I T E P A P E R OVERVIEW Digital designers are now required to make the leap from time domain to
More informationApplication Note 1242
HFBR-5701L/5710L/5720L/5730L and HDMP-1687 Reference Design for 1.25 GBd Gigabit Ethernet and 1.0625 GBd Fiber Channel Applications Application Note 1242 Introduction Avago s objective in creating this
More informationAgilent Technologies EZJIT and EZJIT Plus Jitter Analysis Software for Infiniium Series Oscilloscopes
Agilent Technologies EZJIT and EZJIT Plus Jitter Analysis Software for Infiniium Series Oscilloscopes Data Sheet Features of the EZJIT Plus software that optimize jitter analysis include: Easy-to-use jitter
More informationdesigns with signals operating in the multi-gigahertz (MGH) frequency range. It
DATASHEET ALLEGRO PCB SI GXL Cadence Allegro PCB SI GXL provides a virtual prototyping environment for designs with signals operating in the multi-gigahertz (MGH) frequency range. It offers a completely
More informationSerial Link Analysis and PLL Model
25. July 2007 Serial Link Analysis and PLL Model September 11, 2007 Asian IBIS Summit, Beijing China Huang Chunxing huangchunxing@huawei.com www.huawei.com HUAWEI TECHNOLOGIES Co., Ltd. Agenda High-speed
More informationUnderstanding 3M Ultra Hard Metric (UHM) Connectors
3M Electronic Solutions Division 3MUHMWEBID_100809 Understanding 3M Ultra Hard Metric (UHM) Connectors Enabling performance of next generation 2 mm Hard Metric systems 3M Electronic Solutions Division
More informationPI2EQX6874ZFE 4-lane SAS/SATA ReDriver Application Information
Contents General Introduction How to use pin strap and I2C control External Components Requirement Layout Design Guide Power Supply Bypassing Power Supply Sequencing Equalization Setting Output Swing Setting
More informationPCI Express 3.0 Characterization, Compliance, and Debug for Signal Integrity Engineers
PCI Express 3.0 Characterization, Compliance, and Debug for Signal Integrity Engineers - Transmitter Testing - Receiver Testing - Link Equalization Testing David Li Product Marketing Manager High Speed
More informationThe Touchstone 2.0 Format for Interconnect Modeling
29 The Touchstone 2. Format for Interconnect Modeling SIEMENS AG manfred.maurer@siemens.com 29 Purpose / goal 2 Importance of the channel description for SI+PI Touchstone format 2. is a good choice 29
More informationCadence Power Integrity Solutions For PCBs and IC Packages. May 2013
Cadence Power Integrity Solutions For PCBs and IC Packages May 2013 Simultaneous Switching Noise (SSN) A Power Integrity Issue Design with decaps intentionally removed to demonstrate how poor PI performance
More informationPredicting BER with IBIS-AMI: experiences correlating SerDes simulations and measurement
Predicting BER with IBIS-AMI: experiences correlating SerDes simulations and measurement Todd Westerhoff (SiSoft) Mike Steinberger (SiSoft) Walter Katz (SiSoft) Barry Katz (SiSoft) Adge Hawes (IBM) Kent
More informationModeling and Simulation for Multi- Gigabit Interconnect System
Asian IBIS Summit Modeling and Simulation for Multi- Gigabit Interconnect System Zhu Shunlin ( 朱顺临 ) Hu Weidong Chen Songrui High-Speed System Lab,ZTE Corporation Zhu.shunlin@zte.com.cn Beijing,China September
More informationA HT3 Platform for Rapid Prototyping and High Performance Reconfigurable Computing
A HT3 Platform for Rapid Prototyping and High Performance Reconfigurable Computing Second International Workshop on HyperTransport Research and Application (WHTRA 2011) University of Heidelberg Computer
More informationHigh Speed and High Power Connector Design
High Speed and High Power Connector Design Taiwan User Conference 2014 Introduction High speed connector: Electrically small Using differential signaling Data rate >100Mbps High power connector: Static
More information40 GbE Over 4-lane 802.3ap Compliant Backplane
40 GbE Over 4-lane 802.3ap Compliant Backplane, Intel Contributors: Ted Ballou, Intel Ilango Ganga, Intel Robert Hays, Intel IEEE 802.3 HSSG November 2007 Agenda 40 GbE proposition 40 GbE system configuration
More information100GbE Architecture - Getting There... Joel Goergen Chief Scientist
100GbE Architecture - Getting There... Joel Goergen Chief Scientist April 26, 2005 100GbE Architecture - Getting There Joel Goergen Force10 Networks joel@force10networks.com Subject : 100GbE Architecture
More informationDisplayPort Testing Challenges
DisplayPort Testing Challenges U N Vasudev May 6 th 2013 Agenda DisplayPort Overview DisplayPort 1.2 updates DisplayPort 1.2 Transmitter Testing What s New: T2, TP3, TP3EQ Physical Layer Test Overview
More informationPCI Express 4.0. Electrical compliance test overview
PCI Express 4.0 Electrical compliance test overview Agenda PCI Express 4.0 electrical compliance test overview Required test equipment Test procedures: Q&A Transmitter Electrical testing Transmitter Link
More informationHigh-Speed Jitter Testing of XFP Transceivers
White Paper High-Speed Jitter Testing of XFP Transceivers By Andreas Alpert Abstract Jitter is a key performance factor in high-speed digital transmission systems, such as synchronous optical networks/synchronous
More informationSolving the challenges posed by Chip/Package/Board Co-Design
Solving the challenges posed by Chip/Package/Board Co-Design Identify and locate sources of unwanted coupling Simulation link to EM: Critical Interconnect, Vias, Discontinuities, Embedded Passives, etc
More informationCharacterize and Debug Crosstalk Issues with Keysight Crosstalk Analysis App
Chong Min-Jie Characterize and Debug Crosstalk Issues with Crosstalk Analysis App Page Characterize and Debug Crosstalk Issues with Crosstalk Analysis App Min-Jie Chong HPS Product Manager & Planner Oscilloscope
More informationGenesys 2012 Tutorial - Using Momentum Analysis for Microwave Planar Circuits
Genesys 2012 Tutorial - Using Momentum Analysis for Microwave Planar Circuits Create the following schematics in Figure 1 with Genesys s schematic editor, which depicts two sections of a cascaded microstrip
More informationSerDes Channel Simulation in FPGAs Using IBIS-AMI
White Paper: Virtex-6 FPGA Family WP382 (v10) December 9, 2010 SerDes Channel Simulation in FPGAs Using IBIS-AMI By: Romi Mayder The IBIS Algorithmic Modeling Interface (IBIS-AMI) was developed to enable
More information3.3V, 3.2Gbps DIFFERENTIAL 4:1 LVDS MULTIPLEXER with INTERNAL INPUT TERMINATION
3.3V, 3.2Gbps DIFFERENTIAL 4:1 LVDS MULTIPLEXER with TERNAL PUT TERMATION FEATURES Selects among four differential inputs Guaranteed AC performance over temp and voltage: DC-to > 3.2Gbps data rate throughput
More informationAN 608: HST Jitter and BER Estimator Tool for Stratix IV GX and GT Devices
AN 608: HST Jitter and BER Estimator Tool or Stratix IV GX and GT Devices July 2010 AN-608-1.0 The high-speed communication link design toolkit (HST) jitter and bit error rate (BER) estimator tool is a
More informationModeling MultiGigabit FPGA Channels with Agilent ADS 2008
Modeling MultiGigabit FPGA Channels with Agilent ADS 2008 Andy Turudic Sr. Manager, High-End FPGAs Altera aturudic@altera.com Amolak Badesha Field Applications Engineer - Agilent 2008 Altera Corporation
More informationProposal for modeling advanced SERDES
Proposal for modeling advanced SERDES IBM, Cadence June 2006 1 CADENCE DESIGN SYSTEMS, INC. Presenters, Contributors Presenters / Contributors 1. Joe Abler IBM Systems & Technology Group High Speed Serial
More informationAgilent. Master your next PCIe test with the Agilent M8020A High-Performance BERT Application Brief
Agilent Master your next PCIe test with the Agilent M8020A High-Performance BERT Application Brief 1 Table of Contents Contents Disclaimer... 3 1 Introduction... 4 2 PCI Express Specifications... 4 3 PCI
More informationAddressing the Power-Aware Challenges of Memory Interface Designs
Addressing the Power-Aware Challenges of Memory Interface Designs One of the toughest challenges in designing memory interfaces is accurately measuring timing while also considering fluctuations in power
More information2.5V, 3.2Gbps, DIFFERENTIAL 4:1 LVDS MULTIPLEXER WITH INTERNAL INPUT TERMINATION
2.5V, 3.2Gbps, DIFFERENTIAL 4:1 LVDS MULTIPLEXER WITH TERNAL PUT TERMATION FEATURES Selects among four differential inputs Guaranteed AC performance over temp and voltage: DC-to > 3.2Gbps data rate throughput
More informationOptimizing High-Speed Digital Channels Using State-of-the-art Signal Integrity Tools
Optimizing High-Speed Digital Channels Using State-of-the-art Signal Integrity Tools 2 Welcome and Agenda Time Agenda Presenter 9:00-9:30 Registration & Continental Breakfast 9:30-10:00 Welcome and keynote
More informationAgilent Technologies N5393A PCI Express Electrical Performance Validation and Compliance Software for Infiniium 54855A or Series Oscilloscopes
Agilent Technologies N5393A PCI Express Electrical Performance Validation and Compliance Software for Infiniium 54855A or 80000 Series Oscilloscopes Data Sheet Verify and debug your PCI Express designs
More informationI N T E R C O N N E C T A P P L I C A T I O N N O T E. STRADA Whisper 4.5mm Connector Enhanced Backplane and Daughtercard Footprint Routing Guide
I N T E R C O N N E C T A P P L I C A T I O N N O T E STRADA Whisper 4.5mm Connector Enhanced Backplane and Daughtercard Footprint Routing Guide Report # 32GC001 01/26/2015 Rev 3.0 STRADA Whisper Connector
More informationKeysight Technologies EZJIT Plus Jitter Analysis Software for Infiniium Oscilloscopes. Data Sheet
Keysight Technologies EZJIT Plus Jitter Analysis Software for Infiniium Oscilloscopes Data Sheet 02 Keysight EZJIT Plus Jitter Analysis Software for Infiniium Oscilloscopes - Data Sheet Table of Contents
More informationIP1001 LF DESIGN & LAYOUT GUIDELINES
Index 1 Purpose...2 2 Magnetic trace routing...2 3 Power Supply Plane & GND Plane...3 4 PHY interface...3 5 Trace routing & Placement...3 6 ESD protection...3 7 EMI Supression...3 1/7 April 17 2008. Ver:1.5
More informationSymbol Parameter Min Typ Max VDD_CORE Core power 0.9V 1.0V 1. 1V. VDD33 JTAG/FLASH power 2.97V 3.3V 3.63V
1 Introduction The user guide provides guidelines on how to help you successfully design the CME-M7 board which includes the power supply, configuration, clock, DDR2 or DDR3, high speed USB, LVDS and ADC
More informationLeveraging IBIS Capabilities for Multi-Gigabit Interfaces. Ken Willis - Cadence Design Systems Asian IBIS Summit, Shanghai, PRC November 13, 2017
Leveraging IBIS Capabilities for Multi-Gigabit Interfaces Ken Willis - Cadence Design Systems Asian IBIS Summit, Shanghai, PRC November 13, 2017 Overview In writing EDI CON paper Signal Integrity Methodology
More informationPCI Express 1.0a and 1.1 Add-In Card Transmitter Testing
Abstract PCI Express 1.0a and 1.1 Add-In Card Transmitter Testing Joan Gibson November 2006 SR-TN062 Add-in cards designed for PCI Express require numerous tests to assure inter-operability with different
More informationUsing IBIS-AMI in the Modeling of Advanced SerDes Equalization for Serial Link Simulation
Using IBIS-AMI in the Modeling of Advanced SerDes Equalization for Serial Link Simulation CDNLive Boston August 2013 Mark Marlett and Mahesh Tirupattur, Analog Bits Ken Willis and Kumar Keshavan, Cadence
More informationIBIS-AMI Modeling and Simulation of 56G PAM4 Link Systems
IBIS-AMI Modeling and Simulation of 56G PAM4 Link Systems Hongtao Zhang, hongtao@xilinx.com Fangyi Rao, fangyi_rao@keysight.com Xiaoqing Dong, dongxiaoqing82@huawei.com Geoff Zhang, geoffz@xilinx.com Outline
More informationHigh performance HBM Known Good Stack Testing
High performance HBM Known Good Stack Testing FormFactor Teradyne Overview High Bandwidth Memory (HBM) Market and Technology Probing challenges Probe solution Power distribution challenges PDN design Simulation
More informationUsing RJ45 Category 7 Cabling for 2 Lane, 1 and 2.5Gbps Serial Data Transmission
Using RJ45 Category 7 Cabling for 2 Lane, 1 and 2.5Gbps Serial Data Transmission Test 8561 (Category 7, 2 lane) J Sawdy, Sr. SI Engineer 4/14/10 Forward The RJ45 connector is found in enterprise installations
More informationQPairs QTE/QSE-DP Multi-connector Stack Designs In PCI Express Applications 16 mm Connector Stack Height REVISION DATE: OCTOBER 13, 2004
Application Note QPairs QTE/QSE-DP Multi-connector Stack Designs In PCI Express Applications 16 mm Connector Stack Height REVISION DATE: OCTOBER 13, 2004 Copyrights and Trademarks Copyright 2004 Samtec,
More informationVerification of ICN Usability in Characterizing System Crosstalk
Asian IBIS Summit Shanghai, P.R. China November 9, 212 Verification of ICN Usability in Characterizing System Crosstalk Dongxiaoqing, Huangchunxing www.huawei.com HUAWEI TECHNOLOGIES CO., LTD. ICN Definition
More informationValidation of Quasi-Analytical and Statistical Simulation Techniques for Multi-Gigabit Interconnect Channels
DesignCon 2010 Validation of Quasi-Analytical and Statistical Simulation Techniques for Multi-Gigabit Interconnect Channels Chad Morgan, Tyco Electronics chad.morgan@tycoelectronics.com, 717-649-4129 Abstract
More informationADS USB 3.1 Compliance Test Bench
ADS 2016.01 USB 3.1 Compliance Test Bench Notices Keysight Technologies, Inc. 1983-2016 1400 Fountaingrove Pkwy., Santa Rosa, CA 95403-1738, United States All rights reserved. No part of this documentation
More informationQDR II SRAM Board Design Guidelines
8 emi_dg_007 Subscribe The following topics provide guidelines for you to improve your system's signal integrity and layout guidelines to help successfully implement a QDR II or QDR II+ SRAM interface
More informationEXAMINING THE IMPACT OF SPLIT PLANES ON SIGNAL AND POWER INTEGRITY
EXAMINING THE IMPACT OF SPLIT PLANES ON SIGNAL AND POWER INTEGRITY Jason R. Miller, Gustavo J. Blando, Roger Dame, K. Barry A. Williams and Istvan Novak Sun Microsystems, Burlington, MA 1 AGENDA Introduction
More informationAdvances in 3D Simulations of Chip/Package/PCB Co-Design
Advances in 3D Simulations of Chip/Package/PCB Co-Design Richard Sjiariel, CST AG Co-design environment Signal Integrity and timing Thermal analysis and stress Power Integrity and noise analysis EMC/EMI
More informationIConnect SW for DSA8300* 1 Sampling Oscilloscope
IConnect SW for DSA8300* 1 Sampling Oscilloscope 80SICMX 80SICON 80SSPAR Data Sheet Easily Analyze Sources of Interconnect Jitter, Losses, Crosstalk, Reflections, and Ringing Analyze Interconnects Concurrently
More informationI N T E R C O N N E C T A P P L I C A T I O N N O T E. STEP-Z Connector Routing. Report # 26GC001-1 February 20, 2006 v1.0
I N T E R C O N N E C T A P P L I C A T I O N N O T E STEP-Z Connector Routing Report # 26GC001-1 February 20, 2006 v1.0 STEP-Z CONNECTOR FAMILY Copyright 2006 Tyco Electronics Corporation, Harrisburg,
More informationALLEGRO PCB SI 630 DATASHEET VIRTUAL PROTOTYPING ENVIRONMENT FOR DESIGNS WITH MULTI-GIGAHERTZ SIGNALS THE ALLEGRO SYSTEM INTERCONNECT DESIGN PLATFORM
DATASHEET ALLEGRO PCB SI 630 VIRTUAL PROTOTYPING ENVIRONMENT FOR DESIGNS WITH MULTI-GIGAHERTZ SIGNALS Cadence Allegro PCB SI 630 a key PCB Signal Integrity tool within the Allegro system interconnect design
More informationDesigning High-Speed Memory Subsystem DDR. using. Cuong Nguyen. Field Application Engineer
Designing High-Speed Memory Subsystem using DDR Cuong Nguyen Field Application Engineer cuong@edadirect.com www.edadirect.com 2014 1 Your Design for Excellence Partner Since 1997 EDA Direct has helped
More informationPCB PCB. (dielectric constant) (Crosstalk) ground guard/shunt traces. (termination) side-by-side
PCB 1 PCB PCB PCB ( GHz ) FR-4 GHz (dielectric loss) (dielectric constant) 2 (Crosstalk) ground guard/shunt traces 3 (output impedance)(topology) (termination) 4 ( ) (side-by-side) (over-under) side-by-side
More informationSerial ATA Gen2 Jitter Tolerance Testing
Serial ATA Gen2 Jitter Tolerance Testing Abstract Guy Foster SyntheSys Research, Inc. February 21, 2006 SR-TN054 Serial ATA [i] is an increasingly common serial bus technology aimed at disk drive applications.
More informationPCI Express Link Equalization Testing 서동현
PCI Express Link Equalization 서동현 Application Engineer January 19th, 2016 Agenda Introduction Page 2 Dynamic Link Equalization TX/RX Link Equalization Tests Test Automation RX Stress Signal Calibration
More informationHigh-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs. I.K. Anyiam
High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs I.K. Anyiam 1 Introduction LVDS SerDes helps to reduce radiated emissions, but does not completely eliminate them EMI prevention must
More informationAgenda TDR Measurements Using Real World Products
Agenda TDR Measurements Using Real World Products The Case for using both TDR and S-parameters Device Package Analysis - Measure Impedance -C-self Characterizing Device Evaluation Test board Measure Differential
More informationHigh Speed Design Testing Solutions
High Speed Design Testing Solutions - Advanced Tools for Compliance, Characterization and Debug name title Agenda High-Speed Serial Test Challenges High-Speed Serial Test Simplified - Characterization
More informationOn the Modeling and Analysis of Jitter in ATE Using Matlab
On the Modeling and Analysis of Jitter in ATE Using Matlab Kyung Ki Kim, Jing Huang, Yong-Bin Kim, Fabrizio Lombardi Department of Electrical and Computer Engineering Northeastern University, Boston, MA,
More informationUnderstanding IBIS-AMI Simulations
Understanding IBIS-AMI Simulations IBIS European Summit SPI, Turin, Italy May 11, 2016 Richard Allred, Signal Integrity Software Agenda IBIS-AMI Assumptions & Terminology IBIS-AMI Model Components Analysis
More informationNational Semiconductor EVK User Manual
SD356EVK Evaluation Kit Board for LMH0356 SDI Reclocker User Manual National Semiconductor EVK User Manual Introduction The LMH0356 Serial Digital Interface (SDI) reclocker is designed to recover a clean
More informationPI2EQX6804-ANJE Four-lane SAS/SATA ReDriver Application Information May 13, 2011
Contents General Introduction How to use pin strap and I2C control External Components Requirement Layout Design Guide Power Supply Bypassing Power Supply Sequencing Equalization Setting Output Swing Setting
More informationTITLE. on SSD Boards. Image. Topic: Topic: Seong-Jin Mun, (Samsung Electronics Inc.)
TITLE Topic: Far-Field o Nam elementum EMI commodo Analysis mattis. Pellentesque Methodology and Verification on SSD Boards Topic: o malesuada blandit euismod. Seong-Jin Mun, (Samsung Electronics Inc.)
More informationAgilent Bead Probe Technology
Agilent Bead Probe Technology Page 1 Abstract Lead-free, shrinking geometries, new packages and high-speed signaling present new challenges for ICT. The impact will be more defects, loss of access, lower
More information