Real Time Hardware Co-Simulation for Image Processing Algorithms Using Xilinx System Generator

Transcription

1 International Journal on Electrical Engineering and Informatics - Volume 7, Number 4, Desember 2015 Real Time Hardware Co-Simulation for Image Processing Algorithms Using Xilinx System Generator Mohammed Alareqi 1,3, Rachid Elgouri 1, 2, Khalid Mateur 1, and Laamari Hlou 1 1 Laboratory of Electrical Engineering and Energy System. Faculty of Sciences, Ibn Tofaïl University, Kenitra, Morocco 2 Laboratory of Electrical Engineering and Telecommunications Systems, National School of Applied Sciences (ENSA), Ibn Tofaïl University, Kenitra, Morocco 3 Community College, Sana'a, Yemen Alareqi_mohammed@yahoo.com Abstract: The implementation of digital image processing required detailed knowledge of both hardware design and hardware description languages. This paper presents an efficient approach for the implementation of real time hardware digital image processing algorithms without requiring detailed knowledge of hardware design and hardware description languages. The purpose of this work is to achieve a real time hardware implementation with higher performance in both size and speed. It focuses on the implementation of an efficient architecture for image processing algorithms like segmentation (threshold) and contrast stretching by using the fewest possible system generator blocks for DSP tool, which integrates itself with the MATLAB based Simulink graphics environment and relieves the user of the textual HDL programming. While Past research has shown that the Image enhancement techniques on FPGA based on the Xilinx System Generator. This study connect between image histogram and Image enhancement techniques depending on the type of enhancement required. This paper describes also the methodology for implementing real-time DSP applications on FPGA and concept of hardware software co-simulation for digital image processing by using the Mathworks model-based design tool Simulink / Xilinx System Generator (XSG). Performances of efficient architectures are implemented on FPGA Virtex5 (XUPV5-LX110T). Keywords: Image processing; Xilinx system generator; Field Programmable Gate Array (FPGA); DSP. 1. Introduction Image enhancement techniques improve the visibility of the images. Enhancement results, the output image is more suitable for a specific application rather than input image. It is used in many image-processing applications like medical imaging, SONAR and RADAR as a preprocessing step. Hence, this paper presents the hardware co-simulation and implementation of image enhancement algorithms on FPGA. At present, the use of FPGA in research and development of applied digital systems for specific tasks are increasing. This is due to the advantage FPGAs have over other programmable devices. The advantages include: high clock frequency, high operations per second, code portability, code library reusability, low cost, parallel processing, capability of interacting with high or low interfaces, security and intellectual property (IP) retention [1]. The availability of FPGA design tools that work at a higher level of abstraction allows users to work with FPGAs without detailed knowledge of HDLs. One of such tools is the LabVIEW FPGA. [2] Discussed the use of this tool in DSP teaching. Another tool that also works at a higher level of abstraction and is conducive for those having prior knowledge of MATLAB and Simulink, is the Xilinx System Generator for DSP. [3] Presented a basic DSP design methodology using this tool. Received: March 21 st, Accepted: December 15 th, 2015 DOI: /ijeei

2 Mohammed Alareqi, et al. DSP functions are implemented on two primary platforms such as Digital Signal Processors (DSPs) and FPGAs [4]. Consequently, this paper presents an efficient approach for the implementation of digital image processing in real time (Image enhancement) on FPGA without requiring detailed knowledge of both hardware design and hardware description languages. The approach is based on the Xilinx System Generator for DSP tool, which integrates itself with the MATLAB based Simulink Graphics environment and relieves the user of the textual HDL programming. FPGAs are increasingly used in modern imaging applications image filtering [5-6], medical imaging [7-8], image compression and wireless communication [9]. The rest of the paper is organized as follows. Section2 describes Xilinx System Generator. Section3 presents proposed work. Study case (algorithm for image segmentation threshold and an algorithm for image contrast stretching) displayed in section 4. Sections 5&6 describes the hardware co-simulation, Implementation, and results. Finally, the concluding remarks are given in Section Overview of the Xilinx System Generator System Generator is a DSP design tool from Xilinx created to implement DSP applications on FPGA using the Mathworks model-based design tool Simulink [10]. This tool is very easy to work with because it does not require a previous knowledge of hardware design methodologies. The design by using System Generator only needs a DSP Simulink modeling environment but based on a specific block set from Xilinx. All the downstream FPGA implementation steps including synthesis, place and route are automatically performed to generate an FPGA programming file. System Generator provides a system integration platform for the design of DSP and FPGAs that allows the RTL, Simulink, MATLAB and C/C++ components of a DSP system to come together in a single simulation and implementation environment. System Generator supports a black box block that allows RTL to be imported to Simulink and co-simulated with either ModelSim or Xilinx ISE Simulator. Consequently, the proposed Xilinx System Generator and HDL Co-simulator platform based approaches help the designer to make fault diagnosis, complete analysis of the system, evaluation of system performance, and enhancement of the system performance prior to final implementation onto hardware. This result in reduction in design time and faults also ensures that the designs meet design specifications. Figure1 summarizes the steps of the System Generator design flow. Figure 1. Design flow for xilinx system generator [10] 712

3 Real Time Hardware Co-Simulation for Image Processing Algorithms 3. Proposed Work The objective of this work is to implement an image enhancement algorithm (Segmentation by Thresholding and contrast stretching) by using the fewest possible System Generator Blocks in Field Programmable Gate Array (FPGA) using Xilinx System Generator for still digital images as shown in proposed block diagram, figure(2). The processing method needs to be implemented in hardware in order to meet the real time applications. FPGA implementation can be performed using prototyping environment using Matlab /Simulink and Xilinx System Generator tool goes through 3 phases: Image pre-processing blocks Algorithm model and design using XSG. Image post-processing blocks The pre-processing and post- processing units that transmit the image into the suitable standard of image processing for next unit are also given by Simulink blocks. Those units were described in [11]. The image-processing algorithm designed by Xilinx blocks proposed design flow of hardware implementation of image processing as given in figure 2. Figure 2. Design flow of hardware implementation of image processing 4. Study Case: Digital Image Processing (Contrast Stretching & Segmentation by Thresholding) A. Algorithm for Image Contrast Stretching Contrast Stretching: is an image enhancement technique that improves the contrast in an image by stretching the range of intensity values it contains to span a desired range of values [12]. For example, consider the enhancement of an image whose data numbers (DN) are integers that range between DN min and DN max as shown in figure 3. Figure 3. Histogram of unstretched image 713

4 Mohammed Alareqi, et al. International Journal on Electrical Engineering and Informatics - Volume 7, Number 4, Desember 2015 Figure 4. Algorithm for color image contrast stretching 714

5 Real Time Hardware Co-Simulation for Image Processing Algorithms To stretch a histogram of an image that has low contrast, a contrast-stretching algorithm is applied to such image to enhance that image by using a linear function as Out RGB =3[In RGB - DN max ] + DN min (1) Out RGB =3[In RGB - DN min ] + DN max (2) Where; Out RGB : output image, In RGB : input image, DN max : value max in histogram of input image and DN min : value min in histogram of input image. This paper applied the algorithm for image contrast stretching that is shows in Figure 4. This algorithm aims to increase the dynamic range of input image which has histogram as shown in Figure 8-a. The result featured when applied the algorithm by using Equation (1) as show in Figure 8-b. It means that the histogram stretches in dark region. Another result when using Equation (2) is show in Figure 8-c. It means that the histogram expands in bright region. B. Algorithm for Image Segmentation Thresholding Image threshold technique is one of the important techniques in image segmentation. This algorithm produces binary image that represent objects and their background, which then help interpreting the content of the considered image [13]. This technique can be expressed as: T=T[x, y, p(x, y), f(x, y)] (3) Where; T is the threshold value. x,y are the coordinates of the threshold value point. P(x,y) and f (x,y) are points of the gray level image pixels. Threshold image g(x,y) can be defined: Thresholding segmentation involves separating an image into regions (or their contours) corresponding to objects. We usually try to segment regions by identifying common properties. Similarly, we can identified contours by identifying differences between regions. The simplest property that is shared by pixels in a region is their intensity. Therefore, a natural way to segment these regions is by thresholding, the separation of bright and dark regions. This is what we applied in this paper by using the image-processing algorithm designed by Xilinx blocks as shown in figure 5. (4) 715

6 Mohammed Alareqi, et al. Figure 5. Algorithm for image segmentation by thresholding 716

7 Real Time Hardware Co-Simulation for Image Processing Algorithms International Journal on Electrical Engineering and Informatics - Volume 7, Number 4, Desember Hardware Co-Simulation (a). Segmentation by thresholding 717

8 Mohammed Alareqi, et al. b. Contrast stretching Figure 6. Complete hardware/software co-simulation design 718

9 Real Time Hardware Co-Simulation for Image Processing Algorithms International Journal on Electrical Engineering and Informatics - Volume 7, Number 4, Desember 2015 System Generator provides hardware co-simulation, making it possible to incorporate a design running on an FPGA directly into a Simulink simulation "Hardware Co-Simulation". Using hardware co-simulation, we can select a subsystem in a System Generator model to run in hardware while the rest of the model is simulated on a host PC [10]. Hardware co-simulation block was generated without any errors and the processing speed and hardware resources were obtained using the synthesis ISE implementation tool. Figs.8&10, show that there is almost no difference between the results obtained from MATLAB and FPGA JTAG communication. Figure 6, shows the models with the JTAG-based hardware co-simulation block implemented on Virtex 5 platform (Virtex5 XUPV5-LX110T). 6. Implementation and Results Image contrast stretching and Image segmentation thresholding algorithms, are designed in MATLAB and Simulink (system generator) and they are implemented on Virtex-5 FPGA as shown in the Figure 7. All steps start by generating the Simulink model for the system using Simulink blocks in MATLAB until it get downloaded to FPGA. Figure 7. Design and implementation flow Table 1, shows in details the resource requirements of the contrast stretching design. Note that in practice, additional blocks are needed for input/output interfaces and synchronization. Table 1. Device Utilization Summary (Estimated values) for Contrast stretching design 719

10 Mohammed Alareqi, et al. Figure 8 shows the software and hardware simulations for the Contrast stretching design for the input image. The obtained result when the algorithm is applied by using Equation (1), is shown in Figure 8-b. It shows that the histogram stretches in dark region. Another result is obtained when using Equation (2) is shown in Figure 8-c. It shows the histogram expands in bright region. Both results revealed that, there is no difference between those obtained from MATLAB and FPGA. Figure 8. a) Original image b) XSG based contrast stretching by using equation1 c) XSG based contrast stretching by using equation2 The Top-level RTL schematic for the contrast stretching algorithm developed and implemented on FPGA is shown in Figure 9. This is a schematic representation of the preoptimized design shown at the Register Transfer Level (RTL).This system blocks are designed for the Virtex-5 ML505 board. Figure 9. RTL schematic for Image contrast stretching 720

11 Real Time Hardware Co-Simulation for Image Processing Algorithms Table 2. Details of the resource requirements of the segmentation by thresholding design Figure 10. Shows the software and hardware simulation for the segmentation by thresholding design for the input image. It also shows that there is no difference between the results obtained from MATLAB and FPGA. Figure 10. a) Original image b) XSG based segmentation by thresholding c) FPGA based segmentation by thresholding The Top-level RTL schematic for the segmentation by thresholding algorithm is developed and implemented on FPGA as shown in figure 11. Figure 11. RTL schematic for image segmentation by thresholding 721

12 Mohammed Alareqi, et al. 7. Conclusion The objective of this paper was to demonstrate the use of System Generator for implementing the digital image processing algorithms on a FPGA. Since it does not require a previous knowledge of hardware design methodologies, also has the advantage of using large memory, and embedded multipliers. Advances in FPGA technology with the development of sophisticated and efficient tools for modeling, simulation and synthesis have made FPGA a highly useful platform. Flexible and reasonable use of DSP building blocks provided in the XSG can easily turn the flowchart of algorithm into a corresponding implement on FPGA. 8. References [1]. A. R.Arreguína, J. C. M. Moralesa, J. M. R.Arreguín, J. C. P.Ortegaa, S. T.Arriagaa, M.A.A. Fernandeza and J. d. J. R.Magdalenob, "FPGA Open Architecture Design for a VGA Driver," Iberoamerican Conference on Electronics Engineering and Computer Science,vol.3, pp , 3 ( 2012 ). [2]. N. Kehtarnavaz and S. Mahotra, "FPGA implementation made easy for applied digital signal processing courses," Acoustics, Speech and Signal Processing (ICASSP), 2011 IEEE International Conference on, vol., no., pp , May [3]. M.Ownby and W.H. Mahmoud, "A design methodology for implementing DSP with Xilinx System Generator for Matlab," System Theory, Proceedings of the 35th Southeastern Symposium on, vol., no., pp , March [4]. A. Mohammed, E. Rachid, and H. Laamari, High Level FPGA Modeling for Image Processing Algorithms Using Xilinx System Generator, International Journal of Computer Science and Telecommunications, Vol.5, Issue 6, pp.1-8, June [5]. S. Hasan, A. Yakovlev, and S. Boussakta, Performance efficient FPGA implementation of parallel 2-D MRI image filtering algorithms using Xilinx system generator, IEEE International Conference on Communication Systems Networks and Digital Signal Processing (CSNDSP), pp , July2010. [6]. R.Harinarayan, R. Pannerselvam, M. Mubarak Ali, and D. Kumar Tripathi, Feature extraction of Digital Aerial Images by FPGA based implementation of edge detection algorithms, IEEE International Conference on Emerging Trends in Electrical and Computer Technology (ICETECT), pp , March [7]. C.JohnMoses, D.Selvathi, S.Sajitha Rani, FPGA Implementation of an Efficient Partial Volume Interpolation for Medical Image Registration, IEEE International Conference on Communication Control and Computing Technologies (ICCCCT-10), pp , Oct [8]. M.F. Bin Othman, N. Abdullah, and N.A. Bin Ahmad Rusli, An Overview of MRI Brain Classification using FPGA Implementation, IEEE Symposium on Industrial electronics & Applications (ISIEA),pp , Oct [9]. H. Taha, A.N.Sazish, A.Ahmad, M. S.Sharif, and A. Amira, Efficient FPGA Implementation of a Wireless Communication System Using Bluetooth Connectivity, IEEE International Symposium Circuits and Systems (ISCAS), pp , June [10]. Xilinx System Generator User's Guide, x.com. [11]. P.H. Pawar and R. P. Patil, FPGA Implementation of Canny Edge Detection Algorithm, International Journal of Engineering and Computer Science, Vol. 3, PP , Issue 10, October 2014 [12]. Kalpit R.Chandpa, Ashwini M. Jani, Ghanshyam I. Prajapati, Comparative Study of Linear and Non-linear Contrast Enhancement Techniques, International Journal of Research and Scientific Innovation, Vol. I,PP Issue VI, November [13]. Salem Saleh Al-amri, N.V. Kalyankar and Khamitkar S.D, Image Segmentation by Using Threshold Techniques Journal of Computing, vol. 2, issue.5, PP may

13 Real Time Hardware Co-Simulation for Image Processing Algorithms Mohammed Alareqi was born in Taiz, Yemen in He received the B.S in Applied Physics from University of Technology, Baghdad, Iraq and M.S degree in microelectronics in 2010 from University of Ibn Tofail, Kenitra, Morroco. He is the PhD student and staff member of laboratory electrical engineering and energy systems, Ibn Tofail University, Kenitra Morroco. Rachid Elgouri is a Professor in the National School of Applied Sciences at Ibn Tofail University in Kenitra, Morocco. His research interests in electrical engineering and renewable energy include the modeling and design optimization of renewable energy systems, the development of microelectronic energy management systems and power electronic converters for renewable energy sources applications and the development of sensors and electronic measurement systems and information security. Khalid Mateur received his master degree in microelectronics in 2011, now he is PHD student and member of laboratory electrical engineering and energy systems, Physics department, Faculty of Science, Ibn Tofail University, Kenitra Morroco... Laamari Hlou is the Director of Laboratory electrical engineering and energy systems, Physics department, Faculty of Science, Ibn Tofail University, Kenitra Morroco. His research interests in Electrical Engineering and renewable energy include the modeling and design optimization of Renewable Energy systems, the development of microelectronic Energy Management Systems and power electronic converters for Renewable Energy Sources applications and the development of sensors and electronic measurement systems and information security. 723