EDA365. DesignCon Impact of Backplane Connector Pin Field on Trace Impedance and Vertical Field Crosstalk

Transcription

1 DesignCon 2007 Impact of Backplane Connector Pin Field on Trace Impedance and Vertical Field Crosstalk Ravi Kollipara, Rambus, Inc. (650) Ben Chia, Rambus, Inc. Dan Oh, Rambus, Inc. Chuck Yuan, Rambus, Inc. Luis Boluña, Cisco Systems, Inc.

2 Abstract The signal integrity effects of lowered impedance and induced crosstalk are well understood when signals traverse through the PTH vias. However, the signal integrity impact on trace impedance and crosstalk in the vertical direction between the traces in the adjacent stripline layers are not well understood when signals are simply passing through a given connector pin field region. These effects are present because of the lack of full ground cover for the stripline signal traces in the pin field region due to the large antipads for the PTH vias. This paper addresses the impact of these effects on the system margins. Both single ended and differential connector pin fields are considered. Author(s) Biography Ravi Kollipara is a Senior Principal Engineer responsible for the signal integrity of high speed serial link and parallel bus channels. His duties include design and characterization of packages, line cards and backplanes, and modeling of channel components. He has been with Rambus since 1998 and has a Ph.D. degree in Electrical Engineering from Oregon State University. Ben Chia is a signal integrity engineer responsible for design, modeling and simulation of high speed PCBs and package designs. He received his B.S.E.E from Taipei Institute of Technology in 1980 and M.S.E.E. from Rensselaer Polytechnic Institute in Dan Oh is an Engineering Manager at Rambus Inc. He is currently responsible for the signal integrity analysis and tool development for various I/O channels. Previously, he was a developer at Synopsys where he implemented several signal integrity features in HSPICE and other on-chip parasitic extraction tools. Dr. Oh received his Ph.D. degree from the Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign in Chuck Yuan is an Engineering Manager at Rambus leading a team of SI engineers focused on high speed backplane and memory systems. He joined Rambus in 1998 and holds a Ph.D. in Electrical Engineering from Syracuse University. Luis Boluña is currently a Technical Leader for Cisco Systems, Inc. During his 6+ years at Cisco, Luis has been involved in a variety of projects in support of cutting edge high speed signaling designs. He has contributed in the development of high speed system simulation and metrology. Mr. Boluna holds a Bachelors of Science in Electrical Engineering from the University of California, Santa Barbara with emphasis in Solid State. He has 7 years previous experience in Analog and Mixed Circuit Design. Prior to joining Cisco he worked for National Semiconductor, was Member of the Technical Staff at both ASL Technology and Rambus.

3 I. Introduction As data rates increase, attenuation, crosstalk and reflections increase and careful accounting of all the signal integrity effects are needed to ensure adequate system margins at low (<=10-15 ) bit error rates. Press-fit connectors are widely used in the design of high speed backplanes. As a result, the backplane and line/switch card PCBs have large plated through hole (PTH) vias to accommodate these connectors. The signal integrity effects of lowered impedance and induced crosstalk are well understood when signals pass through the PTH vias while transitioning from the connector pins to various signal layers in the backplane. For example, consider the footprint of the HM-Zd backplane connector, which is widely used in ATCA and XAUI systems. The pin out of a 12 layer, 120 mil thick dual-star ATCA FR4 backplane is shown in Figures 1 [1]. Fig.1 Pin out of an ATCA backplane system. The measured impedance profile and the worst case near-end crosstalk (NEXT) and farend crosstalk (FEXT) S-parameters for the longest backplane differential pair trace length are plotted in Figures 2 and 3, respectively. The differential pair length is 10.6 and is routed in the bottom strip line layer 11. The backplane via stub length for the bottom strip line routed pair is quite small (~ 10 mil), yet the impedance drops to 77 ohms when the signal is transitioning to the bottom layer through the vias. In fact, the true differential impedance of the via pair is below 60 ohms which can be measured with a faster TDR edge or probing the via pair of a much thicker backplane that is routed to the bottom stripline layer [2]. The VNA measured crosstalk is shown in Figure 3(a). The plotted NEXT is between the aggressor pair (A2, B2) and victim pair (C2, D2). The simulated crosstalk in the time domain is plotted in Figure 3(b) for a step risetime of 50ps which is close to the risetime expected for a 6.25Gbps data rate. Both crosstalks are ~ 0.9%. The crosstalk sources are the aggressor s connector pins as well as the backplane and line/switch card vias. The FEXT can not be separated into its component sources but NEXT can be separated into its component sources for a fast rise time and short probing distance. The crosstalk due to the vias depends on the via coupling length.

4 Fig.2 TDR impedance profile of an ATCA backplane. (a) (b) Fig.3 (a) Plot of through and worst case NEXT and FEXT S-parameters. (b) Expected FEXT and NEXT in time domain for a rise time of 50 ps. The signal integrity impact on trace impedance and crosstalk in the vertical direction between the traces in the adjacent stripline layers when signals are simply passing through the connector pin field region is not significant provided the stripline layers have adequate ground cover. The routing in the differential and single-ended connector pin fields is shown in Figure 4 where there is adequate ground cover for the stripline traces.

5 Typically, the differential anti-pad is enlarged to improve the differential via impedance, as shown in Figure 4(a), making sure that there is adequate ground cover under all manufacturing conditions. (a) Fig.4 Typical trace routing in (a) differential connector pin field and (b) singleended connector pin field with adequate ground cover for stripline traces. For differential connectors, the two traces of the differential pair can be routed together between two connector column vias, as shown in Figure 4(a), thus preserving the differential coupling. However, for legacy backplanes using single ended connectors, the differential traces have to be routed single-ended in the connector pin field area, as shown in Figure 4(b), since the routing space between the vias is too narrow to allow for differential routing. For differential connectors, designers are looking at increasing the routing density by routing two differential pairs between two connector column vias as shown in Figure 5(a). This cuts the backplane layer count by nearly half and may eliminate the need for back-drilling. The via impedance of a single ended connector is typically lower than 50 ohms. The single-ended connector pin field routing shown in Figure 5(b) can be a result of a large anti-pad to improve the via impedance, or a wider trace width to minimize the conductor loss, especially in lower loss dielectric materials. (b) (a) (b) Fig.5 (a) Routing of two differential pairs between connector columns (b) Singleended connector pin field routing with no ground cover beyond the stripline traces.

6 When two differential pairs are routed between connector columns, the crosstalk between the differential pairs is managed by maximizing the spacing between the differential pairs. This is achieved by minimizing the size of the anti-pad and placing the outer stripline trace of the differential pair at the edge of the anti-pad. In addition, the stripline trace widths are also narrower resulting in larger conductor loss. This paper presents an analysis of the PCB trace crosstalk that occurs between the adjacent stripline layers in the connector pin field of high speed backplanes when the traces are routed as shown in Figure 5. In addition, the impedance of the traces is also affected by the amount of ground cover present when the traces pass through the connector pin field region which in turn impacts the link insertion loss. This modulation of the insertion loss due to the periodic nature of the anti-pads is well covered in [3]. This paper also looks at the impact on the impedance when the differential traces pass through the connector pin field region of a single ended connector. Section II covers the PCB manufacturing variations and how these variations can contribute to vertical or Z-field crosstalk between adjacent stripline layers. Section III presents the modeling results of Z-field crosstalk using 3-D EM solvers and section IV covers the measurement of Z-field crosstalk on a randomly selected backplane. Section V addresses the impact of routing differential pairs through a single-ended connector pin field on differential impedance and Section VI concludes the paper with a summary. II. PCB Manufacturing Tolerances The amount of crosstalk between traces on different layers for the pin field routing shown in Figure 5 is a strong function of the manufacturing tolerances. This type of crosstalk is inherently 3D in nature and has not been studied in detail in the past. Typically, the tolerance of layer-to-layer registration is much worse for the traces on different cores. The assumed worst case PCB tolerances that are applicable to a backplane footprint are listed in Table 1. In addition to these, the other manufacturing tolerances for trace widths, trace thicknesses, dielectric heights, dielectric loss tangent and dielectric constant could also be considered. Table 1 Assumed worst case PCB manufacturing tolerances that are applicable to a backplane footprint region. Figure 6(a) shows the nominal pin field cross-section and Figure 6(b) shows the crosssection under the worst case PCB manufacturing tolerances listed in Table 1. The Z-field crosstalk in the nominal case is mitigated to a large extent by the presence of ground

7 plane cover in the adjacent layers starting at the strip line edges. This is no longer the case when the worst case manufacturing tolerances are considered. The middle stripline trace is exposed to both the top and bottom traces of the adjacent stripline layers, though the exposure is predominantly on one side. This results in increased Z-field crosstalk on the middle victim pair from the aggressor pairs of the top and bottom striplines. If the trace width is small (4 to 6 mil), the stripline trace may not have any ground cover on one side of the stripline. This not only increases Z-field crosstalk but also affects the differential trace impedance. (a) Fig.6 (a) Nominal pin field cross- section and (b) worst case pin field cross- section. III. Modeling of Z-Field Crosstalk The backplane footprints shown in Figure 5 are modeled using a full-wave 3D field solver. The worst case manufacturing tolerances listed in Table 1 are applied to the footprint region. The modeled geometry of the differential footprint is shown in Figure 7. A total of four differential pairs are included in the model with two pairs in one stripline layer and the other two in the next stripline layer. The scattering parameters are simulated for the 16-port network from which both NEXT and FEXT in the Z (vertical) direction as well as horizontal direction can be obtained. Figure 8 shows the simulated differential S- parameter plots of the Z-field as well as the horizontal (H-field) crosstalk. The crosstalk can also be plotted in time domain for selected riestimes. Figure 9 shows the Z-field crosstalk in time domain for 50 ps and 25 ps risetimes. For the 25 ps risetime case, the NEXT plot is resolved and shows the contribution to the NEXT from each of the four differential oval anti-pads considered in the modeling. The peak value of Z-field NEXT is comparable to the peak value of NEXT resulting from the connector pins and vias shown in Figure 3(b). For the 50 ps risetime case, the NEXT is averaged out to about 60% of the peak NEXT at 25 ps. The NEXT pattern repeats if the traces pass through another connector pin field with a time separation that depends on the spacing between the pin fields. However, the peak amplitude is not expected to increase beyond that shown in Figure 9. The Z-field FEXT is smaller in magnitude (~55%) compared to that of the FEXT resulting from connector pins and vias shown in Figure 3(b). However, FEXT is proportional to the coupling length and hence it is expected to increase if the traces pass through another connector pin field. In addition, the FEXT shown in Figure 3(b) is the accumulated crosstalk from two backplane connector and via transitions. (b)

8 Fig.7 Modeled geometry of the differential connector footprint. Fig.8 Plot of the simulated NEXT and FEXT for the differential connector footprint.

9 Fig.9 Plot of the simulated NEXT and FEXT in time domain for the differential connector footprint. The modeled geometry of the single-ended connector footprint is shown in Figure 10. Figure 11 shows the simulated differential S-parameter plots of the Z-field NEXT and FEXT. The magnitude of this crosstalk is comparable to the typical crosstalk resulting from the single-ended connector and via transitions. Figure 12 shows the Z-field crosstalk in time domain for 50 ps and 25 ps risetimes. For the 25 ps risetime case, the NEXT plot is beginning to show the contribution to the NEXT from each of the four single-ended circular anti-pads considered in the modeling. The single-ended connector s circular antipad is significantly smaller than the differential connector s oval anti-pad. The NEXT plot for the 50 ps risetime case is smoothed out compared to that of the 25 ps case. However, the peak value of the NEXT is unaffected. The NEXT pattern repeats if the traces pass through another connector pin field but the peak amplitude stays the same. The Z-field FEXT magnitude roughly scales with the risetime. The peak value of FEXT also goes up if there are more than four connector pins per connector slot or if the traces pass through another connector pin field.

10 Fig.10 Modeled geometry of the single-ended connector footprint. (a) Fig.11 Plot of the simulated differential (a) NEXT and (b) FEXT in db for the single-ended connector footprint. (b)

11 Fig.12 Plot of the simulated NEXT and FEXT in time domain for the single-ended connector footprint. IV. Z-field Crosstalk Measurement The Z-field near-end crosstalk of a randomly selected single-ended connector backplane is measured with a 10ps edge TDR. The TDR signal is launched using an SMA paddle card and the crosstalk is picked up on another SMA pair on the same paddle card. The connector pins chosen for launching the TDR signal and for picking up the NEXT are far apart so that there is no significant coupling induced from either the aggressor s connector pins or its backplane and line/switch card vias on to the victim s connector pins and vias. However, the victim and aggressors differential pairs are routed in neighboring stripline layers and they pass through a connector pin field in the backplane. Hence, if there is any z-field coupling between the aggressor and victims differential pairs, it should be picked up by the victim s pair and the location of the coupling can be verified since NEXT can be resolved in time. The waveforms recorded from the TDR base are shown in Figure 13. The top waveform shows the plot of the differential TDR signal of the aggressor s link. The SMA launch point and the two backplane connectors interconnecting the PCB backplane traces to the switch and line card PCB traces can be clearly seen. The differential Z-field NEXT measured at the victim s SMA pins is shown in the bottom waveform. Both the aggressor and victims SMA hook ups are on the same paddle card and all the links on the paddle cards have the same trace length. The Z-field NEXT signal is picked in a region of the backplane trace closer to the right side of the aggressor s backplane connector. This is because the aggressor and victim s pairs pass through the connector pin-field that is to the left of the aggressor pair s right backplane connector. This verifies that the measured

12 NEXT is indeed due to the Z-field crosstalk. The magnitude of the crosstalk is about 1 mv which translates into about 0.25% considering the TDR differential swing of 400 mv. The risetime of the aggressor pair at the location of the Z-field coupling will be well above the SMA launch risetime of 10 ps due to significant dispersion resulting from conductor and dielectric losses of the paddle card and backplane PCB traces and connectors. In addition, the induced NEXT has to travel all the way back to the paddle card s victim SMA pair. Hence, the 0.25% number needs adjustment for the TDR signal s attenuation and risetime degradation, and the attenuation of induced crosstalk for travel from the induced point to the measurement point to be compared against the simulated worst case crosstalk shown in Figure 12. Since the backplane is a randomly selected one, the exact process variations that its footprint went through during the fabrication are not known. Nevertheless, the measurement verifies the presence of the Z- field crosstalk. Fig.13 Plots of the measured differential Z-field NEXT (bottom waveform), true and complement of Z-field NEXT (middle waveforms) and TDR of the aggressor link (top waveform). V. Impact of Single-Ended Routing on Impedance In general, when a differential pair is routed through the connector pin field of a single ended connector, the differential pair is forced to split up so it can be routed through the pin field as shown in Figure 4(b). This affects the differential impedance and may also result in increased crosstalk from the signals routed through the neighboring routing

13 channels within the same stripline layer. The nominal case impedance in the pin field of a single ended connector where the ground cover ends at the edge of the stripline is simulated and plotted in Figure 14. The impact here is not significant because the differential pair is not strongly coupled even outside the connector pin field region. However, the impact increases if the differential pair is strongly coupled. In addition, this impact gets only worse if there is not adequate ground cover for the stripline when manufacturing variations are taken into account. Fig.14 The change in the differential impedance when a differential pair is routed through a single-ended connector pin field. VI. Summary The Z-field crosstalk is simulated both for the differential and single ended backplane connectors taking the worst case PCB manufacturing variations into account. The magnitude of this crosstalk is comparable to that induced by the backplane connector and via combination. The simulations considered induced Z-field crosstalk from one side of the strip line layer only. There can be additional Z-field crosstalk from the other side also, as shown in Figure 6(b), though it may not be as large as the worst case single sided crosstalk considered in the simulation. Measurements performed on a random backplane confirmed the presence of Z-field crosstalk. In addition, when a differential pair is routed through the connector pin field of a single ended connector, an impedance mismatch is created and the magnitude of the mismatch depends on the strength of the differential coupling outside the connector pin field. The impedance mismatch is periodic in nature due to routing in and out of backplane connector pin field which induces notches in the link transfer functions [3]. In summary, backplane system designers are considering lowering the layer count and PTH via length by routing two differential pairs between two connector columns. The

14 designers are also attempting to bring up the backplane PTH via impedance closer to the nominal impedance of the channel by enlarging the anti-pads of both the differential as well as the single ended backplane connectors. However, aggressive trace routing and anti-pad designs in the backplane connector pin field could contribute to the Z-field crosstalk and impedance discontinuities when volume PCB manufacturing tolerances are considered. Both the crosstalk and the insertion loss notches induced by the periodic impedance discontinuities impact the system margin. Designers need to set the trace routing rules by taking the PCB manufacturing tolerances into the consideration. These design rules can be part of the backplane design check list. However, if the design space is tight, the worst case crosstalk and insertion loss should be simulated based on the PCB design tolerances and adequate system margins should be ensured at the three sigma corners for low BER operation. Acknowledgement The authors would like to thank Sergio Camerlo for facilitating helpful discussions on accurately modeling the high speed backplane interconnects, and in particular, for stressing the need to model the crosstalk from all the sources. References [1] Ravi Kollipara et al. Practical Design Considerations for 10 to 25 Gbps Copper Backplane Serial Links, presented at the DesignCon2006, 8-WP1, Santa Clara, CA. [2] Ravi Kollipara and Ben Chia, Modeling and Verification of Backplane Press-fit PTH Vias, presented at the DesignCon2004, 8-WP2, Santa Clara, CA. [3] Gustavo Blando et al. Attenuation in PCB Traces Due to Periodic Discontinuities, presented at the DesignCon2006, 8-TP2, Santa Clara, CA.