Procedures for Folding Transformations

Transcription

1 Procedures for Folding Transformations Marjan Gušev 1 and David J. Evans 2 1 Kiril i Metodij University, PMF Informatika, p.f.162, Skopje, Macedonia 2 PARC, University of Technology, Loughborough, LE11 3TU, UK Abstract. Folding transformations on processor arrays result in smaller processor arrays, more efficient work for the processing elements, a decrease in I/O time and pipelineable implementations. The regular folding procedure is realized to improve the efficiency of processor arrays whilst retaining the complexity of the data communications, the processor operations and the regular data flow. The efficiency analysis shows that the implementation obtained utilizes the processor array with double efficiency. Moreover by using the same processor array problems with double dimension can be solved. Also the circular data flow can be used for cascaded algorithms. 1 Introduction The idea of more efficient exploitation of parallelism is currently evolving through different stages, since 1978, when H.T.Kung and C.S.Leiserson introduced systolic arrays, [1]. Some implementations of folding transformations on processor arrays to improve these designs were considered by Megson and Evans in [2], Choffrut and Culik in [3], Yaacoby and Cappello [4] and by the authors in [11, 10]. All these implementations either use processors with irregular data flow or the complexity of the processor operation and communication is increased. Robert in [5] used translation besides it is declared as a folding transformation. The data dependence method is based upon the techniques developed for processor array implementation by Moldovan and Fortes [6], Quinton [7], S.Y.Kung [8] etc., The complete analysis and comparison of the procedures for algorithm implementation on processor arrays, and the notation used in this paper can be found in [9]. In this paper we will analyse the graphs of the algorithm model. Definition 1. A dependence graph (DG) is a directed graph G whose vertices are equal to the points of the index set of the algorithm and edges equal to the data dependence vectors for each vertex in G. The space allocating function S : J J q maps the algorithm index set J into a processor index set J q. According to the definition of the timing function as t : J Z, the set Z T is the codomain of t, i.e. the set of all timing moments needed for algorithm execution. Denote by U the set Z T J q i.e. the set of all processor cells defined for all time moments. The data dependence method maps the algorithm index set by a function T = (t, S) defined by T : J U, where t is a timing function and S is a space function. Therefore the function T maps the DG into a graph defined by

2 Definition 2. Space time graph (STG) is a graph with set of vertices V = { v i } and edges identifying the data flow of variables between the vertices, where v i = (t, x 1, x 2,..., x q ) U = Z T J q, are the vertices identified by a processor cell and a time moment, Z T is a set of time moments t needed for the algorithm execution and (x 1, x 2,..., x q ) J q is a cell in the processor array index set. Definition 3. The set of active cells is the set of STG vertices V (the processor cells) to which the computation are mapped. The complement V of the set V according to U is the set of inactive cells. The previous definition determines the sets of active and inactive cells in STG. The conditions of a valid transformation of a DG to STG are given by the following lemma. Lemma 4. A DG is mapped to a valid STG by a valid timing function t and a valid space allocating function S iff the following conditions are fulfilled: (i) Timing condition All nodes from STG have a positive time coordinate, i.e. they are positioned in the positive halfspace of the time coordinate. (ii) Regular data flow condition All edges have a direction upwards, i.e. the edges in the horizontal direction or the edges in the downward direction are not allowed. (iii) Space time condition No two point are overlapped (covered), i.e. the mapping must be injective. (iv) Multiple data flow condition All edges should form an angle with the time axis not greater then 45 o 2 Folding Transformations The folding is defined in [4] as a m-fold transformation and in [3] as a 2-fold reflection and here will be analyzed on space time graphs. Definition 5. A folding transformation of a graph G according to a hyperplane of symmetry P, that partitions G into two subsets G + and G, is a partitioned linear transformation T = { T +, T }, where T + : G + G + is an identity mapping and T : G G + is a symmetric mapping according to P. Theorem 6. A folding transformation on a STG according to a hyperplane of symmetry P does not result in a valid STG. Theorem 6 proved in [10] shows that folding according to the line of symmetry in a STG results in a irregular space time condition. Many authors tried to solve this problem [2, 3] introducing retiming and reallocation but the proposed solutions have irregular data flow. The following theorem proved in [10] shows a folding transformation that results in a valid STG denoted as regular folding.

3 Definition 7. A translation applied to the set of the STG active cells V, by a vector r, is an interlocking translation if V is mapped into a set W, such that W V is a subset of the set of the STG inactive cells. Theorem 8. A folding transformation applied on a STG with a plane of symmetry P and a vector of interlocking translation r, according to the plane P, obtained by the translation of P by a vector r/2 results in a valid STG. It was shown in [10] that the best regular folding is achieved from the plane of maximum symmetry and the minimal norm interlocking vector. However this is not the only criteria, since the processor complexity and communication must be also considered, so the following procedure is proposed: 1. Map the dependence graph into a STG (by linear transformations). 2. Choose the plane achieving maximum symmetry on the time axis. 3. Analyze the interlocking properties and choose the minimum norm vector. 4. Analyze the processor operation and communication complexity. These four steps realize the Regular Folding Procedure (RFP) which will be analyzed on the Kung Leiserson bidirectional linear systolic array for matrix vector multiplication since it possesses all the required symmetric and interlocking properties. Among the four planes of symmetry, the maximum symmetry the folding line the line of symmetry a) before folding b) after folding Fig. 1. Regular folding of the matrix vector multiplication. achieves x = 0. The minimum norm vector of the interlocking translation is x = 1. Therefore the best regular folding is obtained by folding according the plane x = 1/2 as shown in Fig. 1, which results in an array shown in Fig. 2. The communication links are mapped in the existing opposite links and the processor operation includes switching of the inputs which is realized as a SIPS cell.

4 c out b in c out = c in + b in a in b out = b in or c out = c in b out = b in + c in a in a in c in b out a 33 a 23 a 22 a 12 a 11 a 01 a 00 a 32 a 13 a 21 a 02 a 10 a 31 a 03 a 20 a 30 x 0 y 0x 1 y 1x 2 y 2x 3 y 3 Fig. 2. A new matrix vector multiplication linear array obtained by regular folding. Conclusions The efficiency analysis shows 100% improvement in processor utilization. Folding transformations on processor arrays result in 50% smaller processor arrays, more efficient work for the processing elements, a decrease in I/O time and I/O buffers, pipelineable implementations and circular data flow. The proposed RFP procedure can be efficiently implemented on different algorithms such as linear system solver, convolution, string comparison, digital filters, matrix matrix multiplication, LU or QR decomposition, etc. The main improvement that must be emphasized once again is the use of 40% up to 50% less processors in the same time for the same algorithms. Alternatively this can be formulated as the same systolic (processor) array can be used for algorithms with double the size. References 1. Kung, H.T., Leiserson, C.S.: Systolic arrays (for VLSI). Tech. Rep. CS , Carnegie Mellon University, Pitsburg, PA. (1978) 2. Megson, G., Evans, D.J.: Triangular systolic arrays for matrix product and factorisation. Int. J. Computer Math. 25 (1988) Choffrut, C., Culik, K.: Folding of the plane and the design of systolic array. Inf. Proc. Letters 17 (1984) Yaacoby, Y., Cappello, P.R.: Converting affine recurrence equations to quasiuniform recurrence equations. Tech. Rep. 18 (CA 93106) UCSB Comp. St. (1988) 5. Robert, Y.: Systolic algorithms and architectures. Automata Networks in Computer Science (eds: F. Fogelman-Soulie et al.), Manch. Univ. Press (1987) Moldovan, D.I., Fortes, J.A.B.: Partitioning and mapping algorithms into fixed sized systolic arrays. IEEE Trans. Computers 35 (1986) Quinton, P.: Automatic synthesis of systolic arrays from uniform reccurence equations. Proc. of 11th Ann. Int. Symp. Computer Architecture (1984) Kung, S.Y.: VLSI Array Processors. Englewood Clifs, N.J.: Prentice-Hall (1988) 9. Gušev, M., Tasič, J.: Comparative analysis of methods for broadcast elimination. Parallel Computing 18 (1992) Gušev, M.: Processor array implementations of systems of affine recurrence equations in digital signal processing. PhD thesis, Univ. Ljubljana, Slovenia, (1992) 11. Evans, D.J., Gušev, M.: Implementation of folding transformations on linear systolic or VLSI processor arrays, Parallel Computing 18 (1992)

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