2D-DWT LIFTING BASED IMPLEMENTATION USING VLSI ARCHITECTURE

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1 2D-DWT LIFTING BASED IMPLEMENTATION USING VLSI ARCHITECTURE Joshni C.George, T.Jayachandran, Dr.C.N.Marimuthu Abstract--This paper proposes the design of VLSI architecture for image compression. To perform the process of image compression VLSI architecture is designed using lifting based discrete wavelet transform (DWT) and it is implemented in Spartan 3EDK kit. The lifting based DWT architecture has the advantage of lower computational complexities and higher efficiencies. Through the DWT, signals can be decomposed into different sub bands with both time and frequency information. Traditional DWT architectures are based on convolutions. Then, the second-generation DWTs, which are based on lifting algorithms, are proposed.compared with convolution-based ones; lifting-based architectures not only have lower computation complexity but also require less memory. Here we designed core processor Microblaze and implemented using XILINX platform studio Design suite. The algorithm is written in system C Language and tested in SPARTAN-3 FPGA kit by interfacing a test circuit with the PC using the RS232 cable. In this proposed system, the coprocessor Microblaze is converted into a lifting based DWT architecture. The test results are seen to be satisfactory. It can overcome the shortages in previous works and high speed in processing for higher applications. Index terms Core processor, Discrete wavelet transform (DWT), Lifting scheme, VLSI architecture I.INTRODUCTION Digital image processing is the use of computer algorithms to perform image processing on digital images. As a subcategory or field of digital signal processing, digital image processing has many advantages over analog image processing. It allows a much wider range of algorithms to be applied to the input data and can avoid problems such as the build-up of noise and signal distortion during processing. Since images are defined over two dimensions (perhaps more) digital image processing may be modeled in the form of multidimensional systems. The Discrete Wavelet Transform (DWT) plays a major role in the fields of signal analysis, computer vision, object recognition, image compression and video compression standard. The advantage of DWT over other traditional transformations is that it performs multiresolution analysis of signals with localization both in time and frequency as described by Mallat[14]. At present, many VLSI architectures for the 2-D DWT have been proposed to meet the requirements of real-time processing. The implementation of DWT in practical system has issues. First, the complexity of wavelet transform is several times higher than that of DCT. Second, DWT needs extra memory for storing the intermediate computational results. Moreover, for real time image compression, DWT has to process massive amounts of data at high speeds. The use of software implementation of DWT image compression provides flexibility for manipulation but it may not meet timing constraints in certain applications. The discrete wavelet transform (DWT) is a multiresolution analysis tool with excellent characteristics in the time and frequency domains. Through the DWT, signals can be decomposed into different sub bands with both time and frequency information. The coding efficiency and the quality of image restoration with the DWT are higher than those with the traditional discrete cosine transform. Moreover, it is easy to obtain a high compression ratio. As a result, the DWT is widely used in signal processing and image compression, such as MPEG- 4, JPEG2000, and so on [2], [3]. Traditional DWT architectures [4], [5] are based on convolutions. Then, the second-generation DWTs, which are based on lifting algorithms, are proposed [6], [7]. Compared with convolution-based ones, lifting-based architectures not only have lower computation complexity but also require less memory. Because of such advantages of lifting based method over convolution based one, and to get fast and efficient response, the lifting based method is the better technique in VLSI and signal processing applications. It will also reduce complexities while computation because it has less coefficients than the convolution based method. All Rights Reserved 2013 IJARECE 363

2 Image level 1 level 2 Fig.1.Decomposition of image The DWT can decompose the signals into different sub-bands with both time and frequency information. It also supports features like progressive image transmission, compressed image manipulation, and region of interest coding. Recently several VLSI architectures have been proposed to realize single chip designs for DWT. Traditionally, such algorithms are implemented using programmable DSP chips for low-rate applications, or VLSI application specific integrated circuits (ASICs) for higher rates. In wavelet transforms, the original signal is divided into frequency resolution and time resolution contents. The decomposition of the image using 2-level DWT is shown in Fig.1. In this brief, VLSI architecture is developed to perform the image compression using lifting based DWT method and then it implemented in the Spartan 3EDK kit. Here the core processor microblaze is converted into DWT architecture. The remainder of the paper is organized as follows: Section II reviews the lifting scheme. Section III presents the proposed architecture and hardware implementation of lifting based 2-D DWT, and Section IV provides simulation results. Conclusion is drawn in Section V. II. LIFTING BASED 2D DISCRETE WAVELET TRANSFORM The inherent time-scale locality characteristics of the discrete wavelet transforms (DWT) have established as powerful tool for numerous applications such as signal analysis, signal compression and numerical analysis. This has led numerous research groups to develop algorithms and hardware architectures to implement the DWT. Discrete wavelet transform (DWT) is being increasingly used for image coding. This is due to the fact that DWT supports features like progressive image transmission, ease of compressed image manipulation, region of interest coding etc. level 3 Fig.2.Block diagram of forward lifting scheme The VLSI architectures proposed in for hardware implementations of DWT are mainly convolution-based. In the conventional convolution method of DWT, a pair of Finite Impulse Response filters (FIR) is applied in parallel to derive high pass and low-pass filter coefficients. In the first-level decomposition, the size of the input image is N* N, and the outputs are the three sub bands LH, HL, and HH, of size N/2*N/2. In the second-level decomposition, the input is the LL band and the outputs are the three sub bands LLLH, LLHL, and LLHH, of size N/4*N/4. The implementation of DWT in practical system has issues. First, the complexity of wavelet transform is several times higher than that of DCT. Second, DWT needs extra memory for storing the intermediate computational results. Moreover, for real time image compression, DWT has to process massive amounts of data at high speeds. The use of software implementation of DWT image compression provides flexibility for manipulation but it may not meet timing constraints in certain applications. Hardware implementation of DWT has practical obstacles. First, is that the high cost of hardware implementation of multipliers. Filter bank implementation of DWT contains two FIR filters. It has traditionally been implemented by convolution or the finite impulse response (FIR) filter bank structures. Such implementations require both large number of arithmetic computations and storage, which are not desirable for either high speed or low power image/video processing applications. A. Lifting method The various architectures are analyzed in terms of hardware and timing complexity involved with the given size of input image and required levels of decomposition. This study is useful for deriving an efficient method for All Rights Reserved 2013 IJARECE 364

3 improving the speed and hardware complexities of existing architectures and to design a new hardware implementation of multilevel DWT using lifting schemes. The lifting scheme is a new method to construct wavelet basis, which was first introduced by Swelden s. The lifting scheme[9] entirely relies on the spatial domain, has many advantages compared to filter bank structure, such as lower area, power consumption and computational complexity. The lifting scheme, which is shown in Fig.3.can be easily implemented by hardware due to its significantly reduced computations. Lifting has other advantages, such as in-place computation of the DWT, integer-to-integer wavelet transforms which are useful for lossless coding. The lifting scheme has been developed as a flexible tool suitable for constructing the second generation wavelets. It is composed of three basic operation stages: split, predict and update. Figur.3. shows the lifting scheme of the wavelet filter computing one dimension signal. The three basic steps in Lifting based DWT are, Even values Low pass coefficients Input Split Predict Update Odd values High pass coefficients Fig.3. lifting based method High pass coefficients 1.Splits: where the signal is split into even and odd points, because the maximum correlation between adjacent pixels can be utilized for the next predict step. For each pair of given input samples x(n) split into even x(2n) and odd coefficients x(2n+1). 2.Predict step: The even samples are multiplied by the predict factor and then the results are added to the odd samples to generate the detailed coefficients (dj).detailed coefficients results in high pass filtering Lowpass coefficients o o Update Predict Image output Fig.4. Block diagram of inverse lifting scheme (1) 3.Update step: The detailed coefficients computed by the predict step are multiplied by the update factors and then the results are added to the even samples to get the coarse coefficients (sj).the coarser coefficients gives low pass filtered output. (2) The inverse transform could easily be found by exchanging the sign of the predict step and the update step and apply all operations in reverse order as shown in Fig.4.The implementation of lifting based inverse transform (IDWT) is simple and it involves order of operations in DWT to be reversed. Hence the same resources can be reused to define a general programmable architecture for forward and inverse DWT. The block diagram of the inverse lifting scheme is as shown in Fig.4. High-speed and reduced-area 2-D discrete wavelet transform (2-D DWT) architecture is proposed here. For that the compression of an image using modified lifting based discrete wavelet transform is performed. If we select the input as shown in Fig.5 for image compression, then the outputs after each level of processing is as explained below. All Rights Reserved 2013 IJARECE 365

4 Fig.5.Input image In the lifting based DWT transform, the compressed output image will obtain through the following steps. 1.The input will divide into even and odd functions. Second, the even samples are multiplied by the predict factor. 2.Then the results are added to the odd samples to generate the detailed coefficients (dj).detailed coefficients results in high pass filtering. 3.The detailed coefficients computed by the predict step are multiplied by the update factors and then the results are added to the even samples to get the coarse coefficients (sj).the coarser coefficients gives low pass filtered output. Different levels of image compression can be performed using modified lifting based discrete wavelet transform. After first level of compression the output image will be as shown in Fig.6. After second level of compression the output image will be as shown in Fig.7. After third level of compression the output image will be as shown in Fig.8. The lifting based DWT transform has lower arithmetic complexity than the convolution based DWT transform. Because of this, lifting based method is much faster than the convolution based method. Now, lifting based DWT method is commonly used for signals and image processing. That is in First level of compression the LL,LH,HL,HH bands are produced. Then the second level of compression the LL band again subdivided into four subbands. It is the more compressed image than the first level of compression. The LLLL band in the second level of compression again subdivided into four subbands, which is the more compressed image than the second level of compression. Fig.6. First level of processing Fig.7.Second level of processing Fig.8.Third level of processing III.PROPOSED SYSTEM In this proposed system a VLSI architecture is designed and implemented, which is to perform the image compression with high speed and reduced complexity. For that, the coprocessor Microblaze is converted into lifting based DWT architecture using Xilinx platform studio in system C language and then tested in Spartan 3EDK FPGA kit. RS232 cable is used for interfacing the test circuit with All Rights Reserved 2013 IJARECE 366

5 PC. Instead of convolution based DWT here two dimensional discrete wavelet transform (2D-DWT) lifting based method is used for the designing. This hardware implementation can overcome the shortages of previous works not only that it can achieve high speed in computation and low power consumption also. A.Microblaze processor design The MicroBlaze embedded soft core is a reduced instruction set computer (RISC) optimized for implementation in Xilinx field programmable gate arrays (FPGAs). See Fig.9. for a block diagram depicting the MicroBlaze core.field-programmable gate arrays (FPGA'S) are flexible and reusable high-density circuits that can be easily re-configured by the designer, enabling the VLSIdesign / validation /simulation cycle to be performed more quickly and less expensive. Increasing device densities have prompted FPGA manufacturers, such as Xilinx and Altera, to incorporate larger embedded components, including multipliers, DSP blocks and even embedded processors. One of the recent architectural enhancements in the Xilinx Spartan, Virtex family architectures is the introduction of the MicroBlaze (Soft IP) and PowerPC405 hard-core embedded processor. B.Xilinx platform studio The Xilinx Platform Studio (XPS) is the development environment or GUI used for designing the hardware portion of your embedded processor system. B. Embedded Development Kit Xilinx Embedded Development Kit (EDK) is an integrated software tool suite for developing embedded systems with Xilinx MicroBlaze and PowerPC CPUs. EDK includes a variety of tools and applications to assist the designer to develop an embedded system right from the hardware creation to final implementation of the system on an FPGA. System design consists of the creation of the hardware and software components of the embedded processor system and the creation of a verification component is optional. A typical embedded system design project involves: hardware platform creation, hardware platform verification (simulation), software platform creation, software application creation, and software verification. Base System Builder is the wizard that is used to automatically generate a hardware platform according to the user specifications that is defined by the MHS (Microprocessor Hardware Specification) file. The MHS file defines the system architecture, peripherals and embedded processors]. The Platform Generation tool creates the hardware platform using the MHS file as input. The Microblaze processor is a 32-bit Harvard Reduced Instruction Set Computer (RISC) architecture optimized for implementation in Xilinx FPGAs with separate 32-bit instruction and data buses running at full speed to execute programs and access data from both on-chip and external memory at the same time. An interrupt controller is available for use with the Xilinx Embedded Development Kit (EDK) software tools. The processor will only react to interrupts if the Interrupt Enable (IE) bit in the Machine Status Register (MSR) is set to 1. On an interrupt the instruction in the execution stage will complete, while the instruction in the decode stage is replaced by a branch to the interrupt vector (address Ox 10). The interrupt return address (the PC associated with the instruction in the decode stage at the time of the interrupt) is automatically loaded into generalpurpose register. In addition, the processor also disables Fig.9. Embedded Development Kit Design Flow future interrupts by clearing the IE bit in the MSR. The IE The creation of the verification platform is optional bit is automatically set again when executing the RTlD and is based on the hardware platform. The MHS file is instruction. taken as an input by the Simgen tool to create simulation Due to the advancement in the fabrication technology files for a specific simulator. Three types of simulation and the increase in the density of logic blocks on FPGA, the models can be generated by the Simgen tool: behavioral, use of FPGA is not limited to anymore to debugging and structural and timing models. Some other useful tools prototyping digital circuits. Due to enormous parallelism available in EDK are Platform Studio which provides the achievable on FPGA and the increasing density of logic GUI for creating the MHS and MSS files. Create / Import blocks, it is being used now as a replacement to ASIC IP Wizard which allows the creation of the designer's own solutions in a few applications. Soft cores are technology peripheral and import them into EDK projects. Bitstream independent and require only simulation and timing Initializer tool initializes the instruction memory of verification after synthesized to a target technology. processors on the FPGA. GNU Compiler tools are used for compiling and linking application executables for All Rights Reserved 2013 IJARECE 367

6 each processor in the system. There are two options available for debugging the application created using EDK namely: Xilinx Microprocessor Debug (XMD) for debugging the application software using a Microprocessor Debug Module (MDM) in the embedded processor system, and Software Debugger that invokes the software debugger corresponding to the compiler being used for the processor. C. Software Development Kit Xilinx Platform Studio Software Development Kit (SDK) is an integrated development environment, complimentary to XPS, that is used for C/C++ embedded software application creation and verification. The software application can be written in a "C or C++" then the complete embedded processor system for user application will be completed, else debug & download the bit file into FPGA. Then FPGA behaves like processor implemented on it in a Xilinx Field Programmable Gate Array (FPGA) device. Fig.10.Input image IV. SIMULATION RESULTS Experiments are performed on gray level images to verify the proposed method. These images are represented by 8 bits/pixel and size is 128 x 128. Image used for experiments are shown in below figure. The architectures were implemented in system c and placed and routed on Xilinx spartan3 XC3S200 FPGA, using Xilinx platform studio v.10.1 The input image which is used for the lifting based DWT image compression is as shown in the Fig.10.The measurements used for proposed method are as follows: An often used global objective quality measure is the mean square error (MSE) defined as MSE=((i/p-o/p)^2)/n*m Where, nxm is the number of total pixels. f (i,j) and f(i,j) are the pixel values in the original and reconstructed image. The peak to peak signal to noise ratio (PSNR in db) is calculated as PSNR=Progressive SNR=10log(255^2/MSE)) Usable gray level values range from 0 to 255.And the output image after first level of compression is as shown in Fig.11.Then the DWT transform applied to the first level of compressed image, then we get further compressed image. This is the second level of compressed output image which is as shown in Fig.12. When apply the inverse discrete wavelet transform(idwt) then get the original input image which is as shown in Fig.13. Fig.11.First level compressed output image Fig.12.Second level compressed output image All Rights Reserved 2013 IJARECE 368

7 Fig.13.IDWT image V. CONCLUSION This paper presented an approach towards VLSI implementation of the lifting based Discrete Wavelet Transform (DWT) for image compression. Lifting based DWT implementations have many advantages, and have recently been proposed for the JPEG2000 standard for image compression. Consequently, this has become an area of active research and several architectures have been proposed in recent years. In this paper, we provide a architectures for 2-dimensional DWT. The architectures are representative of many design styles and range from highly parallel architectures. Here a DWT-based reconfigurable system is designed using the EDK tool. Hardware architectures of two dimensional (2-D) DWT have been implemented as a coprocessor in an embedded system. In addition, the hardware cost of this architecture is compared for benchmark images. This type of work using EDK can be extended to other applications of embedded system. REFERENCE [1] Wei Zhang,Zhe Jiang,Zhiyu Gao, and Yanyan Liu, An efficient VLSI architecture for Lifting based discrete wavelet transform, IEEE Trans.Circuits and systems,vol.59,no.3,pp ,Mar [2] G. Xing, J. Li, and Y. Q. Zhang, Arbitrarily shaped videoobject coding by wavelet, IEEE Trans. Circuits Syst. Video Technol., vol. 11, no. 10,pp , Oct [3] S. C. B. Lo, H. Li, and M. T. Freedman, Optimization of wavelet decomposition for image compression and feature preservation, IEEE Trans.Med. Imag., vol. 22, no. 9, pp , Sep [4] K. K. Parhi and T. Nishitani, VLSI architecture for discrete wavelet transforms, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 1, no. 2, pp , Jun [5] P.Wu and L. Chen, An efficient architecture for twodimensional discrete wavelet transform, IEEE Trans. Circuits Syst. Video Technol., vol. 11, no. 4, pp , Apr [6] W. Sweldens, The new philosophy in biorthogonal wavelet constructions, in Proc. SPIE., 1995, vol. 2569, pp [7] I. Daubechies and W. Sweldens, Factoring wavelet transform into lifting steps, J. Fourier Anal. Appl., vol. 4, no. 3, pp , Mar [8] J. M. Jou, Y. H. Shiau, and C. C. Liu, Efficient VLSI architectures for the biorthogonal wavelet transform by filter bank and lifting scheme, in Proc. IEEE ISCAS, May 2001, vol. 2, pp [9] G. Shi, W. Liu, and L. Zhang, An efficient folded architecture for liftingbased discrete wavelet transform, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 56, no. 4, pp , Apr [10] B. F. Wu and C. F. Lin, A high-performance and memoryefficient pipeline architecture for the 5/3 and 9/7 discrete wavelet transform of JPEG2000 codec, IEEE Trans. Circuits Syst. Video Technol., vol. 15, no. 12, pp , Dec [11] Y. K. Lai, L. F. Chen, and Y. C. Shih, A high-performance and memory-efficient VLSI architecture with parallel scanning method for 2-D lifting-based discrete wavelet transform, IEEE Trans. Consum. Electron., vol. 55, no. 2, pp , May [12] C.-T. Huang, P.-C. Tseng, and L.-G. Chen, Flipping structure: An efficient VLSI architecture for lifting-based discrete wavelet transform, IEEE Trans. Signal Process., vol. 52, no. 4, pp , Apr [13] P.-C. Tseng, C.-T. Huang, and L.-G. Chen, Generic RAMbased architecture for two dimensional discrete wavelet transform with linebased method, in Proc. Asia-Pacific Conf. Circuits Syst., 2002, vol. 2, pp [14] C. Xiong, J. Tian, and J. Liu, Efficient architectures for twodimensional discrete wavelet transform using lifting scheme, IEEE Trans. Image Process., vol. 16, no. 3, pp , Mar [15] H. Liao, M. K. Mandal, and B. F. Cockburn, Efficient architectures for 1-D and 2-D lifting-based wavelet transforms, IEEE Trans. Signal Process., vol. 52, no. 5, pp , May [16] C.-Y. Xiong, J.-W. Tian, and J. Liu, A note on flipping structure: An efficient VLSI architecture for lifting-based discrete wavelet transform, IEEE Trans. Signal Process., vol. 54, no. 5, pp , May Joshni C.George,PG Student,ME VLSI Design,Nandha Engineering College,Erode,Tamilnadu,India. T.Jayachandran,AP/ECE Department, Nandha Engineering College,Erode,Tamilnadu,India. Dr.C.N.Marimuthu,Dean/ECE Department,Nandha Engineering College,Erode,Tamilnadu,India. All Rights Reserved 2013 IJARECE 369