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1 28 The McGraw-Hill Companies, Inc. All rights reserved.

2 28 The McGraw-Hill Companies, Inc. All rights reserved. All or Nothing Gate Boolean Expression: A B = Y Truth Table (ee next slide) or AB = Y

3 28 The McGraw-Hill Companies, Inc. All rights reserved. Truth Table - AND Gate B A Y

4 28 The McGraw-Hill Companies, Inc. All rights reserved. QUIZ What is the output of the AND gate? L L? H H? L H? H L? Unique Output: Output HIGH only when all inputs are HIGH.

5 28 The McGraw-Hill Companies, Inc. All rights reserved. Any or All Gate Boolean Expression: A + B = Y Truth Table (ee next slide)

6 28 The McGraw-Hill Companies, Inc. All rights reserved. Truth Table - OR Gate B A Y

7 28 The McGraw-Hill Companies, Inc. All rights reserved. NOT Circuit Gives output that is not the same as the input. Boolean Expression: Y = A or Y = A Double inverting: A = A NOT gate inverts, or complements, or negates

8 28 The McGraw-Hill Companies, Inc. All rights reserved. NOT AND or inverted AND function. Boolean Expression: or A B = Y (A B)' = Y Truth Table (ee next slide)

9 28 The McGraw-Hill Companies, Inc. All rights reserved. Truth Table - NAND Gate B A AND NAND

10 28 The McGraw-Hill Companies, Inc. All rights reserved. NOT OR or Inverted OR Boolean Expression: A + B = Y or (A + B)' = Y Truth Table (ee next slide)

11 28 The McGraw-Hill Companies, Inc. All rights reserved. Truth Table - NOR Gate B A OR NOR

12 28 The McGraw-Hill Companies, Inc. All rights reserved. Known as Exclusive OR Gate Anything but not all Gate Boolean Expression: A B = Y Truth Table (ee next slide)

13 28 The McGraw-Hill Companies, Inc. All rights reserved. Truth Table - XOR Gate B A OR XOR

14 28 The McGraw-Hill Companies, Inc. All rights reserved. Known as the Exclusive NOR Gate The Inverted XOR Boolean Expression: A B = Y or (A B)' = Y or A B = Y Truth Table (ee next slide)

15 28 The McGraw-Hill Companies, Inc. All rights reserved. Truth Table - XNOR Gate B A XOR XNOR

16 28 The McGraw-Hill Companies, Inc. All rights reserved. The NAND as a Universal Gate Universal gate can be used in combination to create any other logic function. horting NAND inputs Example: Yields the NOT logic function A + B Equal to the OR logic function

17 28 The McGraw-Hill Companies, Inc. All rights reserved. Using Inverters to Convert Gates For example:

18 Combinational vs. equential logic circuits Combinatorial logic circuit : Output is determined by input at one moment equential logic circuit : Output is determined by input and current state of the logic circuit equential Logic Circuit input combinational logic circuit feedback memory element output=f(input,state) tate of memory element is determined by input and previous state of the element memory element: flip-flops, latch 28 The McGraw-Hill Companies, Inc. All rights reserved.

19 28 The McGraw-Hill Companies, Inc. All rights reserved. Combinatorial vs. equential logic circuits Combinatorial logic circuits equential logic circuit

20 28 The McGraw-Hill Companies, Inc. All rights reserved. Tools of the Trade for olving Logic Problems Gate symbols Truth tables Boolean expressions Combinational(combinatorial) logic circuits: AND-OR pattern of gates from um-of-products Boolean expression such as: AB + CD = Y AND-OR pattern of gates OR-AND pattern of gates from Product-of-sums Boolean expression such as: (A+B) (C+D) = Y OR-AND pattern of gates

21 28 The McGraw-Hill Companies, Inc. All rights reserved. Logic Circuit From Boolean Expression Example: Draw the AND-OR logic diagram for the Boolean expression: AB + CD = Y tep : OR AB with CD tep 2: Add top AND gate tep 3: Add bottom AND gate

22 28 The McGraw-Hill Companies, Inc. All rights reserved. Boolean Algebra Boolean Postulates P X = or X = P2 = P3 = P4 + = P5 + = P6 = = P7 + = + =

23 28 The McGraw-Hill Companies, Inc. All rights reserved. Basic rules Boolean Algebra. X+=+X=X 2. X = X=X 3. X+=+X= 4. X = X= 5. X+X=X 6. X X=X 7. X X 8. X X 9. X X commutative law. X+Y=Y+X. XY=YX associate law 2. (X + Y) + Z = X + (Y + Z) 3. (XY) Z = X (YZ) distributive law 4. X (Y + Z) = XY + XZ 5. X + YZ = (X+Y)(X+Z) De Morgan's theorem 6. X Y X Y 7. XY X absorptive law 8. X + XY = X 9. X(X+Y) = X Y

24 28 The McGraw-Hill Companies, Inc. All rights reserved. Boolean Expressions um-of-products form: A B + C D = Y Product-of-sums form: (A + B) (C + D) = Y

25 28 The McGraw-Hill Companies, Inc. All rights reserved. Boolean Expressions Minterm A term of a boolean function in sum of products form composed of all input variables For f(w,x,y,z) W XY Z WXYZ minterms W XY Maxterm A term of a boolean function in product of sums form composed of all input variables For f(w,x,y,z) W X Z Not minterms ( W X Y Z ) ( W X Y Z ) maxterms ( W X Y ) ( W X Z ) Not maxterms

26 28 The McGraw-Hill Companies, Inc. All rights reserved. Boolean Expression from Truth Table Write the Boolean expression that describes the logic in this truth table. Truth Table Input Output ABC Y tep : Focus only on the truth table lines with outputs of. tep 2: AND the inputs for these two lines and logically OR the ANDed groups. A B C + A B C = Y Minterm Boolean expression: A B C + A B C = Y

27 Truth Table From Boolean Expressions Fill in a truth table from a minterm Boolean Expression. Minterm Boolean expression: A B C + A B C + A B C = Y tep : Place three s in output column. tep 2: Place five s in blanks in output column of truth table. Truth Table Input Output ABC Y 28 The McGraw-Hill Companies, Inc. All rights reserved.

28 28 The McGraw-Hill Companies, Inc. All rights reserved. Truth Table from Boolean Expressions Fill in a truth table from a Boolean Expression. Boolean expression: A B + A B C = Y tep : Place single output column for term with three variables. tep 2: Place two s in output column for term with two variables. tep 3: Fill in s. Truth Table Input Output ABC Y

29 28 The McGraw-Hill Companies, Inc. All rights reserved. Boolean Expression Minterm expression of 3 Variables x y z f minterm symbol f ( x, y, z) f ( x, y, z) x y z x y z x y z x y z x y z x y z x y z x y z m(,, 3, 5, 7) f ( x, y, z) m(2, 4, 6) m(,, 3, 5, 7) m m m 2 m 3 m 4 m 5 m 6 m 7 m(2, 4, 6) x y z f ( x, y, z) m(,, 3, 5, 7) xyz xyz xyz xyz f ( x, y, z) m(2, 4, 6) xyz xyz xyz xyz xyz xyz x y z xyz x y z x y z x y z x y z xyz xyz xyz xyz xyz xyz xyz

30 Boolean Expression 28 The McGraw-Hill Companies, Inc. All rights reserved. Minterm expression of 4 Variables a b c d minterm symbol a b c d minterm symbol m abcd abcd m abcd m 2 abcd m 3 abcd m 4 abcd m 5 abcd m 6 abcd m 7 abcd abcd abcd abcd abcd abcd abcd abcd m 8 m 9 m m m 2 m 3 m 4 m 5 Example f ( a, b, c, d ) m(,, 5, 9,,5) abcd abcd abcd abcd abcd abcd

31 Boolean Expression 28 The McGraw-Hill Companies, Inc. All rights reserved. Maxterm expression of 3 Variables x y z f maxterm symbol Example x x x x x x x x y z y z y y z y z y z y z z y z M M M 2 M 3 M 4 M 5 M 6 M 7 f ( x, y, z) M(,, 3, 5, 7) ( x y z)( x y z)( x y z)( x y z)( x y z)

32 28 The McGraw-Hill Companies, Inc. All rights reserved. 7) 6, (, 7) 6, (, 5) 4, 3, 2, (, 5) 4, 3, 2, (, ),, ( m M M m c b a f 4,5) 2,3, (, ) )( )( )( )( ( 4,5) 2,3, (, ),, ( M c b a c b a c b a c b a c b a abc abc abc abc abc abc abc abc abc abc abc abc abc abc abc m c b a f (,6,7) ) )( )( ( (,6,7) ),, ( M c b a c b a c b a abc abc abc abc abc abc abc abc abc m c b a f 4,5) 3, 2, (, 4,5) 3, 2, (, (,6,7) (,6,7) ),, ( m M M m c b a f Negation of minterms becomes maxterms Negation of maxterms becomes minterms OP functions and PO functions

33 28 The McGraw-Hill Companies, Inc. All rights reserved. implify Boolean Expression Karnaugh Maps(K-map) A K-map is a diagram made up of squares, with each square representing one minterm of the function is to be minimized. The simplest expression is a Boolean expression with minimum number of terms and the smallest possible number of literals in each term. This expression produces a circuit with minimum number of gates and with minimum number of inputs to each gate. The simplest expression is not unique.

34 28 The McGraw-Hill Companies, Inc. All rights reserved. implify Boolean Expression Drawing and grouping Karnaugh Maps(K-map) Minterms in a K-map must be arranged in a sequence, and the sequence is that only one bit changes in value from one adjacent column to the next. It utilizes the basic rule 7 of Boolean algebra. X+X = hape of a minterm-group has to be a square or a rectangle. The number of minterms in a group must be multiple of 2 n. Group the adjacent minterms or groups. The bigger the better!

35 28 The McGraw-Hill Companies, Inc. All rights reserved. implify Boolean Expression Drawing Karnaugh Maps(K-map) F ( A, B, C) m(,2,3,4,5,7) AB C 2 3 F ( A, B, C, D) m(,2,4,5,7,9, 2, 3, 5) AB CD Only one bit is different 4= = = 3=

36 28 The McGraw-Hill Companies, Inc. All rights reserved. implify Boolean Expression F ( A, B, C, D) m(4,5,7,2,3,5) AB CD implified as:. Group 4,5,2,3 and 7,5 BC + BCD 2. Group 4,5,2,3 and 5,7,3,5 BC + BD Which one is more simple? Can 4,5,7,2,3,5 be grouped?

37 28 The McGraw-Hill Companies, Inc. All rights reserved. implify Boolean Expression Don t care terms: terms that can be either or F( A, B, C, D) m(,2,3,4,5,) d(,7,9,5) F( A, B, C, D) m(,2,3,4,6,8,) d(,2,4) m(,2,3,4,8,9,) F( A, B, C, D) d(,5,6,7,,2) CD AB x x x x CD AB x x x CD AB x x x x x x F AB CD AC F D AB F A B

38 28 The McGraw-Hill Companies, Inc. All rights reserved. implify Boolean Expression f ( w, x, y, z) wx wxy wyz w yz wxy z wx( y y )( z z) wxy( z z) w( x x) yz w( x x) yz wxy z m(, 3, 5, 6, 7, 2, 3, 4, 5) yz wx f ( w, x, y, z) wx wz xy

39 28 The McGraw-Hill Companies, Inc. All rights reserved. Encoder Encoder is a combinational circuit that converts binary information from a maximum of 2 n input lines to n output lines. This output lines generate a binary code corresponding to the input lines. The encoder detects the active input. 4 2 encoder input output D 3 D 2 D D D 3 D 2 D D B B B B B D2 D3, B D D3

40 28 The McGraw-Hill Companies, Inc. All rights reserved. 8 3 encoder input output D 7 D 6 D 5 D 4 D 3 D 2 D D B 2 B B D D D D B D D D D B D D D D B D 7 D 6 D 5 D 4 D 3 D 2 D D B B B 2

41 Example of commercial IC 28 The McGraw-Hill Companies, Inc. All rights reserved.

42 28 The McGraw-Hill Companies, Inc. All rights reserved. Multiplexer A multiplexer is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line. There are 2 n input lines and n selection lines whose bit combinations determine which input is selected. D D D 2 D 3 8x multiplexer x8 demultiplexer D D D 2 D 3 D 4 D 4 D 5 D 5 D 6 D 6 D 7 (sender) (receiver) D elect signals elect signals

43 28 The McGraw-Hill Companies, Inc. All rights reserved. 4 multiplexer election lines output F F D D D 2 D 3 D D D2 D3 D D D 2 F D 3

44 28 The McGraw-Hill Companies, Inc. All rights reserved. 8 multiplexer election lines output 2 F D D D 2 D 3 D 4 D 5 D 6 D 7 D D D 2 D 3 F 2 D 4 D 5 D 6 D D D D D D D D D F

45 28 The McGraw-Hill Companies, Inc. All rights reserved. Decoder A decoder is a combinational logic circuit that converts binary information from n input lines to maximum 2 n unique output lines. Decoders performs the inverse operation of encoders. 2 4 decoder/demultiplexer B A input output B A Y 3 Y 2 Y Y Y Y Y 2 Y Y 2 BA BA Y Y 3 BA BA Y 3

46 28 The McGraw-Hill Companies, Inc. All rights reserved. Commercial IC s are constructed with NAND gates. input output B A B A Y 3 Y 2 Y Y Y Y Y 2 Y Y 2 BA BA Y Y 3 BA BA Y 3

47 28 The McGraw-Hill Companies, Inc. All rights reserved. 2 4 decoders with enable inputs Most decoders include one or more enable inputs to control the circuit operation. A decoder operates when the enable input is equal to. A decoder constructed with NAND gates operates when the enable input is equal to. B A E input output E B A Y 3 Y 2 Y Y Y Y Y 2 Y Y 2 EBA EB A Y Y 3 EBA EBA Y 3

48 28 The McGraw-Hill Companies, Inc. All rights reserved. 3 8 decoder input output C B A Y 7 Y 6 Y 5 Y 4 Y 3 Y 2 Y Y Y Y 4 CBA, CBA, Y Y 5 CBA, CBA, Y Y 2 6 CBA, CBA, Y Y 3 7 CBA CBA C B A Y Y Y 2 Y 3 Y 4 Y 5 Y 6 Y 7

49 Demultiplexer 28 The McGraw-Hill Companies, Inc. All rights reserved. Demultiplexer is combinational circuit that receives information from a single input line and directs it to one of 2 n possible output lines. A decoder with enable input can function as a demultiplexer. A B 2x4 Decoder Y Y Y 2 Y 3 E x4 Demultiplexer Y Y Y 2 Y 3 E A B 2 4 decoder 4 demultiplexer

50 28 The McGraw-Hill Companies, Inc. All rights reserved. 4 cases of one-bit addition X Y + C input output X Y C Y X C Y X XY XY X Y C HA C X Y : sum C : carry Half Adder

51 28 The McGraw-Hill Companies, Inc. All rights reserved. Full Adder Used for adding binary place values other than the s place Input Output Logic ymbol: C in A B Full Adder (sum) C (carry out) Logic Diagram:

52 28 The McGraw-Hill Companies, Inc. All rights reserved. Full Adder 8 cases of one-bit addition C in X + Y C out input output X Y C in C out C XYC in X ( YC in X ( Y C XYC YC in X Y C out C C in in XYC in in in in ( XY XY ) ( X Y ) XY XYC ) X ( YC ) X ( Y C XYC in XY ( C in in in ) XY C in in C XYC YC in in XYC ) in ) in

53 28 The McGraw-Hill Companies, Inc. All rights reserved. Full Adder X Y C in X Y FA HA C out C in C out X Y C in C out C ( X Y) in XY X Y HA HA C in C out

54 28 The McGraw-Hill Companies, Inc. All rights reserved. Parallel Adding Use half adder for LD Use full adder for other digits A 2 A A + B 2 B B

55 Parallel Adder + UM appears here Parallel adders are available in IC form. s place uses half-adder 2s, 4s, 8s places use full adders The The McGraw-Hill Companies, Inc. Inc. All All rights reserved.

56 28 The McGraw-Hill Companies, Inc. All rights reserved. Parallel-adder/subtracter X 3 Y 3 X 2 Y 2 X Y X Y FA FA FA FA C 3 C 2 C C Parallel adder X 3 Y 3 X 2 Y 2 X Y X Y (sign) :Add :ub FA C 3 FA C 2 FA C FA C C Parallel adder/subtracter

57 28 The McGraw-Hill Companies, Inc. All rights reserved. High-speed adder The FA s must wait until their right FA s generate carries, i.e., a parallel adder has the delay time it takes to propagate the carry through the full adder. A high-speed adder(carry Lookahead Adder(CLA)) A CLA employs the carry-lookahead generator that does not have any delay time for propagating the carry. C ) For 4-bit CLA C C G PC out Ci XiYi ( Xi Yi Ci i i i i C where G i X i Y i P i X i Y G: generate, P: propagate G P C 2 G PC G PG P P C 3 G2 P2 C2 G2 P2 G PG P P C) G2 P2 G 2 4 G3 PC 3 3 G3 PG 3 2 P3 P2 G P3 P2 PG P3 P2 PP C C C i X i Y i C i P C i ( P PG P P P C i 2 i

58 28 The McGraw-Hill Companies, Inc. All rights reserved. High-speed adder XY Partial Full Adder (PFA) G P C X 3 Y 3 X 2 Y 2 X Y X Y 3 G P C 2 G P C G P C G P C G 3 P 3 C 3 G 2 P 2 C 2 G P C G P Carry Lookahead Logic C

59 28 The McGraw-Hill Companies, Inc. All rights reserved. High-speed adder 6-bit CLA with four 4-bit CLA s P G P P P G G G 3 2 P C 4 G3 PC 3 3 G3 PG 3 2 P3 P2 G P3 P2 PG P3 P2 PP C 3 P3 G2 P3 P2 G P3 P2 P G X 2-5 Y 2-5 X 8- Y 8- X 4-7 Y 4-7 X -3 Y -3 4-Bit Adder 4-Bit Adder 4-Bit Adder 4-Bit Adder 2-5 G P C 8- G P C 4-7 G P C -3 G P C G 3 P 3 C 3 G 2 P 2 C 2 G P C G P Carry Lookahead Logic G G P G C

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