CPE 628 Chapter 2 Design for Testability. Dr. Rhonda Kay Gaede UAH. UAH Chapter Introduction

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1 Chapter 2 Desgn for Testablty Dr Rhonda Kay Gaede UAH 2 Introducton Dffcultes n and the states of sequental crcuts led to provdng drect access for storage elements, whereby selected storage elements are connected nto a, s currently the most popular DFT approach Scan can be or, more promnent now Scan s now the bass for (BIST) technques Recently, DFT s mgratng from to level Page 2

2 22 Testablty Analyss Test programs use to ad n makng decsons Types of testablty analyss Page 3 22 Testablty Analyss SCOAP For each n a logc crcut, the followng values are calculated CC(s) combnatonal of s CC(s) combnatonal of s CO(s) combnatonal of s SC(s) sequental of s SC(s) sequental of s SO(s) sequental of s CC = CC = for a SC = SC = for a CO = SO = for a Page 4 2

3 22 Testablty Analyss SCOAP (Combnatonal Calculatons) Assgn order for each Calculate for all sgnals startng wth ( ), proceedng n order ( ) Page 5 22 Testablty Analyss SCOAP (Combnatonal Calculatons) Startng from, calculate Page 6 3

4 22 Testablty Analyss SCOAP (Combnatonal Calculatons) A B Sum C out C n Page 7 22 Testablty Analyss Probablty-Based For each sgnal s n a combnatonal crcut, calculate CO(s) - -controllablty of s C(s) - -controllablty of s O(s) - observablty of s C(s) and C(s) are the probabltes of controllng s to and from prmary nputs, respectvely O(s) s the probablty of observng sgnal s at outputs C = C = for a PI + = Page 8 4

5 22 Testablty Analyss Probablty- Based (Controllablty Calculaton Rules) Prmary Input AND OR NOT NAND NOR BUFFER XOR XNOR Branch -controllablty (Prmary nput, output, branch) p (output -controllablty) Π (nput -controllabltes) Input -controllablty Π (nput -controllabltes) (output -controllablty) Input -controllablty -controllablty -controllablty Stem -controllablty -controllablty (Prmary nput, output, branch) p = - p Π (nput -controllabltes) (output -controllablty) Input -controllablty (output -controllablty) Π (nput -controllabltes) Input -controllablty Σ(C(a) C(b), C(a) C(b)) Σ(C(a) C(b), C(a) C(b)) Stem -controllablty Page 9 UAH Chapter 2 22 Testablty Analyss Probablty- Based (Observablty Calculaton Rules) Page 5

6 22 Testablty Analyss Probablty- Based (Comparson to SCOAP) Sgnals wth probablty-based testablty measures tend to be dffcult to test wth or test patterns The faults on these lnes are often referred to as - Page 22 Testablty Analyss Smulaton-Based Smulaton-based methods use for testablty analyss and can be used as an to or a to -based analyss A sample set of nput test patterns are selected that are ether generated or derved from a s conducted to collect the of all or part of sgnal lnes of nterest Occurrences of, Occurrences of, transtons Due to long run tmes, ths technque s used mostly for - or - applcatons Page 2 6

7 22 Testablty Analyss RTL Improve testablty Improve the testablty of a - logc BIST crcut Lead to more results The number of s much less Become more tme Much than an equvalent -level model Page 3 22 Testablty Analyss RTL(Example) a b a b a n- b n- c c c c + c n- c out s n s s s n- Rpple Carry Adder Page 4 7

8 22 Testablty Analyss RTL(Example--Controllablty) The probablty-based -controllablty measures of s and c +, denoted by C(s ) and C(c +), are calculated as follows: C(s ) = α + C(c ) - 2 ( α C(c )) C(c + ) = α C(c ) + C(a ) C(b ) α = C(a ) + C(b ) - 2 C(a ) C(b ) α s the probablty that (a b ) = C(s ) s the probablty that (a b c ) = Page 5 22 Testablty Analyss RTL(Example- -Controllablty & Observablty) The probablty-based -controllablty of each output l, denoted by C(l), n the n-bt rpple-carry adder s O(l, s ) s defned as the probablty that a sgnal change on l wll result n a sgnal change on s O(a, s ) = O(b, s ) = O(c, s ) = O(s ) Snce where =,,, n - Harder for Page 6 8

9 23 Desgn for Testablty Bascs DFT (lterally ) Effects are and not Not Dffcult to A DFT Easly and Yelds the results Easy to Page 7 23 Desgn for Testablty Bascs Ad Hoc Approach Typcal Ad Hoc DFT technques Insert ponts Avod for storage elements Avod combnatonal Avod logc Avod logc a large crcut nto Page 8 9

10 23 Desgn for Testablty Bascs Ad Hoc Technques(Observablty Test Ponts) Logc crcut Low-observablty node A Low-observablty node B Low-observablty node C OP OP 2 OP 3 SO D SO SO OP_output OP2 shows the structure of an, whch s composed of a Observaton shft regster multplexer (MUX) and a D flp-flop Page 9 23 Desgn for Testablty Bascs Ad Hoc Technques(Controllablty Test Ponts) A MUX s nserted between the source and destnaton ends Durng normal operaton, TM =, such that the value from the source end drves the destnaton end through the port of the MUX Durng test, TM = such that the value from the D flp-flop drves the destnaton end through the port of the MUX Page 2

11 23 Desgn for Testablty Bascs Structured Approach X Combnatonal logc Y Y 2 X 2 X 3 f FF 3 D FF 2 D FF D To detect a fault, f Shft the desred Apply desred values on Apply one and fault effect Shft (shft n next test stmulus for ) Page 2 24 Scan Cell Desgns Muxed-D Scan Cell(Flp-Flop) D /SO D D 2 D 3 D 4 T T 2 T 3 T 4 Edge-trggered muxed-d scan cell /SO D T 3 Edge-trggered muxed-d scan cell operaton Page 22

12 24 Scan Cell Desgns Muxed-D Scan Cell(Latch) D D Level-senstve/edgetrggered muxed-d scan cell desgn SO Ths scan cell s composed of a multplexer, a D latch, and a D flp-flop In ths case, operaton s conducted n an manner, whle operaton and operaton s conducted n a manner Page Scan Cell Desgns Clocked Scan Cell /SO D S Clocked-scan cell Clocked-scan cell operaton Page 24 2

13 24 Scan Cell Desgns LSSD Scan Cell D L C I A B SRL L 2 C +L A B +L D 2 I +L D D 2 D 3 D 4 T T 2 T 3 T 4 D T 3 Modes of Operaton Normal Fed by, clocks Fed by, clocks to, clocks data to Shft clocks to, clocks to +L 2 T 3 Page Scan Cell Desgns Comparson Advantages Dsadvantages Muxed-D Scan Cell Clocked-Scan Cell LSSD Scan Cell to modern desgns provded by desgn automaton tools No degradaton Insert scan nto a desgn Guaranteed to be Add a multplexer Requre addtonal routng Increase complexty Page 26 3

14 25 Scan Archtectures Full-Scan Desgn or storage elements are converted nto and ATPG s used for test generaton Partal-Scan Desgn A of storage elements are converted nto and ATPG s typcally used for test generaton Random-Access Scan Desgn A random addressng mechansm, nstead of scan chans, s used to provde drect access to read or wrte scan cell Page Scan Archtectures Full-Scan Desgn All storage elements are replaced wth scan cells All can be All can be Advantage: Converts ATPG nto ATPG Almost full-scan desgn A percentage of storage elements are not replaced wth scan cells For performance reasons Storage elements that le on paths For functonal reasons Storage elements drven by a small that are deemed too to be worth the scan nserton effort Page 28 4

15 25 Scan Archtectures Full-Scan Desgn(Muxed-D) PI PPI X X 2 X 3 SFF Combnatonal logc Y Y2 SFF 2 SFF 3 SO Pseudo prmary outputs (PPOs) the scan cell can be are observed through outputs PO PPO Prmary nputs (PIs) nputs can be set to logc values set drectly n Pseudo prmary nputs (PPIs) the scan cell can be set to logc values are set through scan chan Prmary outputs (POs) outputs can be are observed drectly n Page Scan Archtectures Full-Scan Desgn(Muxed-D) PI SFF SFF 2 SFF 3 X X V : PI V 2 : PI S H C H S H C X L L H H L L L H L L L H V : PPI PO observaton PPO observaton V 2 : PPI S: shft operaton / C: capture operaton / H: hold cycle Test Operatons Page 3 5

16 25 Scan Archtectures Full-Scan Desgn(Clocked) PI X X 2 X 3 Combnatonal logc Y Y2 PPI PPO SFF SFF 2 SFF 3 SO D S D S D S D S PO In a muxed-d fullscan crcut, a scan enable sgnal s used In a clocked full-scan desgn, two operatons are dstngushed by properly applyng the two ndependent clocks S and D durng shft mode and capture mode Page 3 25 Scan Archtectures Full-Scan Desgn(LSSD) C A B C 2 X Combnatonal logc Combnatonal logc 2 Y X 2 2 SRL D I +L 2 C A +L B X 3 Y SRL 2 D I +L 2 C A +L B Sngle Latch Desgn SRL 3 D I +L 2 SO A +L C B The output port +L of the latch L s used to drve the combnatonal logc of the desgn In ths case, the latch L 2 s only used for scan testng To prevent combnatonal feedback, s fed by only, s fed by only Page 32 6

17 25 Scan Archtectures Full-Scan Desgn(LSSD) X X 2 X 3 C A C 2 or B SRL D I +L 2 C A +L B Combnatonal logc SRL 2 D I +L 2 C A +L B SRL 3 D I +L 2 C A +L B Y Y 2 SO In mode, use and Durng the operaton, use and Durng the operaton, use and Double Latch Desgn Page Scan Archtectures Partal-Scan Desgn PI PPI X X 2 X 3 Combnatonal logc SFF FF 2 SFF 3 Partal-Scan Desgn Y Y2 PO PPO SO Advantages Reduces and Dsadvantages Results n and generaton Offers less support for, compared to full-scan Page 34 7

18 25 Scan Archtectures Random-Access Scan Desgn Full-scan and partal scan are both scan Advantage low overhead of Dsadvantages Cannot control cells Hgh swtchng actvty at scan cells leads to hgh, resultng n,, or even - scan (RAS) ams to allevate these ssues Each cell s and addressable PI Row (X) decoder Combnatonal logc SC SC SC SC SC SC SC SC SC Column (Y) decoder Address shft regster PO S SO AI Page Scan Archtectures Random-Access Scan Desgn(Progressve) RAS sgnfcantly reduces test and smplfes ndependent applcaton Dsadvantage s to acheve random access Also, no guarantee of reduced random-access scan has been proposed to allevate these problems RE D SD Ф Ф Ф SD Ф Ф Ф PRAS scan cell desgn In mode, all horzontal row enable (RE) sgnals are set to, forcng each cell to act as a D flp-flop In mode, to capture the response from D, the RE sgnal s set to and a pulse s appled on clock, whch causes the value on D to be nto the scan cell Page 36 8

19 25 Scan Archtectures Random-Access Scan Desgn(Progressve) Row enable shft regster TM Test /SO control logc Sense-amplfers & MISR SC SC Column lne drvers SC SC SC SC SC SC SC Column address decoder CA PRAS Archtecture PO Combnatonal logc PI for each test vector v ( =, 2,, N){ /* Test stmulus applcaton */ /* Test response compresson */ enable TM; for each row r j (j =, 2,, m) { read all scan cells n r j / update MISR; for each scan cell SC n r j /* v(sc): current value of SC */ /* v (SC): value of SC n v */ f v(sc) v (SC) update SC; } /* Test response acquston */ dsable TM; apply the normal clock; } scan-out MISR as the fnal test response; Page Scan Desgn Rules Problematc I/O Ports Clocks Clocks Feedback Loops Set/Reset Sgnals Page 38 9

20 26 Scan Desgn Rules Trstate Buses Problem wth may occur durng Fault wthout, or SFF EN D SFF EN Bus keeper Functonal enable logc SFF 2 EN 2 D 2 Bus Functonal enable logc SFF 2 EN 2 D D 2 Bus SFF 3 EN 3 D 3 SFF 3 EN 3 D 3 Page Scan Desgn Rules Bdrectonal I/O Ports Problem may occur durng shftng Pn s nput but shfted value may enable BO BO BI Orgnal Crcut I/O BO BI I/O Modfed Crcut Page 4 2

21 26 Scan Desgn Rules Gated Clocks D D Clock EN gatng logc LAT Orgnal Crcut CEN D G If s used, only durng If s used, fault coverage on the s lost A G TM or DFF D D D Clock gatng reduces consumpton but also means that the clock cannot be from Clock gatng logc EN LAT Modfed Crcut CEN D G B G DFF D Page 4 26 Scan Desgn Rules Derved Clocks D I DFF D DFF 2 D A derved clock s a clock sgnal and s not controllable from the Orgnal Crcut A derved clock must be durng the operaton TM I D DFF D DFF 2 D Modfed Crcut Page 42 2

22 26 Scan Desgn Rules Combnatonal Feedback Loops Combnatonal logc Ḍ S Orgnal Crcut D Get rd of t f at all possble Combnatonal logc TM S Modfed Crcut Page Scan Desgn Rules Asynchronous Set/Reset Sgnals SFF RL Orgnal Crcut Usng means that faults n the logc cannot be Usng may lead to Use, R SFF 2 Asynchronous set/reset sgnals not from the prmary nputs can prevent from workng properly TM SFF RL Modfed Crcut R SFF 2 Page 44 22

23 26 Scan Desgn Flow Scan Desgn Rule Checkng and Repar and all scan desgn rule Scan Synthess Converts a desgn nto a desgn wthout orgnal functonalty Scan Extracton all scan cell nstances from all specfed Scan Verfcaton Verfy operaton and operaton usng tmng fle n standard delay format (SDF) Constrant & control nformaton Orgnal desgn Scan desgn rule checkng and repar Testable desgn Scan synthess Scan confguraton Scan replacement Scan reorderng Layout nformaton Scan sttchng Scan desgn Scan extracton Test generaton Scan verfcaton Page Scan Desgn Flow Scan Desgn Rule Checkng and Repar CD CCD CCD 2 2 CD 2 CD 3 CCD 3 CCD 4 CD 4 CD 5 CD 6 CD 7 3 CCD 5 Durng the phase, followng desgn rules should guarantee correctness for data paths that and wthn the same Movng across s trcky, but can some The clock between scan cells must be properly n order not to cause any Page 46 23

24 27 Scan Desgn Flow Scan Synthess Includes four separate and dstnct steps: Scan Confguraton The number of used The of scan cells used to these scan chans Whch storage elements to from the process How the scan cells are Scan Replacement Replaces all storage elements n the testable desgn wth ther scan cells Scan Reorderng The process of reorderng the scan chans based on the scan cell, n order to mnmze the amount of used to mplement the scan chans Scan Sttchng Sttch all together to form Page Scan Desgn Flow Scan Synthess(Scan Confguraton) Scan Confguraton The number of scan chans used lmted by, share wth pns, can t put any on I/O pads, also lmted by on tester The types of scan cells used to mplement these scan chans pcked from Whch storage elements to exclude from the process or reasons How the scan cells are arranged consder and of scan cells SC SC 2 X Y X D D 2 D 3 Y D D 2 D 3 Mxng Fallng and Rsng Edges Page 48 24

25 27 Scan Desgn Flow Scan Synthess(Scan Confguraton) Crossng Clock Domans Lock up latch, or, put n to guarantee that any between the clocks can be Clock skew s not across Ths scheme works only when the between the clocks s less than the of the clock pulse Clock doman Clock doman 2 SC p Lock-up latch SC q D X Y Z 2 2 X D D 2 D 3 Y D D 2 D 3 Z D D 2 D 3 Page RTL Desgn for Testablty RTL desgn Logc synthess Gate-level desgn Testablty repar Testable desgn Scan synthess Scan desgn Gate-Level Testablty Repar Desgn Flow RTL desgn Testablty repar Testable RTL desgn Logc/scan synthess Scan desgn RTL-Level Testablty Repar Desgn Flow Page 5 25

26 29 RTL Desgn for Testablty RTL Scan Desgn and Repar(Example) clk) f (q == 4'b) clk_5 <= ; else begn clk_5 <= ; q <= q + ; end clk_5) d < = start; clk clk_5 start D d RTL Verlog Descrpton Generated Schematc Page 5 29 RTL Desgn for Testablty RTL Scan Desgn and Repar(Example) clk) f (q == 4'b) clk_5 <= ; else begn clk_5 <= ; q <= q + ; end assgn clk_test = (TM)? clk : clk_5; clk_test) d < = start; clk clk_5 start D clk_test TM d Repared RTL Verlog Descrpton Repared Schematc Page 52 26

27 2 Concludng Remarks DFT has become for ensurng product s the most wdely used technque New desgn and test challenges Further reduce test, test and test Cope wth falures of the desgn era Page 53 27

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