Low-Cost Solutions for Video Compression Systems

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1 Overview Lw-Cst Slutins fr Cmpressin Systems Brian Jentz Altera Crpratin 101 Innvatin Drive San Jse, CA 9505, USA (08) Many device applicatins utilize vide cmpressin t reduce the amunt f data necessary t prduce a sequence f images. This array f applicatins ranges frm highdefinitin televisin t lw-pwer wireless vide transmissin. Implementatin f realtime vide cmpressin systems requires high data thrughput and cmplex cmputatinal algrithms. Traditinally, multiple device cmpnents have been required t implement bth the cmpressin and pre- and pst-prcessing functinality, but the increasing density f lw-cst FPGAs enables a cst-effective single-chip slutin fr the entire prcessing chain. This paper will demnstrate that real-time vide cmpressin systems can be implemented in lw-cst FPGAs. Starting frm available cmpressin IP cres (MPEG/JPEG2000), vide prcessing architectures fr the surveillance and security markets will be explred. Surveillance Case Study surveillance is a gd case study t examine as it has many f the elements cmmn in ther vide applicatins. First, let s examine the tp level blck diagram f a vide surveillance system. This system has 1- camera inputs with D1 reslutin, a hard disk drive fr strage, and a netwrk interface. ADC Memry Hard Disk Functinal Blcks include interface, vide cmpressin, vide prcessing, and system functins. System Prcessing Cmpressin Interfaces File System De- Interlacin M-JPEG BT-656 Scaling FPGA Clr Cnversi M- MPEG- JPEG200 SD-SDI VGA DVI Interfaces I²S I²C DDR Hardware RTP/UDP Sftware Flicker Filtering Cmpressin Chices DAC PHY Overlay Strea Rate IDE PCI One f the mst imprtant system decisins is the chice f vide cmpressin used in the system. The table belw shws sme f the key cnsideratins in chsing a cmpressin scheme.

2 Cmpressin is defined as the amunt f cmpressin achievable at a reasnable picture quality fr standard applicatins. The bit rate is the bandwidth requirement needed t get that quality (simply the raw size divided by the cmpressin rati). Mtin cmpensatin establishes a crrespndence between elements f nearby images in the vide sequence, allwing a useful predictin fr a given image frm a reference image. Variable Bit Rate (VBR) ffers the pssibility f fixing a cnstant picture quality by varying the bit-rate accrding t the needs f the picture. This allws the images that usually require little data, like still frames, t use additinal data nly when needed t maintain quality. The result is an verall saving in strage r mre efficient allcatin f ttal available bit-rate. Cnstant Bit Rate (CBR) frces a fixed utput rate, regardless f cmpressin quality, with the gal f fitting within a given bandwidth such as that n a cnstant bit rate transmissin channel. With vide, the useful infrmatin cntained in the material varies widely, bth spatially and with mvement. Fr example, a ftball game with crwds and grass texture as well as fast-panning cameras typically cntains far mre infrmatin than a largely static head-and-shulders sht f a newsreader. Using CBR means that the quality is altered t reduce the infrmatin t fit the fixed bit rate. In the ftball case, the grass may g flat during a pan with the texture reappearing when the camera is still. As verflwing the available bit rate culd have disastrus results with bits being lst, the aim is always t use just under the available bit rate. The degree f success in almst filling the available space is a measure f the quality and efficiency f the cmpressin system. Latency is essentially the ttal time fr encding and decding. Cmpressin algrithms wrk with blcks f data (8x8 fr JPEG) which can result in blck artifacts in the picture. Lssless cmpressin refers t cmpressin where n data is lst the dwnside is that the cmpressin is nly 2x. A cmpressed data stream is reslutin scalable if it cntains identifiable subsets that represent successively lwer reslutin versins f the surce; it is distrtin scalable (r SNR scalable) if it cntains identifiable subsets that represent the surce at full reslutin, but with successively lwer quality (in ther wrds, with mre distrtin and carser quantizatin). Scalability can als describe ther attributes. Subsets f a JPEG2000 cde-stream may be extracted t represent the riginal image at a reduced reslutin, a reduced quality (higher distrtin), r ver a reduced spatial regin. JPEG advantages are cst t implement and lw latency. Disadvantages are lack mtin cmpensatin and CBR supprt, presence f blcking artifacts. JPEG2000 advantages include n blcking artifacts and lssless supprt. Disadvantages are lack f mtin cmpensatin and cst t implement. MPEG advantages include high cmpressin, lw bit rate and mtin cmpensatin supprt. Disadvantages are latency and blcking artifacts. JPEG, JPEG2000, and MPEG have all been used in vide surveillance systems, with the chice depending n what is mst imprtant in that particular applicatin. H.26 is an advanced cmpressin scheme which is als starting t find its way int vide

3 surveillance systems. H.26 ffers very high cmpressin at the expense f additinal hardware cmplexity. It is nt examined in this paper, but FPGA-based slutins exist fr H.26. FPGA Implementatin This paper examines the use f Altera s lwcst FPGA family t implement the digital prtin f a vide surveillance system in a single device. Altera s Cyclne II family scales frm,600 lgic elements (LEs) t 68,000 LEs. A table f resurces fr Cyclne II is shwn belw. Device EP2C5 EP2C8 EP2C20 EP2C35 EP2C50 EP2C70 JPEG-Based System The diagram belw shws a JPEG-based implementatin f a vide surveillance system with D1 reslutin in an EP2C20 FPGA. N external memry is required. YUYV :2:2 Lgic Elements,608 8,256 18,752 33,216 50,528 68,16 Raw t Blck Cnversin 300 LEs Ttal Memry Bits 119, , ,616 83,80 59,32 1,152,000 18x18 Embedded Multipliers DDR Cntrller MPEG- Encder PLLs 2 2 Y Y Y Y U V :2:0 18,000 LEs 92 MK s Maximum User I/O Pins Buffered Reference 2,500 LEs Prductin Availability July August External DDR DRAM memry is required fr buffer memry. YUYV :2:2 Raw t Blck Cnversin 300 LEs DDR Cntrller MPEG- Encder Y Y Y Y U V :2:0 18,000 LEs 92 MK s JPEG2000-Based System Buffered Reference 2,500 LEs The diagram belw shws a JPEG2000- based implementatin f a vide surveillance system with D1 reslutin in an EP2C70 FPGA. External DDR DRAM memry is als required fr buffer memry In each f these implementatins, a 32-bit RISC prcessr, Altera s Nis II, is used t implement the IP stack and system initializatin. Nis II is a sft prcessr, meaning that it can be synthesized t any Altera FPGA. It can easily run ver 100 MHz in Cyclne II. All f the implementatins shwn are single channel implementatins, but multiple channel implementatins are pssible. A - channel JPEG-based system culd be implemented in the EP2C35. FPGAs als allw the scaling f the system feature set. Fr example, if ne wanted t add the ability t supprt multiple reslutins, alng with dynamic verlay t the MPEG-based system described earlier, it culd still be dne in the Cyclne II family, using the EP2C70. A blck diagram is shwn belw. MPEG-Based System The diagram belw shws a MPEG-based implementatin f a vide surveillance system with D1 reslutin in an EP2C35 FPGA, making this a $25 slutin in vlume. Stream PAL/NTSC DVI Overlay Graphics I/F I/F Deint er lacin Scalin g Scali ng Rate Cnv Hrizntal Scaling May Be Applied Here t Cnvert t Square Pixels (12.27/1.75 MHz) Overl ay Memry I/F Flicker Filter Raw t Blc k Clr Cnv MPE G-

4 Cnclusin Cmpressin-based vide systems are mving t higher reslutins, resulting in implementatins which ften require multiple device cmpnents. This paper shws hw a lw-cst FPGA family can be leveraged t meet a wide variety f system requirements multiple channels, multiple reslutins, and verlay in a single device.

5 101 Innvatin Drive San Jse, CA 9513 (08) Cpyright 2005 Altera Crpratin. All rights reserved. Altera, The Prgrammable Slutins Cmpany, the stylized Altera lg, specific device designatins, and all ther wrds and lgs that are identified as trademarks and/r service marks are, unless nted therwise, the trademarks and service marks f Altera Crpratin in the U.S. and ther cuntries. All ther prduct r service names are the prperty f their respective hlders. Altera prducts are prtected under numerus U.S. and freign patents and pending applicatins, maskwrk rights, and cpyrights. Altera warrants perfrmance f its semicnductr prducts t current specificatins in accrdance with Altera's standard warranty, but reserves the right t make changes t any prducts and services at any time withut ntice. Altera assumes n respnsibility r liability arising ut f the applicatin r use f any infrmatin, prduct, r service described herein except as expressly agreed t in writing by Altera Crpratin. Altera custmers are advised t btain the latest versin f device specificatins befre relying n any published infrmatin and befre placing rders fr prducts r services.

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