Embedded Systems and Software. Serial Interconnect Buses I 2 C (SMB) and SPI
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1 Embedded Systems and Software Serial Interconnect Buses I 2 C (SMB) and SPI I2C, SPI, etc. Slide 1
2 Provide low-cost i.e., low wire/pin count connection between IC devices There are many of serial bus standards I2C SMB SPI Microwire Maxim 3-wire Maxim/Dallas 1-wire CAN etc. Purpose of Serial Interconnect Buses We will focus on I 2 C and SPI I2C, SPI, etc. Slide 2
3 Overview Generic Serial Interconnect Bus Devices on bus. Can be several micros, one micro + peripherals, or multiple micros and one or more peripherals Pullup resistors ensure idle state of bus is HIGH. Devices pull line low when signaling. Wired-OR arrangement Bus. 1, 2, or 3 wires. This bus has 2 lines: Data and Clock. Bus carries data and commands. I2C, SPI, etc. Slide 3
4 SPI Devices D/A Converters Barometric Pressure SD Card EEPROMs I2C, SPI, etc. Slide 4
5 SPI Devices Ethernet Compass I2C, SPI, etc. Slide 5
6 SPI Devices FM Radio Chip FM Radio Module I2C, SPI, etc. Slide 6
7 I2C Devices BlinkM is a Smart LED, a networkable and programmable full-color RGB LED for hobbyists, industrial designers, and experimenters. MCP4725 is an I2C controlled Digital-to-Analog converter (DAC). A DAC allows a microcontroller to output analog values like a sine wave. Digital to analog converters are used sound generation, musical instruments, filtering, etc. I2C, SPI, etc. Slide 7
8 I2C Devices Honeywell HMC6352 Compass Module Breakout board for the Analog Devices 7746 capacitance sensor. I2C, SPI, etc. Slide 8
9 I2C Devices The TCM8240MD is a high quality, very small 1.3 mega-pixel color camera from Toshiba with the standard data + I2C interface. Breakout board using the AR1010 IC from Airoha. This FM receiver uses a simple command set over an I2C or SPI interface. This camera is also unique in that it offers on-board JPEG compression. I2C, SPI, etc. Slide 9
10 TWI Hardware on ATmega88PA ATmega88PA The ATmega88PA controller has dedicated TWI hardware. These pins provide access to the hardware One can also implement a Two-Wire serial interface in software on other pins. In other words, by bit-banging. I2C, SPI, etc. Slide 10
11 Commonly Encountered Terminology Term Transmitter Receiver Master Slave Multi-Master Arbitration Synchronization Description The device which sends the data to the bus. The device which receives the data from the bus. The device which initiates a transfer, generates clock signals and terminates a transfer. The device addressed by a master. More than one master can attempt to control the bus. Only one master can control the bus. Procedure to sync. the clock signal. I2C, SPI, etc. Slide 11
12 I 2 C (Inter-IC) I 2 C, Eye-Square-See, I2C, Eye-Two-See Two-wire serial bus protocol developed by Philips Semiconductors ~ 20 years ago Enables peripheral ICs to communicate using simple communication hardware Data transfer rates up to 100 kbits/s and 7-bit addressing possible in normal mode 3.4 Mbits/s and 10-bit addressing in fast-mode Common devices capable of interfacing to I 2 C bus: EPROMS, Flash, and some RAM memory, real-time clocks, watchdog timers, and microcontrollers Many microcontrollers, including ATmega88PA, have Two-Wire Interface (TWI) hardware AVR s TWI can be used to implement I2C, SMB, etc. I2C, SPI, etc. Slide 12
13 I2C The I2C-bus is a multi-master bus. This means that more than one device capable of controlling the bus can be connected to it. Masters are usually microcontrollers, slaves are peripherals We will use only one master (Atmega88PA) and one slave (RTC) I2C, SPI, etc. Slide 13
14 I2C Structure Master controls the bus, typically a microcontroller Pull-up resistors, ensure that by default, lines are high. We will use 4.7K resistors Slave responds to master(s), typically sensors, memory, etc. We will use one slave, a real-time clock (RTC) I2C, SPI, etc. Slide 14
15 I2C Structure Serial Clock Serial Data I2C, SPI, etc. Slide 15
16 I2C RTC Used in Lab 5 PCF8583 Clock/calendar with bit RAM Power Supply Note: the part has a built-in capacitors for the oscillator, so we don t have to supply them externally I2C, SPI, etc. Slide 16
17 PCF8583 Pin Functions Power Supply One can configure the part so that this pin periodically goes low, or goes low when an alarm goes of, or do nothing. We will not use this pin. Partially determines the RTC address on the bus (see data sheet). I2C Bus Lines It can be 1 or 0, we choose 0 I2C, SPI, etc. Slide 17
18 I2C RTC Used in Lab 5 PCF8583 Clock/calendar with bit RAM Notice, this does not use much current, one reason is because the clock frequency is low: khz I2C, SPI, etc. Slide 18
19 I2C RTC Used in Lab 5 I2C, SPI, etc. Slide 19
20 I2C RTC Used in Lab 5 Register addresses. This is located within the RTC I2C, SPI, etc. Slide 20
21 I2C RTC Used in Lab 5 Control register determines behavior: use as an event counter, or a clock, khz or 50 Hz time base, I2C, SPI, etc. Slide 21
22 I2C RTC Used in Lab 5 Registers contain the current time I2C, SPI, etc. Slide 22
23 I2C RTC Used in Lab 5 One can use the IC as a timer to time event durations I2C, SPI, etc. Slide 23
24 I2C RTC Used in Lab 5 One can use the part as an alarm clock. When alarm goes off pull INT line low I2C, SPI, etc. Slide 24
25 I2C RTC Used in Lab 5 Few bytes of additional RAM. One can use this for IDs, scratchpad, I2C, SPI, etc. Slide 25
26 I2C RTC Used in Lab 5 Select device s address on I2C bus I2C, SPI, etc. Slide 26
27 I2C RTC Used in Lab 5 IC2 Interface I2C, SPI, etc. Slide 27
28 I2C Protocol Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P). I2C, SPI, etc. Slide 28
29 Acknowledgement on the I2C Bus Each byte of eight bits is followed by an acknowledge bit (ACK). Upon transmission of the 8 th bit, the master releases the SDA line, which goes HIGH, the master generates an ACK clock pulse, and the slave acknowledges by pulling the SDA line low. A master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. (master) MSB (slave) Also, a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. I2C, SPI, etc. Slide 29
30 Acknowledgement on the I2C Bus A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave (NACK). In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition. (master) MSB (slave) I2C, SPI, etc. Slide 30
31 Addressing on the I2C Bus Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always carried out with the first byte transmitted after the start procedure. This part of the address is determined by the manufacturer of the PCF8583, and is fixed. I2C, SPI, etc. Slide 31
32 Addressing on the I2C Bus Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always carried out with the first byte transmitted after the start procedure. This part of the address is determined by the state of the IC s A0 pin It can be 1 or 0, we choose 0 I2C, SPI, etc. Slide 32
33 Addressing on the I2C Bus Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always carried out with the first byte transmitted after the start procedure. This bit determines if we are reading ( = 1) from or writing to (= 0) to the devices I2C, SPI, etc. Slide 33
34 I2C Structure SCL SDA Microcontroller (master) EEPROM (slave) Temp. Sensor (slave) LCDcontroller (slave) < 400 pf Addr=0x01 Addr=0x02 Addr=0x03 SDA SDA SDA SDA SCL SCL SCL SCL Start condition Sending 0 Sending 1 Stop condition From Slave From receiver SDA SCL S T A R T A 6 A 5 A 0 R / w A C K D 8 D 7 D 0 A C K S T O P Start condition 7-bit address R/W 8-bit data I2C, SPI, etc. Slide 34
35 PCF8583 Control Status Register I2C, SPI, etc. Slide 35
36 PCF8583 Register Arrangement Values are stored in in BCD What does BCD mean? Answer Binary-Coded Decimal. There are two variants: Unpacked and packed Example 12d = 0x0C = b Unpacked BCD: Packed BCD: I2C, SPI, etc. Slide 36
37 PCF8583 Master transmits to slave receiver (WRITE) mode. I2C, SPI, etc. Slide 37
38 PCF8583 Master reads after setting word address (write word address; READ data). I2C, SPI, etc. Slide 38
39 PCF8583 Master reads slave immediately after first byte (READ mode). I2C, SPI, etc. Slide 39
40 I2C Bus Timing f scl = 100 khz SCL clock frequency I2C, SPI, etc. Slide 40
41 I2C Bus Timing t SU;STA = 4.7 μs min START setup time I2C, SPI, etc. Slide 41
42 I2C Bus Timing t BUF = 4.7 μs min Bus free time I2C, SPI, etc. Slide 42
43 I2C Bus Timing t HD;STA = 4 μs min START Hold Time I2C, SPI, etc. Slide 43
44 I2C Bus Timing t LOW = 4.7 μs min SCL LOW time I2C, SPI, etc. Slide 44
45 I2C Bus Timing t HIGH = 4.7 μs min SCL HIGH time I2C, SPI, etc. Slide 45
46 I2C Bus Timing t t = 1.0 μs max t f = 0.3 μs max SDA and SCL rise and fall times I2C, SPI, etc. Slide 46
47 I2C Bus Timing t SU;DAT = 250 ns min Data setup time I2C, SPI, etc. Slide 47
48 I2C Bus Timing t VD;DAT = 3.4 μs SCL LOW to data out valid I2C, SPI, etc. Slide 48
49 I2C Bus Timing t SU;STO = 3.4 μs STOP setup time I2C, SPI, etc. Slide 49
50 Actual Bus Signals SDA SCL SDA (above) and SCL (below) with R p = 10 kω and C p = 300 pf. The SCL clock runs at 100 khz (nominal). One can improve rise- and fall times by decreasing resistance values I2C, SPI, etc. Slide 50
51 Serial Peripheral Interface (SPI) Originally developed by Motorola Synchronous, serial protocol Data timing is controlled by an explicit clock signal (SCK) Master-slave Master device controls the clock Bi-directional data exchange Data clocked into and out-of device at same time I2C, SPI, etc. Slide 51
52 SPI Devices D/A Converters Barometric Pressure SD Card EEPROMS I2C, SPI, etc. Slide 52
53 SPI Devices Ethernet Compass I2C, SPI, etc. Slide 53
54 SPI Devices FM Radio Chip FM Radio Module I2C, SPI, etc. Slide 54
55 SPI signals SS (CS) (Slave Select, Chip Select) When SS is low the slave is enabled SCK (Serial Clock) Controls the sending and reading of data SD0 (Serial Data Out) Carries data OUT of the device SDI (Serial Data In) Carries data INTO the device I2C, SPI, etc. Slide 55
56 Connecting Multiple SPI Devices arbitrary SDO SDI SCK pins AVR or other Micro (Master) SS SDO SDI SCK SPI Slave 1 SS SDO SDI SCK SPI Slave K I2C, SPI, etc. Slide 56
57 SPI on AVRs AVR microcontrollers have built-in hardware support for SPI AVRs can be bus masters (common), but one can also configure them to be bus slaves AVRs use SPI pins for ISP What is ISP? I2C, SPI, etc. Slide 57
58 SPI on AVRs AVR microcontrollers have built-in hardware support for SPI SCK Master Clock Output, Slave Clock I2C, SPI, etc. Slide 58
59 SPI on AVRs AVR microcontrollers have built-in hardware support for SPI MISO SPI Bus Master Input, Slave Output) I2C, SPI, etc. Slide 59
60 SPI on AVRs AVR microcontrollers have built-in hardware support for SPI MOSI SPI Bus Master Output, Slave Input I2C, SPI, etc. Slide 60
61 SPI on AVRs AVR microcontrollers have built-in hardware support for SPI SS SPI Bus Master Slave Select If AVR is configured as slave and one is using SPI hardware for SPI, then this would be used for selecting the AVR slave I2C, SPI, etc. Slide 61
62 SPI on AVRs Port pins I2C, SPI, etc. Slide 62
63 SPI on AVRs SPI Control Register I2C, SPI, etc. Slide 63
64 SPI on AVRs SPI Status Register I2C, SPI, etc. Slide 64
65 SPI on AVRs One can configure SPI hardware to generate interrupts I2C, SPI, etc. Slide 65
66 SPI on AVRs SPDR SPI Data Register. This is where our program reads/writes data I2C, SPI, etc. Slide 66
67 SPI Data Loop SPDR Master Slave I2C, SPI, etc. Slide 67
68 SPI Data Loop Internal shift register SPDR Master Slave I2C, SPI, etc. Slide 68
69 SPI Data Loop SPDR SPI Data Register. This is where our program reads/writes data SPDR Master Slave Master selects slave on bus to talk to I2C, SPI, etc. Slide 69
70 SPI Data Loop SPDR SPI Data Register. This is where our program reads/writes data SPDR Master Slave Master generates the clock that controls the data transfer I2C, SPI, etc. Slide 70
71 SPI Modes SPI has several modes that determine when data is valid with respect to the clock Caution: read SPI peripheral (i.e., RTC, sensor, ) datasheets carefully, and make sure your AVR uses the same mode I2C, SPI, etc. Slide 71
72 SPI Transfer Modes SPI Transfer Format with CPHA = 0 SPI Transfer Format with CPHA = 1 I2C, SPI, etc. Slide 72
73 SPI Transfer Modes SPI Transfer Format with CPHA = 0 SPI Transfer Format with CPHA = 1 I2C, SPI, etc. Slide 73
74 SPI Transfer Modes SPI Transfer Format with CPHA = 0 SPI Transfer Format with CPHA = 1 I2C, SPI, etc. Slide 74
75 SPI Transfer Modes SPI Transfer Format with CPHA = 0 SPI Transfer Format with CPHA = 1 I2C, SPI, etc. Slide 75
76 SPI Transfer Modes SPI Transfer Format with CPHA = 0 SPI Transfer Format with CPHA = 1 I2C, SPI, etc. Slide 76
77 SPI Transfer Modes SPI Transfer Format with CPHA = 0 SPI Transfer Format with CPHA = 1 I2C, SPI, etc. Slide 77
78 Configuring SPI SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set and the if the Global Interrupt Enable bit in SREG is set. I2C, SPI, etc. Slide 78
79 Configuring SPI SPE: SPI Enable When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI operations. I2C, SPI, etc. Slide 79
80 Configuring SPI DORD: Data Order When the DORD bit is written to one, the LSB of the data word is transmitted first. When the DORD bit is written to zero, the MSB of the data word is transmitted first. I2C, SPI, etc. Slide 80
81 Configuring SPI MSTR: Master/Slave Select This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to reenable SPI Master mode. I2C, SPI, etc. Slide 81
82 Configuring SPI CPOL: Clock Polarity When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low when idle. I2C, SPI, etc. Slide 82
83 Configuring SPI CPHA: Clock Phase The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or trailing (last) edge of SCK. I2C, SPI, etc. Slide 83
84 Configuring SPI CPHA: Clock Phase The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or trailing (last) edge of SCK. I2C, SPI, etc. Slide 84
85 I2C, SPI, etc. Slide 85
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