SIDH on ARM: Faster Modular Multiplications for Faster Post-Quantum Supersingular Isogeny Key Exchange.
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1 SIDH on ARM: Faster Modular Multiplications for Faster Post-Quantum Supersingular Isogeny Key Exchange. Hwajeong Seo (Hansung University), Zhe Liu (Nanjing University of Aeronautics and Astronautics), Patrick Longa (Microsoft Research), Zhi Hu (Central South University)
2 Outline Short Overview Post-quantum supersingular isogeny Diffie-Hellman (SIDH) key exchange Supersingular isogeny key encapsulation (SIKE) protocol Our implementation Optimized implementations for 32-bit ARMv7 Optimized implementations for 64-bit ARMv8 Implementation results Conclusion 1
3 Post-Quantum Cryptography (Isogeny) RSA and ECC: integer factorization and ECDLP Hard problems can be solved by Shor s algorithm in a quantum computer. Quantum-Resistant Cryptography NIST launches the post-quantum cryptography standardization project. The goal of this process is to select a number of acceptable candidate cryptosystems for standardization. Code, Lattice, Hash, Multivariate, Isogeny Isogeny-based cryptography: (conjectured to be) hard for quantum computers Supersingular isogeny Diffie-Hellman (SIDH) key exchange was proposed by Jao and De Feo in Among all the submitted post-quantum candidates, SIDH uses the smallest keys 2
4 Mobile Platform (32-bit/64-bit ARM) Platform ARM Cortex-A15 ARM Cortex-A53 ARM Cortex-A72 Architecture 32-bit ARMv7 64-bit ARMv8 64-bit ARMv8 Frequency 2.0 GHz GHz GHz No. registers No. registers (NEON) Application Wearable devices Smartphones 3
5 Previous Works Hardware Implementation FPGA: Koziel et al. [INDOCRYPT 16, TCAS 17] Software Implementation 64-bit Intel processor: Costello et al. [CRYPTO 16, EUROCRYPT 17], Faz-Hernández et al. [ToC 17], Zanon et al. [PQCrypto 18] 64-bit ARM processor: Jalali et al. [SAC 17] this work [CHES 18] 32-bit ARM processor: Koziel et al. [CANS 16] this work [CHES 18] 4
6 Motivation Type Algorithm Advantage Disadvantage Code McEliece Fast computation Long key size Hash XMSS, SPHINCS Security proof Long signature size Lattice (ring)-lwe Fast computation Multivariate UOV, Rainbow Short signature size Fast computation Difficulty of parameter selection Long key size Isogeny SIDH, SIKE Short key size Slow computation All PQC candidates have their own pros and cons. Disadvantage of SIDH/SIKE is slow computation. In this talk, we address this problem on 32-bit and 64-bit ARM processors. 5
7 Contribution Unified ARM/NEON multiplication: instruction level parallelism New Montgomery reduction: UMAAL + hybrid-scanning Efficient Implementation of SIDH: p503 (88 msec) / p751 (292 msec) on 32-bit p503 (45 msec) on 64-bit 6
8 Outline Short Overview Post-quantum supersingular isogeny Diffie-Hellman (SIDH) key exchange Supersingular isogeny key encapsulation (SIKE) protocol Our implementation Optimized implementations for 32-bit ARMv7 Optimized implementations for 64-bit ARMv8 Implementation results Conclusion 7
9 Post-quantum key exchange algorithm Supersingular Isogeny Diffie-Hellman (SIDH) Shared key generation between two parties over an insecure communication channel. SIDH works with the set of supersingular elliptic curves over F p 2 and their isogenies. E AB = Φ B Φ A E 0 E 0 / P A + s A Q A, P B + s B Q B E BA = Φ A Φ B E 0 8
10 Supersingular Isogeny Key Encapsulation (SIKE) SIDH is not secure when keys are reused (Galbraith-Petit-Shani-Ti 2016) SIKE: (Costello De Feo Jao Longa Naehrig Renes 2017) IND-CCA secure key encapsulation based on SIDH. Uses a variant of Hofheinz Hövelmanns Kiltz (HHK) transform: IND-CPA PKE IND-CCA KEM For a starting curve E 0 /F p 2 :y 2 = x 3 + x, where p = 2 ea 3 eb 1 Scheme (SIKEp + log 2 p ) e A,e B classical sec. quantum sec. Security level SIKEp503 (250,159) 126 bits 84 bits AES-128 (NIST level 1) SIKEp751 (372,239) 188 bits 125 bits AES-192 (NIST level 3) SIKEp964 (486,301) 241 bits 161 bits AES-256 (NIST level 5) 9
11 Outline Short Overview Post-quantum supersingular isogeny Diffie-Hellman (SIDH) key exchange Supersingular isogeny key encapsulation (SIKE) protocol Our implementation Optimized implementations for 32-bit ARMv7 Optimized implementations for 64-bit ARMv8 Implementation results Conclusion 10
12 Multiplication Instruction (32-bit ARMv7) ARM 32 bits NEON 32 bits R0 a0 V0 a3 a2 a1 a0 R1 b0 V1 b3 b2 b1 b0 + R2 c0 V2 a1b0 a0b bits R3 d0 UMULL R3, R2 a0b0 + c0 + d0 64 bits UMAAL 11
13 Previous Multiprecision Multiplication (32-bit ARMv7) C[14] C[7] C[0] C[14] C[7] C[0] 1 A[7]B[0] A[7]B[0] 4 A[7]B[7] 3 A[0]B[0] A[7]B[7] A[0]B[0] 2 A[0]B[7] Consecutive Operand Caching (COC) for ARM A[0]B[7] Cascade Operand Scanning (COS) for NEON Bitlength Method Instruction Timings [cc] 256-bit COC ARM (UMAAL) 158 COS NEON (UMULL) bit COC ARM (UMAAL) 596 COS NEON (UMULL) 632 Target processor: 32-bit ARM Cortex-A15 BEST BEST 12
14 Proposed Multiprecision Multiplication (32-bit ARMv7) Instruction level parallelism ARM and NEON instructions are issued together Karatsuba multiplication: m-bit multiplication (A H B H 2 m + A H B H + A L B L A H A L B H B L 2 m/2 + A L B L ) Two m/2-bit multiplication in ARM One m/2-bit multiplication in NEON 13
15 NEON ARM Operand passing Operand subtraction 1 15
16 NEON Operand passing ARM Operand subtraction 1 C[14] C[7] C[0] 3 C[10] C[4] C[6] C[0] 2 3 C[14] C[8] 4 A[7]B[7] 4 2 A[0]B[0] 16
17 NEON Operand passing ARM Operand subtraction 1 C[14] C[7] C[0] 3 C[10] C[4] Result passing C[6] C[0] 2 3 C[14] C[8] 4 A[7]B[7] 4 2 A[0]B[0] Result accumulation 5 17
18 Proposed Multiprecision Multiplication (32-bit ARMv7) Bitlength Method Instruction Timings [cc] COC ARM bit GMP ARM 1,138 COS NEON 632 This work ARM/NEON bit GMP ARM 2,408 This work ARM/NEON 912 Target processor: 32-bit ARM Cortex-A x 2.64x 18
19 Proposed Modular Reduction (32-bit ARMv7) m-bit modular reduction using Montgomery reduction Two m/2-bit multiplication in ARM Two m/2-bit multiplication in NEON 19
20 NEON Operand passing ARM 20
21 T[14] T[7] T[0] 2 4 T[14] T[10] NEON T[8] T[4] Operand passing Operand passing T[10] ARM T[6] T[0] T[4] 1 3 Q[7]M[7] 4 Q[0]M[7] 3 2 Q[7]M[0] 1 Q[0]M[0] 21
22 T[14] T[7] T[0] 2 4 T[14] T[10] NEON T[8] T[4] Operand passing Result passing Operand passing T[10] T[6] T[4] ARM T[0] Result Accumulation Q[7]M[7] 4 Q[0]M[7] 3 2 Q[7]M[0] 1 Q[0]M[0] 22
23 Modular Reduction for SIDH Efficient Montgomery reduction: Montgomery-friendly modulus The lower word of the modulus is 2 w 1 Montgomery constant is equal to 1. Multiplications with an all-ones word (T 0xFFFFFFFF T 2 32 T): shifts and subtractions (e.g., p503 = ) 0x4066F541811E1E6045C6BDDA77A4D01B9BF6C87B7E7DAF13085BDA2211E7A0ABFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF (in hexadecimal) A modulus M+1 turns the lower part of the modulus into all-zero words (e.g., p = ) 0x4066F541811E1E6045C6BDDA77A4D01B9BF6C87B7E7DAF13085BDA2211E7A0AC (in hexadecimal) 23
24 Proposed Modular Reduction for SIDH (32-bit ARMv7) m-bit modular reduction using Montgomery reduction One m/2-bit multiplication in ARM One m/2-bit multiplication in NEON 24
25 NEON Operand passing ARM 25
26 T[14] T[10] T[3] NEON Operand passing T[10] ARM Q[7]M[3] T[14] T[7] T[3] Q[7]M[7] 1 Q[0]M[3] Q[0]M[7] 26
27 T[14] T[10] T[3] NEON Operand passing T[10] ARM Q[7]M[3] T[14] T[7] T[3] Result Accumulation 3 Q[7]M[7] 1 Q[0]M[3] Q[0]M[7] 27
28 Outline Short Overview Post-quantum supersingular isogeny Diffie-Hellman (SIDH) key exchange Supersingular isogeny key encapsulation (SIKE) protocol Our implementation Optimized implementations for 32-bit ARMv7 Optimized implementations for 64-bit ARMv8 Implementation results Conclusion 28
29 Multiplication Instruction (64-bit ARMv8) X0 X1 a0 X0 a0 b0 X1 b0 a1b0 a0b0 a0b0 a0b0 X3 X2 64 bits X3 64 bits X2 MUL UMULH 29
30 Proposed Multiprecision Multiplication (64-bit ARMv8) Instruction level parallelism (high throughput) Instruction Instruction group Latency [cc] Throughput [cc] ADD/ADC/SUB/SBC ALU, basic 1 2 MUL Multiply 3 1/3 UMULH Multiply high 6 1/4... MUL X0, X4, X5 UMULH X1, X4, X5 ADDS X10, X10, X2 ADCS X11, X11, X3 ADC X12, XZR, XZR MUL X2, X6, X7 UMULH X3, X6, X7 ADDS X10, X10, X0 ADCS X11, X11, X1 ADC X12, X12, XZR... Based on these features, the 128-bit multiplication using column-wise multiplication is implemented at the lowest level. 128-bit (column-wise multiplication) 256-bit (1-level Karatsuba) 512-bit (2-level Karatsuba) 30
31 Outline Short Overview Post-quantum supersingular isogeny Diffie-Hellman (SIDH) key exchange Supersingular isogeny key encapsulation (SIKE) protocol Our implementation Optimized implementations for 32-bit ARMv7 Optimized implementations for 64-bit ARMv8 Implementation results Conclusion 31
32 Results (32-bit ARM Cortex-A15) SIDHp503 is about 1.7x faster than Koziel et al. s, and 13x faster than (generic C) Microsoft SIDH v3.0 library Implementation Language Instruction Timings [cc] Timings [cc 106 ] F p mul Alice R1 Bob R1 Alice R2 Bob R2 Total SIDHp503 SIDH v3.0 C Generic 8, ,296 Koziel et al. ASM NEON 1, This work ASM ARM/NEON SIDHp751 SIDH v3.0 C Generic 36,592 2,006 2,256 1,650 1,924 7,836 Koziel et al. C Generic N/A ,632 This work ASM ARM/NEON 1,
33 Results (64-bit ARM Cortex-A53/A72) SIDHp503 is about 1.3x faster than Campagna et al. s, and 4.8x faster than (generic C) Microsoft SIDH v3.0 library Implementation Language Processor SIDHp503 SIDH v3.0 C Timings [cc] Timings [cc 10 6 ] F p mul Alice R1 Bob R1 Alice R2 Bob R2 Total 4, Campagna et al. ASM Cortex-A53 1, This work ASM SIDH v3.0 C 3, Campagna et al. ASM Cortex-A This work ASM
34 Results (64-bit ARM Cortex-A53/A72) SIKEp503 is about 1.3x faster than Campagna et al. s, and 4.8x faster than (generic C) Microsoft SIDH v3.0 library Implementation Language Processor SIKEp503 SIDH v3.0 C Timings [cc] Timings [cc 10 6 ] F p mul KeyGen Encaps Decaps Total 4, Campagna et al. ASM Cortex-A53 1, This work ASM SIDH v3.0 C 3, Campagna et al. ASM Cortex-A This work ASM
35 Outline Short Overview Post-quantum supersingular isogeny Diffie-Hellman (SIDH) key exchange Supersingular isogeny key encapsulation (SIKE) protocol Our implementation Optimized implementations for 32-bit ARMv7 Optimized implementations for 64-bit ARMv8 Implementation results Conclusion 35
36 Conclusion New implementations of modular multiplication on ARM Faster multi-precision multiplication Faster Montgomery reduction Record-setting SIDH and SIKE implementations On both 32-bit and 64-bit ARM SIDH Library: 32-bit ARMv7 code is coming soon! 64-bit ARMv8 code is already integrated Thank you for your attention! 36
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