Midterm I March 12, 2003 CS152 Computer Architecture and Engineering

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1 University of California, Berkeley College of Engineering Computer Science Division EECS Spring 2003 John Kubiatowicz Midterm I March 2, 2003 CS52 Computer Architecture and Engineering Your Name: SID Number: Discussion Section: Problem Possible Score Total

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3 Problem : Short Answer Problem a [3 pts]: What is Amdhal s law? Give a formula and define the terms. How is this useful? Problem b [3 pts]: What are setup and hold-time and how can they be violated in a synchronous circuit? Can you still use a chip that is experiencing hold-time violations? How about setup violations? Problem c [2 pts]: Is the multi-cycle data path always faster than the single-cycle data path? Explain. Problem d [3 pts]: What are precise interrupts and why is it easy to provide them for our multi-cycle data path? 3

4 Problem e [3 pts]: Suppose that you have analyzed a benchmark that runs on your company s processor. This processor runs at 500MHz and has the following characteristics: Instruction Type Frequency (%) Cycles Arithmetic and logical 40 Load and Store 30 2 Branches 20 Floating Point 0 2 What is the CPI and MIPS rating of this processor running this benchmark? Problem f [2 pts]: What is the technique used for a carry-select adder and how can it be used in general to speed up hardware (hint: this is a very general technique to make a time space tradeoff) Problem g [3pts]: What does it mean for a branch to have a delay slot, and why does it complicate the servicing of interrupts? 4

5 Problem h[3pts]: The Clark paper on testing talked about using randomness in at least two different ways during testing of the VAX. What were they? Problem i [3 pts]: The -bit Booth algorithm recodes one of the operands of a multiplier from binary into trinary logic with symbols:, 0, and. The transformation occurs one bit at a time, as given in class: Cur Prev Out Suppose we encode 3 bits at a time. Finish filling out the following transformation table: Cur Prev Out

6 Problem 2: Delay For a Full Adder A key component of an ALU is a full adder. A symbol for a full adder is: A B C out Full Adder C in S Problem 2a [5pts]: Implement a full adder using as few 2-input AND, OR, and XOR gates as possible. Keep in mind that the Carry In signal may arrive much later than the A or B inputs. Thus, optimize your design (if possible) to have as few gates between Carry In and the two outputs as possible: 6

7 Assume the following characteristics for the gates: AND: Input load: 00fF, Propagation delay: TPlh=0.4ns, TPhl=0.4ns, Load-Dependent delay: TPlhf=.0020ns, TPhlf=.002ns OR: Input load: 00fF Propagation delay: TPlh=0.2ns, TPhl=0.6ns Load-Dependent delay: TPlhf=.0020ns, TPhlf=.002ns XOR: Input load: 200fF, Propagation delay: TPlh=.8ns, TPhl=.8ns Load-Dependent delay: TPlhf=.0040ns,TPhlf=.0042ns Problem 2b [3pts]: Compute the input load for each of the 3 inputs to your full adder: Problem 2c [4pts]: Identify two critical paths from the inputs to the Sum and the Carry Out signal. Compute the propagation delays for these critical paths based on the information given above. (You will have 2 numbers for each of these two paths): Problem 2d [2pts]: Compute the Load Dependent delay for your two outputs. 7

8 Problem 2e [6pts]: Suppose we wish to build a fast adder. One component might be a 4-bit adder with propagate and generate signals (such as might be used for carry-lookahead logic). Construct this adder as a 4-bit ripple adder internally (you can use your full-adders) with separate propagate and generate outputs. Let the output carry be a function of the propagate and generate signals. Draw a circuit for this component and compute the propagation delay for the slowest signal. A[3:0] B[3:0] C out [FAST] 4-BIT Adder C in S[3:0] G P 8

9 Problem 3: Non-Restoring Division Here is the pseudo-code for an unsigned division algorithm. It is the non-restoring version of the last divider that we developed. Assume that quotient and remainder are -bit global values. As far as inputs are concerned dividend is bits wide, while divisor is no more than 3 bits. divide(dividend, divisor) { int count; /* Missing initialization instructions */ MOBIUS64(remainder,quotient); while (count > 0) { count--; /* Low bit of quotient is inverted sign of remainder*/ if (quotient & 0x) remainder = remainder - divisor; else remainder = remainder + divisor; } MOBIUS64(remainder,quotient); } /* Missing trailing instructions */ The MOBIUS64(hi,lo) instruction rotates the 64-bit value <hi,lo> around to the left bit, wrapping the top bit of hi back to the bottom of lo and inverting it in the process. So, for instance: MOBIUS64(0xFFFFFFFF, 0x000000FF) 0xFFFFFFFE, 0x00000FE And: MOBIUS64(0x0FFFFFFF, 0x000000FF) 0xFFFFFFE, 0x00000FF Problem 3a [5pts]: Implement MOBIUS64($t, $t0) as 6 MIPS instructions. Assume $t2 contains the constant 0x Hint: what can different flavors of slt/sltu do to help? Problem 3b [5pts]: The divide algorithm is incomplete. It is missing some initialization and some final code. What is missing? (Careful what if the remainder is negative?) 9

10 Problem 3c [pts]: Assume that you have a MIPS processor that is missing the divide instruction. Assume that dividend and divisor are in $a0 and $a respectively, and that remainder and quotient are returned in registers $v0 and $v respectively. You can use MOBIUS64 as a pseudo-instruction that takes 3 registers (don t forget the constant in $t2). Make sure to adher to MIPS register conventions, and optimize the loop as much as possible. Problem 3d [4pts]: How will this algorithm have to change if the divisor is allowed to be bits in size? 0

11 Problem 4: New instructions for a multi-cycle data path PCWr PC PCWrCond Zero IorD MemWr 0 Mux RAdr Ideal Memory WrAdr Din Dout IRWr Instruction Reg Mem Data Reg RegDst Rs Rt Rt 0 Mux Rd 5 5 Mux 0 RegWr Ra Rb busa A Reg File Rw busw busb B << 2 ALUSelA 4 PCSrc 0 Mux Mux 0 Zero ALU ALU Control ALU Out Imm 6 ExtOp Extend MemtoReg ALUOp The Multi-Cycle datapath developed in class and the book is shown above. In class, we developed an assembly language for microcode. It is included here for reference: Field Name Values For Field Function of Field Add ALU Adds ALU Sub ALU subtracts Func ALU does function code (Inst[5:0]) Or ALU does logical OR SRC PC PC st ALU input rs R[rs] st ALU input nd ALU input rt R[rt] 2 nd ALU input SRC2 Extend sign ext imm6 (Inst[5:0]) 2 nd ALU input Extend0 zero ext imm6 (Inst[5:0]) 2 nd ALU input ExtShft 2 nd ALU input = sign extended imm6 << 2 rd-alu ALUout R[rd] ALU Dest rt-alu ALUout R[rt] rt-mem Mem input R[rt] Read-PC Read Memory using the PC for the address Memory Read-ALU Read Memory using the ALUout register for the address Write-ALU Write Memory using the ALUout register for the address MemReg IR Mem input IR PC Write ALU ALU value PCibm ALUoutCond If ALU Zero is true, then ALUout PC Seq Go to next sequential microinstruction Sequence Fetch Go to the first microinstruction Dispatch Dispatch using ROM ALUSelB

12 In class, we made our multicycle machine support the following six MIPS instructions: op rs rt rd shamt funct = MEM[PC] op rs rt Imm6 = MEM[PC] INST Register Transfers ADDU R[rd] R[rs] + R[rt]; PC PC + 4 SUBU R[rd] R[rs] - R[rt]; PC PC + 4 ORI R[rt] R[rs] + zero_ext(imm6); PC PC + 4 LW R[rt] MEM[ R[rs] + sign_ext(imm6)]; PC PC + 4 SW MEM[R[rs] + sign_ext(imm6)] R[rs]; PC PC + 4 BEQ if ( R[rs] == R[rt] ) then PC PC sign_ext(imm6) 00 else PC PC + 4 For your reference, here is the microcode for two of the 6 MIPS instructions: Label ALU SRC SRC2 ALUDest Memory MemReg PCWrite Sequence Fetch Add PC 4 ReadPC IR ALU Seq Dispatch Add PC ExtShft Dispatch RType Func rs rt Seq rd-alu Fetch BEQ Sub rs rt ALUoutCond Fetch In this problem, we are going to add five new instructions to this data path: jal <const> PC zero_ext(instr[25:0]) 00 R[3] PC + 4 addiu $rt, $rs, <const> R[rt] R[rs] + sign_ext(imm6) multu $rs, $rt <hi,lo> R[rs] R[rt] mfhi $rs R[rs] <hi> mflo $rs R[rs] <lo>. The jal instruction is familiar to you from the normal MIPS instruction set. 2. The addiu instruction is also a normal MIPS instruction that has an immediate value 3. The multu instruction is an unsigned multiply, and the mfhi/mflo instructions are for getting the result. 2

13 Problem 4a [0pts]: Describe/sketch the modifications needed to the datapath for the new instructions. Assume that the original datapath had only enough functionality to implement the original 6 instructions. Try to add as little hardware as possible. In particular, you must use the existing ALU for multiply. You can showing additions to the data path you do not need to completely redraw it. Make sure that you are very clear about your changes. Hint: you need to add hi and lo registers. They can be made from shift-registers. Your CPI for multiply should be no more than 40. So: how will you loop times for multu??? 3

14 Problem 4b [6pts]: Draw a block diagram of as microcontroller that will support the new instructions (it will be slightly different than that required for the original instructions). Include sequencing hardware, the dispatch ROM, the microcode ROM, and decode blocks to turn the fields of the microcode into control signals. Hint: you will need to provide a branching facility to your sequencer. Make sure to include this functionality! 4

15 Problem 4c [4pts]: Describe changes to the microinstruction assembly language for these new instructions. How wide are your microinstructions now? Problem 4d [0pts]: Write complete microcode for the new instructions. Include the Fetch and Dispatch microinstructions. If any of the microcode for the original instructions must change, explain how. 5

16 Problem 4e [Extra Credit: 5pts]: Describe a (relatively) small change that will allow you to implement the signed mult instruction (think Booth!). Be complete with your answer (datapath/microcode, etc). 6

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19 EXTRA SHEET FOR PROBLEM 4: FEEL FREE TO REMOVE PCWr PC PCWrCond Zero IorD MemWr 0 Mux RAdr Ideal Memory WrAdr Din Dout IRWr Instruction Reg Mem Data Reg RegDst Rs Rt Rt 0 Mux Rd 5 5 Mux 0 RegWr Ra Rb busa A Reg File Rw busw busb B << 2 ALUSelA 4 PCSrc 0 Mux Mux 0 Zero ALU ALU Control ALU Out Imm 6 ExtOp Extend MemtoReg The Multi-Cycle datapath developed in class and the book is shown above. In class, we developed an assembly language for microcode. It is included here for reference: Field Name Values For Field Function of Field Add ALU Adds ALU Sub ALU subtracts Func ALU does function code (Inst[5:0]) Or ALU does logical OR SRC PC PC st ALU input rs R[rs] st ALU input nd ALU input rt R[rt] 2 nd ALU input SRC2 Extend sign ext imm6 (Inst[5:0]) 2 nd ALU input Extend0 zero ext imm6 (Inst[5:0]) 2 nd ALU input ExtShft 2 nd ALU input = sign extended imm6 << 2 rd-alu ALUout R[rd] ALU Dest rt-alu ALUout R[rt] rt-mem Mem input R[rt] Read-PC Read Memory using the PC for the address Memory Read-ALU Read Memory using the ALUout register for the address Write-ALU Write Memory using the ALUout register for the address MemReg IR Mem input IR PC Write ALU ALU value PCibm ALUoutCond If ALU Zero is true, then ALUout PC Seq Go to next sequential microinstruction Sequence Fetch Go to the first microinstruction Dispatch Dispatch using ROM ALUSelB ALUOp 9

20 EXTRA SHEET FOR PROBLEM 4: FEEL FREE TO REMOVE In class, we made our multicycle machine support the following six MIPS instructions: op rs rt rd shamt funct = MEM[PC] op rs rt Imm6 = MEM[PC] INST Register Transfers ADDU R[rd] R[rs] + R[rt]; PC PC + 4 SUBU R[rd] R[rs] - R[rt]; PC PC + 4 ORI R[rt] R[rs] + zero_ext(imm6); PC PC + 4 LW R[rt] MEM[ R[rs] + sign_ext(imm6)]; PC PC + 4 SW MEM[R[rs] + sign_ext(imm6)] R[rs]; PC PC + 4 BEQ if ( R[rs] == R[rt] ) then PC PC sign_ext(imm6) 00 else PC PC + 4 For your reference, here is the microcode for two of the 6 MIPS instructions: Label ALU SRC SRC2 ALUDest Memory MemReg PCWrite Sequence Fetch Add PC 4 ReadPC IR ALU Seq Dispatch Add PC ExtShft Dispatch RType Func rs rt Seq rd-alu Fetch BEQ Sub rs rt ALUoutCond Fetch In this problem, we are going to add five new instructions to this data path: jal <const> PC zero_ext(instr[25:0]) 00 R[3] PC + 4 addiu $rt, $rs, <const> R[rt] R[rs] + sign_ext(imm6) multu $rs, $rt <hi,lo> R[rs] R[rt] mfhi $rs R[rs] <hi> mflo $rs R[rs] <lo> 4. The jal instruction is familiar to you from the normal MIPS instruction set. 5. The addiu instruction is also a normal MIPS instruction that has an immediate value 6. The multu instruction is an unsigned multiply, and the mfhi/mflo instructions are for getting the result. 20

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