Timing for Ripple Carry Adder

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Herbert Taylor
5 years ago
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1 Timing for Ripple Carry Adder 1

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5 Look Ahead Method 5

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9 9 Look-Ahead, bits wide

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12 Multiplication Simple Gradeschool Algorithm for 32 Bits (6 Bit Result) Multiplier Multiplicand AND gates 32 Bit Adder 6 Bit Product Register 12

13 Multiplication Simple Gradeschool Algorithm for 32 Bits (6 Bit Result) Multiplier Multiplicand Multiplier Register: parallel load (from source), serial output (least significant bit first) on command from control unit AND gates 32 Bit Adder 6 Bit Product Register Multiplication Simple Gradeschool Algorithm for 32 Bits (6 Bit Result) Multiplier Multiplicand Multiplicand Register: constant value for duration of algorithm. Load on command from source AND gates 32 Bit Adder 6 Bit Product Register 13

14 Multiplication Simple Gradeschool Algorithm for 32 Bits (6 Bit Result) Multiplier Multiplicand AND gates: form row of partial product array. In this case, 32 bits wide AND gates 32 Bit Adder 6 Bit Product Register Multiplication Simple Gradeschool Algorithm for 32 Bits (6 Bit Result) Multiplier Multiplicand 32 Bit Adder: add output of AND gates to running sum that will become product AND gates 32 Bit Adder 6 Bit Product Register 1

15 Multiplication Simple Gradeschool Algorithm for 32 Bits (6 Bit Result) Multiplier Multiplicand 6 Bit Product Register: contains running sum of rows of partial product array; ends with product of Multiplier, Multiplicand AND gates 32 Bit Adder 6 Bit Product Register Multiplication Simple Gradeschool Algorithm for 32 Bits (6 Bit Result) Multiplier Multiplicand Connection from Adder to the Product Register includes one-bit shift: carry out becomes MSB of Product Register, 32 Adder outputs next 32 bits, and 31 least significant bits, shifted product bits AND gates 32 Bit Adder 6 Bit Product Register 15

16 Multiplication Simple Gradeschool Algorithm for 32 Bits (6 Bit Result) Step 1: Clear Product Register Clear Counter Load Multiplicand Load Multiplier Step 2: (repeat 32 times) Increment Counter Load Product Register Shift Multiplier Step 3: Done Implement the Modified Gradeschool Multiplication Algorithm Multiplier (32 bits) Zero Detect Multiplicand (32+32 bits) AND gates (6 bits wide) Initial Zero Detect 6 Bit Adder 6 Bit Product Register 16

17 Biggest Unsigned Binary Multiply 16 Bits 16 Bits Biggest Unsigned Binary Multiply 16 Bits 16 Bits

18 Implement the Modified Gradeschool Multiplication Algorithm Multiplier (32 bits) Zero Detect Multiplier Register: 32 bits wide; parallel load on start of algorithm, serial shift for remainder of calculation Multiplicand (32+32 bits) AND gates (6 bits wide) 6 Bit Adder 6 Bit Product Register Initial Zero Detect Implement the Modified Gradeschool Multiplication Algorithm Multiplier (32 bits) Zero Detect Zero Detect: Determines when answer is ready when no 1 bits left in the Multiplier register Multiplicand (32+32 bits) AND gates (6 bits wide) 6 Bit Adder 6 Bit Product Register Initial Zero Detect 18

19 Implement the Modified Gradeschool Multiplication Algorithm Multiplier (32 bits) Zero Detect Multiplicand Register: 6 bits wide; loaded with 32 zeros (in MSBits) and initial input value (32 bits); during multiply calculation shifts to the left Multiplicand (32+32 bits) AND gates (6 bits wide) 6 Bit Adder 6 Bit Product Register Initial Zero Detect Implement the Modified Gradeschool Multiplication Algorithm Multiplier (32 bits) Zero Detect Initial Zero Detect: Check for initial value of zero on input Multiplicand Multiplicand (32+32 bits) AND gates (6 bits wide) 6 Bit Adder 6 Bit Product Register Initial Zero Detect 19

20 Implement the Modified Gradeschool Multiplication Algorithm Multiplier (32 bits) Zero Detect AND gates: To create expanded rows of partial product array, one row at a time (single bit from Multiplier register) Multiplicand (32+32 bits) AND gates (6 bits wide) 6 Bit Adder 6 Bit Product Register Initial Zero Detect Implement the Modified Gradeschool Multiplication Algorithm Multiplier (32 bits) Zero Detect 6 Bit Adder: Addition across whole product register with entire row of Partial Product Array Multiplicand (32+32 bits) AND gates (6 bits wide) 6 Bit Adder 6 Bit Product Register Initial Zero Detect 20

21 Implement the Modified Gradeschool Multiplication Algorithm Multiplier (32 bits) Zero Detect 6 Bit Product Register: Result builds from addition of rows of Partial Product Array; process terminates when all remaining rows are zeros. Multiplicand (32+32 bits) AND gates (6 bits wide) 6 Bit Adder 6 Bit Product Register Initial Zero Detect Multiplication Modified Gradeschool Algorithm for 32 Bits (6 Bit Result) Step 1: Clear Product Register Load Multiplicand Load Multiplier Step 2: If MIER = 0 OR MCAND = 0, done Step 3: Load Product Register Shift Multiplier Step : If MIER = 0, then Done else Go to Step 3 21

22 Newer Multiply Techniques Use More Gates! Very Simple Example x

23 Partial Product Rows Result Partial Product Rows Result 23

24 CSA CSA CSA CSA CSA CSA CSA CSA CSA CSA CSA CSA CSA CSA CSA CSA CSA CSA CSA CSA CSA Carry Propagate Adder Answer 2

25 Carry-Save Adder: Minimal Row Reduction Unit (RRU) : 3 rows Output: 2 rows 3-2 RRU Note: Care must be taken to make sure that the significance of the bits is handled properly Row Reduction: any combination of 2 N -1 rows N rows 2 N N

26 Row Reduction System 2 Bits CPA Division (Gradeschool) 26

27 Division Process A is integer (32 bits) B is integer (32 bits) Form A/B to give MQ the quotient ACC the remainder Explicatory Example: bits A is integer ( bits) B is integer ( bits) Form A/B to give MQ the quotient ( bits) ACC the remainder ( bits) 27

28 A / B : let A = 0111 let B = 0101 Answer should be: 0001 with a remainder: 0010 Grade School Approach

29 Grade School Approach Divisor Quotient Dividend Remainder Activity of Divide Divisor ACC Remainder Dividend(MQ) and Quotient Subtractor 29

30 More General Approach Denominator of initial problem Start condition: all zeros (ACC) Numerator of initial problem (MQ) Initial conditions: set up registers as shown here, then left-shift the ACC-MQ pair More General Approach First bit of answer: zero, since 0101 is bigger than 0000, so remember that and then left shift ACC-MQ 30

31 More General Approach x 0 Second bit of answer: zero, since 0101 is bigger than 0001, so remember that and then left shift ACC-MQ More General Approach xx 00 Third bit of answer: zero, since 0101 is bigger than 0011, so remember that and then left shift ACC-MQ 31

32 More General Approach xxx 000 Fourth bit of answer: one, since 0101 is smaller than 0111, so replace ACC with = 0010, and shift only MQ with the 1 bit More General Approach xxxx 0001 Final result: 0001 with remainder

33 More General Approach (2) Initial conditions: set up registers as shown here, then left-shift the ACC-MQ pair (Problem here is 2 / 11) More General Approach (2) First bit of answer: zero, since 1011 is bigger than 0000, so remember that and then left shift ACC-MQ 33

34 More General Approach (2) x 0 Second bit of answer: zero, since 1011 is bigger than 0000, so remember that and then left shift ACC-MQ More General Approach (2) xx 00 Third bit of answer: zero, since 1011 is bigger than 0001, so remember that and then left shift ACC-MQ 3

35 More General Approach (2) xxx 000 Fourth bit of answer: zero, since 1011 is bigger than 0010, so remember that, and since last step of algorithm, leave ACC as is and shift only MQ More General Approach (2) xxxx 0000 Final result: 0000 with remainder

36 More General Approach (3) Initial conditions: set up registers as shown here, then left-shift the ACC-MQ pair (Problem here is 13 / 2) More General Approach (3) First bit of answer: zero, since 0010 is bigger than 0001, so remember that and then left shift ACC-MQ 36

37 More General Approach (3) x 0 Second bit of answer: one, since 0010 is less than 0011, so replace ACC with = 0001, then remember the 1 and left shift ACC-MQ More General Approach (3) xx 01 Third bit of answer: one, since 0010 is same as 0010, so replace ACC with = 0000, remember the 1 and then left shift ACC-MQ 37

38 More General Approach (3) xxx 011 Fourth bit of answer: zero, since 0010 is bigger than 0001, so remember that, and since last step of algorithm, leave ACC as is and shift only MQ More General Approach (3) xxxx 0110 Final result: 0110 with remainder

39 Division Algorithm Initialization: Divisor (D S ) <= input value Dividend (MQ) <= input value Remainder (ACC) <= zero Count <= zero Note: this algorithm takes advantage of the fact that the MQ register starts with Dividend and ends with Quotient Division Algorithm Step 2: Left shift ACC-MQ pair Step 3: if ACC >= D S then ACC <= ACC D S ; FF <= 1 ; else FF <= 0 ; end if; Count <= Count + 1; 39

40 Division Algorithm Step : if Last Iteration then left shift MQ-FF; else left shift ACC-MQ-FF; end if; Step 5: if Count < Termination then return to Step 3; else Done; end if; High Speed Division Use High Speed Multiplier Follows Newton-Raphson iteration method Can find correct answer after few iterations 0

41 High Speed Divide A B High Speed Divide A f B f 0 0 1

42 High Speed Divide A f B f 0 0 let B = 1 x, then x = 1- B, and let f0 = 1 + x = 2 - B High Speed Divide A f B f 0 0 let B = 1 x, then x = 1 - f 0 = 1 + x = AND : B, and let 2 - B B f0 = (1- x) (1+ x) = 1- x 2 2

43 3 High Speed Divide f f f f f B f f f f f A A B 2 s Comp 2 s Comp 2 s Comp 2 s Comp Answer

44 Floating Point Arithmetic Addition of Floating Point Numbers = = x 2 10 IEEE: = = so,

45 Addition of Floating Point Numbers = = x 2 10 IEEE: = = so, = = x 2 8 IEEE: = = so, Addition of Floating Point Numbers Step 1: Determine larger of two numbers by comparing the exponents Number A: Number B: A B = Number A is bigger than Number B by a factor of about (2 2 ) 5

46 Addition of Floating Point Numbers Step 2: Represent numbers in same format of user s choosing. Choice here is two words (6 bits) with p=56. Note: keep track of fact that this is x Addition of Floating Point Numbers Step 3: do the addition:

47 Addition of Floating Point Numbers Step : Post normalize: (restore normalized condition) and adjust exponent x 2 1 So, final IEEE representation: Addition of Floating Point Numbers = = x 2 10 IEEE: = = so, = = x 2 10 IEEE: = = so,

48 Addition of Floating Point Numbers Step 1: Determine larger of two numbers by comparing the exponents Number A: Number B: A B = Number A is same order of magnitude as Number B; no alignment necessary Addition of Floating Point Numbers Step 2: Represent numbers in same format of user s choosing. Choice here is two words (6 bits) with p=56. Note: keep track of fact that this is x

49 Addition of Floating Point Numbers Step 3: do the addition (in this case, subtraction): Addition of Floating Point Numbers Step : Post normalize: (restore normalized condition) and adjust exponent x 2 - So, final IEEE representation:

Clocked Sequential System Design. Multiply Example

Clocked Sequential System Design Example 1 Multipliers (Gradeschool, Modified Gradeschool) Multiply Example (185) (215) 00000000 00000000 ------ 1001101101011111 (39775) 1 0000000000000000