CS61C : Machine Structures

Transcription

1 CS 61C L path (1) insteecsberkeleyedu/~cs61c/su6 CS61C : Machine Structures Lecture # path natomy: 5 components of any Computer Personal Computer This week Computer Processor ( brain ) path ( brawn ) (where programs, data live when running) Devices Input Output Keyboard, Mouse Disk (where programs, data live when not running) Display, Printer ndy Carle CS 61C L path (2) Outline Design a processor: step-by-step Requirements of the Set Hardware components that match the instruction set requirements CS 61C L path (3) How to Design a Processor: step-by-step 1 nalyze instruction set architecture (IS) => datapath requirements meaning of each instruction is given by the register transfers datapath must include storage element for IS registers datapath must support each register transfer 2 Select set of datapath components and establish clocking methodology 3 ssemble datapath meeting requirements 4 nalyze implementation of each instruction to determine setting of control points that effects the register transfer 5 ssemble the control logic CS 61C L path (4) Step 1: The MIPS Formats ll MIPS instructions are bits long 3 formats: R-type I-type J-type op rs rt rd shamt funct bits op target address 6 bits bits The different fields are: op: operation ( opcode ) of the instruction rs, rt, rd: the source and destination register specifiers shamt: shift amount funct: selects the variant of the operation in the op field address / immediate: address offset or immediate value target address: target address of jump instruction 5 bits 5 bits 6 bits op rs rt address/immediate 6 Step 1: The MIPS-lite Subset for today DD and SU addu rd,rs,rt subu rd,rs,rt OR Immediate: ori rt,rs,imm LOD and STORE Word lw rt,rs,imm sw rt,rs,imm RNCH: beq rs,rt,imm op rs rt rd shamt funct 5 bits 5 bits 6 bits bits bits bits 6 CS 61C L path (5) CS 61C L path (6)

2 CS 61C L path (7) Step 1: Register Transfer Language RTL gives the meaning of the instructions {op, rs, rt, rd, shamt, funct} = MEM[ ] {op, rs, rt, Imm} = MEM[ ] ll start by fetching the instruction inst Register Transfers DDU R[rd] = R[rs] + R[rt]; = + 4 SUU R[rd] = R[rs] R[rt]; = + 4 ORI R[rt] = R[rs] zero_ext(imm); = + 4 LOD R[rt] = MEM[ R[rs] + sign_ext(imm)]; = + 4 STORE MEM[ R[rs] + sign_ext(imm) ] = R[rt]; = + 4 EQ if ( R[rs] == R[rt] ) then = sign_ext(imm)] << 2 else = + 4 Step 1: Requirements of the Set (MEM) instructions & data (R: x ) read RS read RT Write RT or RD (sign extend) dd and Sub register or extended immediate dd 4 or extended immediate to CS 61C L path (8) Step 1: bstract Implementation Next Ideal CS 61C L path (9) -bit Signals Conditions Rd 5 path In Ideal Out How to Design a Processor: step-by-step 1 nalyze instruction set architecture (IS) => datapath requirements meaning of each instruction is given by the register transfers datapath must include storage element for IS registers datapath must support each register transfer 2 Select set of datapath components and establish clocking methodology 3 ssemble datapath meeting requirements 4 nalyze implementation of each instruction to determine setting of control points that effects the register transfer 5 ssemble the control logic (hard part!) CS 61C L path (1) Step 2a: Components of the path Combinational Elements Storage Elements Clocking methodology Combinational Logic: More Elements dder MUX Select Y MUX CarryIn dder Sum Carry OP CS 61C L path () CS 61C L path (12)

3 CS 61C L path (13) Needs for MIPS-lite + Rest of MIPS ddition, subtraction, logical OR, ==: DDU R[rd] = R[rs] + R[rt]; SUU R[rd] = R[rs] R[rt]; ORI R[rt] = R[rs] zero_ext(imm) EQ if ( R[rs] == R[rt] ) Test to see if output == for any operation gives == test How? P&H also adds ND, Set Less Than (1 if <, otherwise) follows chap 5 Storage Element: Idealized Write Enable (idealized) One input bus: In In One output bus: Out word is selected by: selects the word to put on Out Write Enable = 1: address selects the memory word to be written via the In bus Clock input (CLK) The CLK input is a factor ONLY during write operation During read operation, behaves as a combinational logic block: - valid => Out valid after access time Out CS 61C L path (14) Storage Element: Register (uilding lock) Similar to D Flip Flop except - N-bit input and output - Write Enable input Write Enable: - negated (or deasserted) (): Out will not change - asserted (1): Out will become In Write Enable In N Out N Storage Element: Register File Register File consists of registers: Two -bit output busses: and One -bit input bus: RWR R Write Enable 5 -bit Register is selected by: R (number) selects the register to put on (data) R (number) selects the register to put on (data) RW (number) selects the register to be written via (data) when Write Enable is 1 Clock input (CLK) The CLK input is a factor ONLY during write operation During read operation, behaves as a combinational logic block: - R or R valid => or valid after access time CS 61C L path (15) CS 61C L path () dministrivia Project 2 due Friday Hope you ve already started HW5 (maybe HW56?) out soon Step 3: ssemble Path meeting requirements Register Transfer Requirements path ssembly Fetch Read Operands and Execute Operation CS 61C L path (17) CS 61C L path (18)

4 CS 61C L path (19) 3a: Overview of the Fetch Unit The common RTL operations Fetch the : mem[] Update the program counter: - Sequential Code: = ranch and Jump: = something else Next Logic Word 3b: dd & Subtract R[rd] = R[rs] op R[rt] Ex: addu rd,rs,rt Ra, Rb, and Rw come from instruction s Rs, Rt, and Rd fields 6 ctr and RegWr: control logic after decoding the instruction Rd RegWr 5 -bit CS 61C L path (2) op rs rt rd shamt funct 5 bits 5 bits 6 bits ctr lready defined register file, Clocking Methodology Register-Register Timing: One complete cycle Old Value Rs, Rt, Rd, Op, Func ctr ccess Time Old Value Delay through Logic Old Value Storage elements clocked by same edge eing physical devices, flip-flops (FF) and combinational logic have some delays Gates: delay from input change to output change Signals at FF D input must be stable before active clock edge to allow signal to travel within the FF, and we have the usual clock-to-q delay Critical path (longest path through logic) determines length of clock period RegWr Old Value Register File ccess, Old Value Time Delay Old Value Rd RegWr 5 -bit ctr Register Write Occurs Here CS 61C L path () CS 61C L path (22) 3c: Logical Operations with Immediate R[rt] = R[rs] op ZeroExt[imm] ]? RegWr 5 imm -bit CS 61C L path (23) ZeroExt 15 rd? bits bits Src ct r immediate bits What about Rt register read?? lready defined -bit MUX; Zero Ext? 3d: Load Operations R[rt] = Mem[R[rs] + SignExt[imm]] Example: lw rt,rs,imm CS 61C L path (24) RegWr 5 imm bits -bit ExtOp ctr In?? Src MemWr WrEn dr W_Src

5 CS 61C L path (25) 3e: Store Operations Mem[ R[rs] + SignExt[imm] ] = R[rt] Ex: sw rt, rs, imm bits ctr MemWr RegWr5 -bit imm In WrEndr W_Src 3f: The ranch bits beq rs, rt, imm mem[] Fetch the instruction from memory Equal = R[rs] == R[rt] Calculate branch condition if (Equal) Calculate the next instruction s address - = ( SignExt(imm) x 4 ) else - = + 4 ExtOp Src CS 61C L path () path for ranch Operations beq rs, rt, imm path generates condition (equal) 4 imm Ext bits dder dder CS 61C L path (27) n_sel Inst RegWr 5 -bit Cond lready MUX, adder, sign extend, zero Equal? Putting it ll Together: Single Cycle path imm 4 Ext dder dder n_sel Equal 1 RegWr 5 -bit 1 imm CS 61C L path (28) Inst dr <:25> Rs <:2> Rt Rd <:15> <:15> Imm ExtOp Src <:> ctr MemWr MemtoReg = In WrEn dr 1 Peer Our is a synchronous device We should use the main to compute =+4 C The is inactive for memory reads or writes Summary: Single cycle datapath 5 steps to design a processor 1 nalyze instruction set => datapath requirements 2 Select set of datapath components & establish clock methodology 3 ssemble datapath meeting the requirements 4 nalyze implementation of each instruction to determine setting of control points that effects the register transfer Processor 5 ssemble the control logic Input is the hard part Next time! path Output CS 61C L path (29) CS 61C L path (3)