Review: ISA. Review: Compiling Applications. Computer Architecture ELEC3441. Instruction Set Architecture (1) Computer Architecture: HW/SW Interface

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1 Computer Architecture ELEC3441 Instruction Set Architecture (1) 2 nd Semester, Dr. Hayden Kwok-Hay So Review: ISA n Instruction set architecture defines the user observable behavior a processor A contract between hardware and software n Usually includes: Observable state of a processor A set of machine instructions Semantics of the instruction and processor execution Department of Electrical and Electronic Engineering 2nd sem. '17-18 ENGG HS 2 Computer Architecture: HW/SW Interface Applications Review: Compiling Applications Software Compiler Assembler Applications (C/C++/Java) foo.c Operating System Instruction Set Architecture ISA Hardware Microarchitecture Processor Digital Design Circuit Design Transistors Memory I/O Assembly Code foo.s Assembler Machine Instructions foo.exe 2nd sem. '17-18 ENGG HS 3 2nd sem. '17-18 ENGG HS 4

2 Note about learning an ISA n By learning how ONE ISA is designed, you learn how various architectural tradeoffs are performed. n NOT to memorize details of a single ISA n The subset of RISC-V covered in class is very similar to MIPS: More examples in COD Will use MIPS software for simulation in some cases Version 2.0 2nd sem. '17-18 ENGG HS 5 2nd sem. '17-18 ENGG HS 6 RISC-V ISA n New RISC design from UC Berkeley n Realistic & complete ISA, but open & small n Not over-architected for a certain implementation style n 32-bit and 64-bit address space variants RV32 and RV64 n Designed to be extensible High-performance multiprocessing Efficient instruction encoding for embedded system etc n Easy to subset/extend for education/research n Complete compilation toolchain n FPGA and ASIC designs RISC-V Foundation 2nd sem. '17-18 ENGG HS 7 2nd sem. '17-18 ENGG HS 8

3 RISC-V ISA 2.0 n A revised version to the original definition n Divides into an integer base ISA + extension Floating point, etc n Revised instruction coding Make hardware design easier n Added 128-bit support n Much more n We will be using RISC-V ISA 2.0 this semester: Things may break RISC-V base integer ISA is similar to MIPS in textbook Will try cross reference between RISCV and MIPS 2nd sem. '17-18 ENGG HS 9 RISC-V ISA Overview n The riscv processor has a load-store architecture Most instructions operate on values directly to and from the register file Dedicated load/store instructions to transfer data between register file and main memory n RV32 has a 32-bit word length Fixed instruction length of 32 bits A data word is 32 bits wide RISCV-V ISA designed to allow variable length instruction code and instruction extension Not covered in this course 2nd sem. '17-18 ENGG HS 10 RV32 Processor State Base Integer Design n Register file with bit generalpurpose registers n Labeled x0 x31 x0 always contains the value 0 n Application Binary Interface (ABI) names used in assembler t0 t6 for temp variables s0 s11 for saved variables, etc n Additional Program Counter (PC) register Contains the memory address of the current executing instruction Register ABI Name x0 zero x1 ra x2 sp x3 gp x4 tp x5-7 t0-2 x8 s0/fp x9 s1 x10-17 a0-7 x18-27 s2-11 x28-31 t3-6 XLEN=32 in RV32 Integer Register-Register Operations n Basic arithmetic and bit operations: Arithmetic: ADD, SUB Bit Operations: AND, OR, XOR, SLL, SRL, SRA Comparison: SLT, SLTU n Take two source register inputs (denoted rs1, rs2) and produce one destination register output (denoted rd). 2nd sem. '17-18 ENGG HS 11 2nd sem. '17-18 ENGG HS 12

4 ADD/SUB Assembler ADD rd, rs1, rs2 SUB rd, rs1, rs2 n 3 operands: 2 sources and 1 destination n Add/sub the values of the 2 source registers (rs1, rs2) and store the result in destination register (rd) n Discard overflow n Lower 32 bits are written Semantics rd ß rs1 + rs2 rd ß rs1 - rs2 ADD/SUB Example n C code: n Assume e, f, g, h, y stored in a0, a1, a2, a3, a4 respectively. n RISCV code: y = (e + f) (g + h);! ADD t0, a0, a1! ADD t1, a2, a3! SUB a4, t0, t1!! 2nd sem. '17-18 ENGG HS 13 2nd sem. '17-18 ENGG HS 14 Bit Operations n Similar semantics to ADD/SUB instructions n Bit operations useful for masking values n E.g.: Assembler AND rd, rs1, rs2 OR rd, rs1, rs2 XOR rd, rs1, rs2 Semantics rd ß rs1 AND rs2 rd ß rs1 OR rs2 rd ß rs1 XOR rs2 # t0 ß 0xABCD0123! # t1 ß 0x000F0000! AND t2, t0, t1! # t2 contains 0x000D0000! Quick Quiz # t0 ß 0x00C00005! # t1 ß 0xFFFFFFFF! XOR t2, t0, t1! What is the value stored in t2? 2nd sem. '17-18 ENGG HS 15 2nd sem. '17-18 ENGG HS 16

5 RISC-V Instruction Encoding n Each supported instruction in the ISA must be uniquely encoded to describe its function n Any unique encoding works, but good encoding may optimize: Regularity Simple hardware decode Instruction length Extensibility n In RV32, Each instruction is 32-bit wide Favors hardware regularity over human readability 6 general types of instructions R-type, I-type, S-type, SB-type, U-type, UJ-type 2nd sem. '17-18 ENGG HS 17 R-type Instruction Encoding n So far, all the simple integer register-register operations are encoded as R-type instructions n Instructions within the same type shares similar encoding n Differentiate only by the funct3 and funct7 fields R-Type format funct7 rs2 rs1 funct3 rd opcode src2 src1 ADD/SLT/SLTU dest OP src2 src1 AND/OR/XOR dest OP src2 src1 SLL/SRL dest OP src2 src1 SUB/SRA dest OP 2nd sem. '17-18 ENGG HS 18 Quick Quiz n If the size of register file is increased to include 64 registers, how many bits are needed to encode rs1? n How would the above change affect the number of instructions representable? Immediate Operations n Very often programs need to operate on (small) numerical constants in the code e.g.: a = b + 3 n RV32 includes register-immediate instructions for these cases n Small constant embedded within the instruction. Arithmetic: ADDI Bit Operations: ANDI, ORI, XORI Comparison: SLTI, SLTIU n Take one source register inputs (rs1) and produce one destination register output (rd). 2nd sem. '17-18 ENGG HS 19 2nd sem. '17-18 ENGG HS 20

6 I-type Instruction Encoding n Most register-immediate operations are encoded using the I-type format imm[11:0] rs1 funct3 rd opcode I-immediate[11:0] src ADDI/SLTI[U] dest OP-IMM I-immediate[11:0] src ANDI/ORI/XORI dest OP-IMM n NOTE: since the constant is encoded within the instruction, size of immediate must be < 32 bits n In RV32, I-type instruction, immediate constants are encoded using 12 bits n Note that bit locations of rs1, funct3, rd and opcode are the same as in R-type Simplicity è high performance I-Type format ADDI Example n C code: n Assume e, y stored in a0, a1 respectively. n RISCV code: ADD t0, a1, a0! ADDI a1, t0, 1!! y = y + e + 1! Why is there no SUBI instruction? 2nd sem. '17-18 ENGG HS 21 2nd sem. '17-18 ENGG HS 22 Unsigned Numbers n Represent non-negative binary numbers (0, 1, 2, 3, ) using their natural binary representations n An n-bit bitstring can represent numbers in "0, # 2 n 1$ % n Represents equally spaced integers on the number line Value Binary Bitstring (8- bit) Two s Complement (1) n Negative numbers are represented by the 2 s complement of the absolute value of that number 2 s complement of an n-bit number v is the value 2 n - v n For example, to represent value -3 using a 4- bit bitstring: = 16-3 = nd sem. '17-18 ENGG HS 23 2nd sem. '17-18 ENGG HS 24

7 Two s complement (2) n 2 s complement of a number can be obtained by adding 1 to the 1 s complement of the number Original s complement s complement n The value of a bitstring { b n 1 b n 2 b 0 } in 2 s complement can be calculated as: 2 n 1 + n 2 i= 0 n Range: Note that is asymmetric 2 i b i [ 2 n 1, 2 n 1 1] Quick Quiz n What is the binary representation of 13? n What is the binary representation of -13? Cannot be represented 4 Cannot be determined based on given information 2nd sem. '17-18 ENGG HS 25 2nd sem. '17-18 ENGG HS 26 Quick Quiz n What are the binary representations of 13 and -13 as 8-bit integers? : : : : n What are the binary representations of 13 and -13 as 12-bit integers? : : : : Sign Extension n The sign of an integer can only be known with the width of integer specified n In 2 s complement representations, the most significant bit (MSB) of an integer denotes its sign: MSB=1 è negative MSB=0 è non-negative n To cast an integer value to a representation with more bits, it must be sign-extended to preserve its sign: If it is negative number, fill the additional bits with 1 If it is non-negative, fill the additional bits with 0 2nd sem. '17-18 ENGG HS 27 2nd sem. '17-18 ENGG HS 28

8 ADDI with negative numbers imm[11:0] rs1 funct3 rd opcode I-immediate[11:0] src ADDI/SLTI[U] dest OP-IMM I-immediate[11:0] src ANDI/ORI/XORI dest OP-IMM n Subtraction with immediate values can be achieved by using negative immediate with ADDI n Recall that immediate constants are 12 bits long in all I-type instructions Range: [-2 11, ] n In general, instructions must clearly specify in its semantics if it is treating the value as signed or unsigned numbers E.g. SLTI vs SLTIU Load Upper Immediate n Load upper bits of immediate constant n Form constants of any values in combination with ADDI, etc n No need for sign extension U-Type format n NOTE: opcode and rd in the same location as most other instructions 2nd sem. '17-18 ENGG HS 29 2nd sem. '17-18 ENGG HS 30 Memory Operations n All program data + instruction originally stored in main memory Array, structure, user data, string, etc n Dedicated instruction to load/store data between register file and main memory n NOTE: registers are much faster than main memory Limited registers availability (32 registers vs. 4GB of memory) Compiler must use registers wisely for best performance RV32 Memory Model n Memory is byte-addressable Each address corresponds to 1 byte of data n Native data types: Word: 32 bit (int) Half-word: 16 bit (short) Byte: 8 bit (char) n RV32 has a Little-Endian byte addressing scheme The least significant byte is at the lowest address 2nd sem. '17-18 ENGG HS 31 2nd sem. '17-18 ENGG HS 32

9 Endianness Big Endian Little Endian Word Alignment int A[20]! A[0]=0xABCD0123! A[1]=0xFACECAFE! 0x000A0007 0x000A0006 0x000A0005 0x000A0004 FE CA CE FA FA CE CA FE n Words are naturally aligned at 4-byte boundary n Half-words naturally aligned at 2-byte boundary 0x000A0007 0x000A0006 0x000A0005 0x000A0004 AB CD AB CD 0x000A0003 0x000A0002 0x000A0001 0x000A CD AB AB CD n RV32I allows nonaligned access Not common in most processors See ISA spec 0x000A0003 0x000A0002 0x000A0001 0x000A0000 AB CD nd sem. '17-18 ENGG HS 33 2nd sem. '17-18 ENGG HS 34 I Memory Operations imm[11:0] rs1 f3 rd opcode S imm[11:5] rs2 rs1 f3 imm[4:0] opcode offset[11:5] src base width offset[4:0] STORE Load: offset[11:0] base width dest LOAD (dest) ß M[(base) + offset] n Immediate is sign extended n LW/SW Word n LH/SH Half Word Store: M[(base) + offset] ß (src) n LB/SB Byte 2nd sem. '17-18 ENGG HS 35 Memory Operations Load n Assume e, f, y stored in a0, a1, a2 respectively. n RISCV code: int y = e + f[3];! lw t0, 12(a1) # 12 = 3 x 4! ADD a2, a0, t0!! n LW, LH, LB instructions load word, half-word and byte from memory 2nd sem. '17-18 ENGG HS 36

10 Memory Operations Store n Assume f is stored in a0. n RISCV code: int f[7] = f[6] + f[5];! lw t0, 20(a0) # 20 = 5 x 4! lw t1, 24(a0)! ADD t0, t0, t1! sw t0, 28(a0)!! n SW, SH, SB instructions store word, halfword and byte to memory Load/Store Instruction Encoding imm[11:0] rs1 funct3 rd opcode o set[11:0] base width dest LOAD imm[11:5] rs2 rs1 funct3 imm[4:0] opcode o set[11:5] src base width o set[4:0] STORE n LOAD instructions are encoded as I-type n STORE instructions are encoded as S-type n funct3 encodes the length (W, H, B) n 12-bit offset is sign extended and added to base address in rs1 n Note the bit location of imm[11:5] and imm[4:0] in S-type 2nd sem. '17-18 ENGG HS 37 2nd sem. '17-18 ENGG HS 38 Branch Operations n Normally programs execute sequentially The next instruction to fetch is normally at location PC + 4 (32 bit) n Decision making constructs requires fetching instruction from run-time determined location if-the-else, do while, goto, switch, etc n RISCV has two types of control transfer instructions: Unconditional jump Conditional branch Motivation: Unconditional Jump n Just like GOTO n RISC-V Assembler supports unconditional jump 0xA000 addi a0, zero, 9! 0xA004 JUMP alabel! 0xA008 ori a0, a0, 27! alabel: 0xBC08 subi a0, a0, 18! 0xBC0C and a1, a1, a0! 0xBC10 <...>! label 2nd sem. '17-18 ENGG HS 39 2nd sem. '17-18 ENGG HS 40

11 Motivation: Conditional Branch n Just like If-Then n Jump only if the branch condition is true 0xA000 addi a0, zero, 9! 0xA004 BEQ a0, a1, alabel! 0xA008 ori a0, a0, 27! alabel: 0xBC08 subi a0, a0, 18! 0xBC0C and a1, a1, a0! 0xBC10 <...>! label Conditional Branches imm[12] imm[10:5] rs2 rs1 funct3 imm[4:1] imm[11] opcode o set[12,10:5] src2 src1 BEQ/BNE o set[11,4:1] BRANCH o set[12,10:5] src2 src1 BLT[U] o set[11,4:1] BRANCH o set[12,10:5] src2 src1 BGE[U] o set[11,4:1] BRANCH n 12-bit branch immediate encoded as signed offset in multiples of 2 E.g. offset[12:1] = 0x00C è jumps to PC + 12*2 = PC + 24 Assembler BEQ rs1, rs2, dest BNE rs1, rs2, dest BLT rs1, rs2, dest BGE rs1, rs2, dest BLTU, BGEU Semantics if rs1=rs2 then branch dest If rs1 rs2 then branch dest If rs1<rs2 then branch dest If rs1 rs2 then branch dest Unsigned comparison of BLT, BGE SB-Type format 2nd sem. '17-18 ENGG HS 41 2nd sem. '17-18 ENGG HS 42 Unconditional Jump-and-Link imm[20] imm[10:1] imm[11] imm[19:12] rd opcode o set[20:1] dest JAL n Semantics: Unconditional jump to PC+offset*2 Store return address (PC+4) in rd Jump n J-immediate encodes a signed offset in multiples of 2 bytes 20 bits è ±1MiB range n Jump relative to PC n Plain jump (J assembler) use rd=x0 UJ-Type format v = 9! and-link r = sqrt(v)! r = r + 27! n To facilitate function calls Call to function and return to the next instruciton n Convention is to use x1 (ra) as return register 0xA000 addi a0, zero, 9! 0xA004 jal ra, sqrt! 0xA008 addi a0, a0, 27! 0xBC04 <...>! 0xBC08 <...>! 0xBC0C <...>! 0xBC10 return! + 0x1C00 return to 0xA008 0xA008 stored in register ra from the jal instruction 2nd sem. '17-18 ENGG HS 43 2nd sem. '17-18 ENGG HS 44

12 Unconditional JALR imm[11:0] rs1 funct3 rd opcode o set[11:0] base 0 dest JALR n Similar to JAL, except destination is relative to the value of rs1 n Semantics: Unconditional jump to offset + (rs1) Store return address (PC+4) in rd n Note the offset is not offset by multiple of 2 Entirely same as an I-type format instruction I-Type format JAL + JALR for function calls 0xA000 addi a0, zero, 9! 0xA004 jal ra, 0x1C00! 0xA008 addi a0, a0, 27! 0xBC04 <...>! 0xBC08 <...>! 0xBC0C <...>! 0xBC10 jalr zero, ra! 2nd sem. '17-18 ENGG HS 45 2nd sem. '17-18 ENGG HS 46 If-Then-Else Conversion if (a >= b) {!!c = a b! } else {!!c = a + b! }! blt a1, a0, truepart! add a2, a1, a0! j exit! truepart: sub a2, a1, a0! exit : < >! Summary n RISC-V ISA is a new academic RISC ISA used as examples RV32 forms the base set of architectural feature 32-bit architecture 32 General Purpose Register File n Each instruction in an ISA must be uniquely encoded. Encoding and semantics of ISA must tradeoff between hardware efficiency and usability. 2nd sem. '17-18 ENGG HS 47 2nd sem. '17-18 ENGG HS 48

13 SI Prefix Prefix Symbol (base 10) Power (base 10) n Binary prefix more important as order-ofmagnitude increases: 1000 ó ,000,000,000 ó 1,073,741,824 Symbol (base 2) exa E 18 Ei 60 peta P 15 Pi 50 tera T 12 Ti 40 giga G 9 Gi 30 mega M 6 Mi 20 kilo k 3 Ki 10 milli m -3 micro µ -6 nano n -9 pico p -12 Power (base 2) 2nd sem. '17-18 ENGG HS 49