EPC6055 Digital Integrated Circuits EXAM 1 Fall Semester 2013

Transcription

1 EPC6055 Digital Integrated Circuits EXAM 1 Fall Semester 2013 Print Here Student ID Signature This is a closed book exam. The exam is to be completed in one-hundred ten (110) minutes. Don t use scratch paper; show all of your work on these pages. Please print your name on the top of each page. (8 pages including this one) Please check here to indicate that you have received all parts of the exam. Problem 1 Problem 2 Problem 3 Problem 4 Problem 5 Problem 6 Problem 7 (20 points) (30 points) ( 6 points) (10 points) (24 points) (10 points) (10 points) Total for Exam (110 points)

2 Problem 1 (20 points) Logic Representation/Combinational Logic A B out C F A. Represent the logic of the given circuit in the truth table B. Represent the logic of the given circuit in Boolean expression. C. The following Verilog code describes the structure of the given circuit. Fill out the blanks. wire out; a (,, ); b (,, ); D. The following Verilog code describes the behavior of the given circuit using assign statement. Fill out the blanks. wire F; assign ; E. The following Verilog code describes the behavior of the given circuit using always block. Fill out the blanks. F; always@( ) begin end Incheon National University Page 2 / 8

3 Problem 2 (30 points) Sequential Logic A. Circle all of the answers that are correct (may be more than one answer). Which of the following are properties of sequential logic? (i) The outputs depends on the present inputs only. (ii) The outputs depends on the present inputs and the past sequence of inputs. (iii) It contains memory. (iv) It can contain combinational logic. (v) It consists of AND,OR, XOR gates only. A B D LOAD Q F clk This figure depicts a D flip-flop with synchronous load. Data on the D input is loaded only if LOAD is 1. B. The following Verilog code describes the behavior of the above circuit using always block. Fill out the blanks. Assume that F is declared properly. always@( ) begin end C. Draw a circuit functionally equivalent to the above flip-flop (in other words, a circuit that has the same behavior of the above flip-flop) using a multiplexer and a regular D flip-flop? D. In Verilog, describe the behavior of the circuit you have drawn above using always block. Assume that F is declared properly. Incheon National University Page 3 / 8

4 Problem 3 (6 points) Verilog/Instantiation A part of the definition of dff module is shown below: module dff(din, clk, q); The following shows an instance of dff module: dff f0(d, clock, out); Another way to write this instantiation in Verilog is as follows. Fill out the blanks. dff f0(. ( ),. ( ),. ( )); Incheon National University Page 4 / 8

5 Problem 4 (10 Points) Verilog/Non-blocking and blocking assignments The following verilog code shows the definition of TEST module. module TEST; reg [3:0] A,B,C,D; initial begin A = 4 b1111; B = 4 b1011; A = B; B = A; C = 4 b1111; D = 4 b1011; C <= D; D <= C; end endmodule A. What are the values of A and B after the simulation of TEST module is done? A:, B: B. What are the values of C and D after the simulation of TEST module is done? C:, D: Incheon National University Page 5 / 8

6 Problem 5 (24 Points) FSM A finite state machine for the BCD to excess-3 code converter is shown below. The FSM has one input (X) and one output (Z). A. Represent the number 2 in the excess-3 code. B. What is the minimum number of flip-flops to implement the above FSM? C. Assume the FSM starts in state S0. Given the following sequence of the input values, what is the resulting sequence of the output values? X: Z: D. What state is the FSM in at the end of the above sequence? Incheon National University Page 6 / 8

7 Problem 6 (10 Points) FSM Design You are supposed to design a sequence detector. The circuit examines string of 0 s and 1 s applied to input X, and generate output Z=1 only when input bit sequence is Input X can change only between clock pulses and the output Z=1 coincident with last 1 in The circuit will keep checking for the proper bit sequence and does not reset to the initial state after it recognized the string. As an example, the input string X= will cause the output to go high twice: Z= Draw a Moore state diagram for the sequence detector. Incheon National University Page 7 / 8

8 Problem 7 (10 Points) Array The definition of module ram is shown below: module ram (q, a, d, we, clk); output [7:0] q; input [7:0] d; input [?:0] a; input clk, we; reg [7:0] mem [127:0]; clk) if(we) mem[a] <= d; assign q = mem[a]; endmodule A. What should the size (bit-width) of input a be to access all the entries in array mem? B. How many bits can be stored in array mem? Incheon National University Page 8 / 8