CHAPTER 5. CHE BASED SoPC FOR EVOLVABLE HARDWARE

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1 90 CHAPTER 5 CHE BASED SoPC FOR EVOLVABLE HARDWARE A hardware architecture that implements the GA for EHW is presented in this chapter. This SoPC (System on Programmable Chip) architecture is also designed on CHE (Complete Hardware Evolution) methodology. Simple combinational adder circuits are evolved using this architecture. The programming structure of CGP (Cartesian Genetic Programming) is modeled into the search space for the evolution of the circuits. Power estimation for the evolved circuits is also carried out. This chapter is organized as follows; section1 presents the architectural details of the implementation, section 2 presents the issues involved in the design, section 3 discusses the results obtained and section 4 summarizes the chapter. 5.1 DESIGN ISSUES All reported hardware implementations use external hardware / software support or use boards with multiple FPGAs with interfaced external memory. In contrast, the present work implements the different operations of the GA on a single FPGA leading to a CHE based SoPC framework for EHW. To the best knowledge of the authors, this is the first attempt to CHE based EHW using the CGP programming structure. Every module is indigenously modeled and implemented on the CLB (Configurable Logic Block) of a single

2 91 COTS FPGA. The design criteria for this architecture is to achieve the following characteristics in hardware The flexibility that is inherently available with software CHE based evolution of combinational circuits Achieving scalability with respect to logic slices Minimizing I/O (Input / Output) block utilization Achieving significant reduction in computational delay, leading to a drastic speed - up For each of the circuit to be evolved, the bit size requirements for the encoded genome, the bit size requirements for fitness values and the size of the required memory array are different. Thus, the size of each of these variables has to be decided as per the requirement. Since the code is in HDL (Hardware Descriptive Language), such variations can be incorporated into the design. For EHW, the length of the chromosome runs to hundreds of bits and with appropriate population sizes, they occupy quite a considerable amount of logic slices on the CLB of the FPGA, as the memory used for storing them is also on chip. In the CHE architecture presented in the previous chapter, as the GA proceeds through each generation, the logic slice and I/O block utilization would linearly increase, leading to constrain the number of generations through which the CHE could proceed to achieve the optimized circuit. Thus, a modification was essential for this application. These limitations have been overcome in the present work by enhancing the architecture by adding some extra modules called Flush and Replace Module (FRM), a sorting module along with a module performing elitism (Figure 5.1). Also the fitness evaluation module is designed to completely

3 92 gratify the requirement of evolving completely fit circuits based on the CGP model. With these modifications, the memory size does not linearly grow with scaling in the number of generations. It remains the same as that of the initial population. Hence, a huge conservation in resource utilization is achieved. Though the constantly increasing scale of chip integration seems to provide a solution for scalability in terms of slice logic utilization, the limitation of I/O blocks is still not sufficiently addressed by technology. FRM specifically addresses this critical limitation, facilitating the evolution of digital circuits on a single COTS FPGA. The fundamental programming model around which this architecture has been developed is CGP. CGP is the abbreviated form of Cartesian Genetic Programming. It was developed by Miller et al (1997). However, the term Cartesian genetic programming first appeared in 1999, and was proposed as a general form of genetic programming in Miller & Thomson (2000). It is called Cartesian because it represents a program using a two-dimensional grid of nodes. In CGP, programs are represented in the form of directed acyclic graphs. These graphs are represented as a twodimensional grid of computational nodes. The genes that make up the genotype in CGP are integers that represent where a node gets its data, what operations the node performs on the data and where the output data required by the user is to be obtained. When the genotype is decoded, some nodes may be ignored. This happens when node outputs are not used in the calculation of output data. The program that results from the decoding of a genotype is called a phenotype. The genotype in CGP has a fixed length. However, the size of the phenotype (in terms of the number of computational nodes) can be anything from zero nodes to the number of nodes defined in the genotype (Miller 1999).

4 93 In the process of correlating the above programming structure in to a hardware realization, the current work has a two dimensional array of m * n configurable logic cells as the search space for the evolution of digital combinational circuits. Each cell here is a digital gate with two inputs and one output. Since ten different logical functions are under consideration, their representation requires a bit string which is 4 bits wide. Table 5.1 gives the ten functionalities that these digital blocks are allowed to perform and the bit strings used for representing them in the encoded genome. Table 5.1 Logical functions and their corresponding bit strings used in encoding Bit String Logical Function 0000 NAND 0001 NOR 0010 XNOR 0011 NOT (IN0) 0100 NOT (IN1) 0101 WIRE (IN0) 0110 WIRE (IN1) 0111 AND 1000 OR 1001 XOR NOT (IN0) means the output is the inverted form of first input, and NOT (IN1) means the output is the inversion of the second input to the CLB. The CLBs are equipped to connect to distant gates, with the identity function of WIRE (IN0) for first input and WIRE (IN1) for the second input of the CLB under consideration. The other specified gates function in the regular manner with two inputs.

5 94 The inputs to the first column of cells are the external inputs of the system. The rest of the columns get their inputs from the outputs of the preceding column of cells. The number of cells used in the last column is equal to the number of outputs of the system. Feedback is not considered. The configuration bits for each cell are called an allele. An allele describes the inputs to the cell and the logical function that the cell is configured to perform. The number of bits i required to represent each input of the cell depends on the total number of inputs x available, viz. log 2 x. That is, if the available number of inputs to a particular column of cells is three, then we need to allot, at least 2 bits for representing each input port of the cell. Hence, to represent the two inputs of each digital gate, 2i bits are required. Since the cells are designed to take up 9 different logical operations as presented in Table 5.1, a minimum of 4 bits are essential to represent these 9 different logical functions of each configurable cell. Thus, the number of bits required for representing each of allele is 2i + 4. The length of the genome depends on the number of cells in the selected 2 D array. The genome is formed by concatenating the configuration bits of all the cells in the array. The strength of the population is 32 chromosomes, which stays constant, irrespective of the number of generations through which the GA passes. A two dimensional array of size 32 * (length of genome) is required for storage of the current population. The fitness of each chromosome is evaluated and that is separately stored in the fitness memory. Since chromosomes are a collection of credible solutions to the problem at hand, they should indoctrinate into their structure the objectives and advantages of the elucidation at hand. This encoding format introduces spatial redundancy and representational degeneracy into the chromosome. These features provide fault tolerance capability to the chromosome. These aspects of the chromosomal encoding are exhaustively analyzed in the next chapter. The entire framework incorporating the issues discussed here is presented in detail in the following section.

6 THE SoPC ARCHITECTURE FOR EHW The proposed architecture consists of eight main modules, which is built as a SoPC on a COTS FPGA. The required memory module is also placed within the CLBs of the FPGA. The generic process involved in the evolution of circuits is initiated from the Random Number Generator. Figure 5.1 shows the block diagram of the proposed system Random Number Generator (RNG) Random number generation is of great importance for the proper operation of the GA. A Linear Feedback Shift Register (LFSR) is used here, as it is easy to implement and produces fairly good pseudo-randomness. The RNG generates the initial population of 32 chromosomes, of the required size. The seed for the RNG here is also programmable, which means that the user can supply this input parameter. This enables different convergence characteristics for each generation. These chromosomes are then stored in an array of 2 dimensional registers which forms the memory module Memory Module (MM) The memory module consists of two separate memories, one for the chromosomes (Chromosome Memory) and the other for their fitness values (Fitness Memory). These are 2 D arrays of registers for storing the chromosomes and their fitness values. The initial population of randomly generated chromosomes is stored in the chromosome memory. Since memory is also on chip, it can be accessed at full clock speed but would occupy significant physical area. Now the individual chromosomes are passed to the fitness evaluation module for fitness calculation.

7 96 Figure 5.1 Block schematic of the proposed architecture Fitness Evaluation Module (FM) The FM module evaluates the fitness for each genome in accordance with the different fitness functions defined for each of the circuit under consideration. The fitness of each chromosome is evaluated and stored in the fitness memory of the memory module. For each functional circuit that is being evolved, it is the FM which needs to be modified; the rest of the system is very much the same.

8 97 Every chromosome that reaches the FM is decoded with respect to function of each cell and its interconnections with the neighbouring cells for the defined 2 D array of cells. The resulting structure is subjected to all possible input combinations and the outputs are recognised. The acquired outputs are then verified to match with the required truth table of the circuit. All of this is done in hardware, on the CLB of the FPGA. For every correct output, a counter is incremented to reach the final value. If the specified output is reached by the counter, then a fully functional circuit is said to have been evolved Sorting Module (SRM) After the process of fitness evaluation of chromosomes in the whole population, the chromosomes and their corresponding fitness values are arranged in descending order of their fitness by the sorting block in the MM. If the required fitness is not obtained, the genetic operators, viz. selection, crossover and mutation are evoked RNG (5 bit) The five bit RNG generates two random numbers. These numbers are used to index to the chromosome memory and the corresponding two chromosomes are chosen to be operated on, by the selection module. They would compete among themselves to become one of the parents for the process of crossover. Two sets of random numbers are generated for the process of selecting the two parents Tournament Selection (TS) This module handles the two pairs of selected chromosomes. For each pair, a tournament is conducted - out of these two chromosomes; the one

9 98 with the highest fitness is selected as one of the parent. The selection of both the parents is executed in the same manner. TS is chosen here as the method for selection as every chromosome has an equal probability of being chosen as a parent. Thus, even the weak chromosomes have a chance to participate in the process. After selection, the two parents are passed on to the crossover module Crossover Module (CM) The crossover operator is mainly responsible for the search aspect of the genetic algorithm. The crossover module operates on the two selected parent chromosomes to give two new off - springs. The CM implemented here is designed to perform single point cross over on the selected parents. The resulting child chromosomes are then transferred to the mutation module Mutation Module (MUM) The operation of mutation is performed by the mutation module. To adopt the concept of introducing variation into the genome, mutation is applied to alter the genes randomly with a certain probability. The mutation module introduces single bit flip operation, based on a probability condition. The mutant is then sent to the FM module for calculation of its fitness. After the evaluation of the child chromosomes they are sent to the Flush and Replace Module Flush and Replace Module (FRM) This module along with the elitism block is mainly responsible for the slice logic conservation advantage of this CHE implementation. This checks and compares the two least fit genomes of the population with the two child genomes newly generated. If the fitness of the new genomes is better

10 99 than the existing genomes of the population, then the generated genomes flush out the weakest two genomes and occupy their position in the population. The corresponding fitness values are also suitably substituted. The resulting new population is now called the next generation, over which the iterative process of evolution continues Elitism Elitism is used while creating a new population using the newly generated child chromosomes. This block is used by the flush and replace block to compare between the chromosomes and eliminate the weakest genome of the whole population. Thus, the best chromosomes are retained in the population. The FRM module together with the Elitism block is designed to accomplish the job of comparison and replacement. Thus, the population size and its corresponding memory requirement remain constant, irrespective of the number of generations that the process may have to traverse. This helps in the conservation of silicon with the passage of each generation. The drastic reduction in computational delay is an advantage of most hardware implementations. Additionally, since this architecture is designed as a SoPC, it eliminates all complicated communication protocols, interfaces and other hardware resources. Behavioral modeling of the complete framework is done using the HDL, Verilog. Synthesis and simulation of the HDL code is executed using Xilinx ISE 9.1i simulator. Each module is indigenously modeled and implemented on the CLB of a single off-the-shelf FPGA.

11 RESULTS AND PERFORMANCE ANALYSIS Evolution of combination circuits is performed using the developed framework. The GA parameters used by the framework are presented in Table 5.2. Table 5.2 Parameters used for evolution Parameter Population size 32 Length of the chromosome Selection Crossover Mutation Termination criteria Dimension 24 bits: Half Adder: 2 i/p bits, 2 o/p bits. 64 bits: Full Adder: 3 i/p bits, 2 o/p bits. 78 bits: 2 bit adder: 5 i/p bits, 3 o/p bits. Tournament Selection Single point crossover One bit mutation 1000 generations or evolution of fit circuit. parameters. The results obtained are discussed with respect to the following (i) (ii) (iii) (iv) Evolution of completely fit circuits Resource utilization on different FPGAs Computation time Power consumption of the evolved circuits Evolution of Circuits As proof of concept, three circuits, a half adder, a full adder and a 2 bit adder have been synthesized using the designed architecture. For the

12 101 design of a half adder circuit, an array of 2 x 2 cells is chosen. Each allele is 6 bits wide. The length of each chromosome in the population is 24 bits (4cells x 6bits). The memory array required for the storage of the chromosomes is 32 x 24 bits wide. For the half adder, there are only 4 different possible input combinations. If correct outputs are obtained for all of these 4 input combinations, then the fitness value is 4 (Table 5.3). For every correct output, a fitness counter is incremented by 1 in the FM. Thus, the fittest half adder circuit has a fitness value of 4. Three bits are required to store the highest fitness value for this circuit, and the required fitness memory is an array of size 32 x 3 bits. Table 5.3 gives the different evolved chromosomes (in hexadecimal format) for the half adder circuit and the number of generations after which these completely fit chromosomes for this function have been achieved with different seeds for the LFSR. Sample circuits of the evolved chromosomes are presented in Figure5.2. The evolved chromosome that the Figure 5.2 (a) represents is EB747B and that which Figure 5.2 (b) represents is DA6803. Thus, every chromosome evolved presents a different structure but perform the same function. Table 5.3 Evolved 100% fit chromosomes for Half Adder Evolved chromosome Fitness value No. of Generations taken for evolution DA EB747B E60F

13 102 (a) EB747B (b) DA6803 Figure 5.2 Two sample circuits of the evolved half adders The evolved chromosomes for a full adder circuit are presented in Table 5.4. Here, an array of 8 cells is used as the search space. Each allele is now 8 bits wide. The length of each chromosome is 64 bits (8 cells x 8 bits). The memory array required for the storage of these chromosomes is 32 x 64 bits. The full adder circuit has 8 possible input combinations, if the evolved circuit produces correct output for all these 8 input states then it is the fittest circuit and its fitness value is 8 (Table 5.4). Four bits wide registers are required to store the highest fitness value of this circuit, hence for storing the fitness of all chromosomes of the population a memory array of size 32 x 4 bits is required. The encoded chromosomal hexadecimal form of Figure 5.3 is 694F This sample evolved chromosome is decoded and the resulting circuit is presented here. These decoded circuits are presented to exhibit the novelty of EHW. No human engineered circuit has such structures. Sometimes it is said that the circuits evolved are just black boxes which may not be decoded and fully understood by human knowledge (Thompson & Layzell 1999).

14 103 Table 5.4 Evolved 100% fit chromosomes for full Adder Evolved chromosome Fitness value No: of Generations taken for evolution. 694f f3f f8f f8ff Figure 5.3 Sample circuit of an evolved full adder (694F ) Fit chromosomes have been evolved right from just four generations to a few hundred generations as seen in Table 5.3 and Table 5.4. Some circuits did not even have resource over heads in terms of the number of gates used for the functioning of the circuit. Irrespective of the number of generations through which the system has to traverse, the slice utilization remains the same because of the designed framework Resource Utilization Table 5.5 presents the comparison on the basis of resource utilization between the previous CHE framework of the previous chapter and

15 104 the current framework for the realization of half adder circuits using CHE on a Spartan 3 FPGA. The FM module of the previous architecture was redesigned for circuit evolution of half adder circuit and synthesized. It can be seen from Table 5.5a. that, for the previous architecture presented, the resources available on the COTS FPGA are not sufficient for the system to traverse through just nine generations. Over utilization is observed for both the slice logic and 4 input LUT s. Scaling in silicon utilization and Input / Output blocks is also observed with increase in the number of generations. Whereas, for the same circuit with the presented framework and the additional modules incorporated, it is seen to occupy only 69% of the slices, 61% of the 4 input LUTs and just 5% of the available Input / Output blocks as presented in Table5.5.b. Here the resource utilization does not scale up with increasing generational count. Hence, any limitation on the number of generations through which the system needs to evolve to reach its perfectly functional state is now removed. The resource utilization for this architecture synthesized on a Spartan 3 FPGA, is illustrated in Figure 5.4. Table 5.5a Resource utilization for the architecture presented in chapter 4 on a Spartan 3 FPGA for EHW Resources Available on the FPGA Utilization for just 5 generations Utilization in % Utilization for just 9 generations Utilization in % Slices % % 4 I/P LUT S % % IOB s % %

16 105 Table 5.5b Resource utilization for the CHE based EHW architecture (Figure 5.1) on a Spartan 3 FPGA Resources Available on the FPGA Utilization with the presented architecture Utilization in %. Slices % 4 Input LUT S % IOB s % Figure 5.4 Resource utilization for the proposed architecture to evolve a half adder circuit on a Spartan 3 FPGA To substantiate the claim on scalability further, the system has been synthesized on a Virtex 4 FPGA, for three circuits which have different design specifications. They are a half adder, a full adder and a 2 bit adder and the results are presented in Figure 5.5. The 2 bit adder circuit has 5

17 106 inputs (viz., 3 bits to represent the 5 options) and three outputs and hence, a 3 x 3 array of cells is chosen. For each of the three cells in the first column, 10 bits (2 *3bits + 4) are required. Hence, there is a need to allocate a total of 30 bits for the three cells of the first column (3 cells x 10 bits = 30bits). For cells in the successive columns, the number of input options available are the outputs of the previous column which now, is only 3 (feed forward configuration of CGP). Therefore, the size of the allele for these cells needs to be only 8 bits (2 *2 + 4). The total bits required for cells of the second and third columns are 48bits (6 cells x 8 bits = 48bits). Hence, the total chromosome length required for evolving this circuit on a 3 x 3 array is 78 bits, which is more than three times that of a half adder. The memory array required for the storage of the chromosomes is 32 x 78 bits wide. The highest fitness for this circuit is 32 (2 5 ), hence for fitness memory, the array size is (32 x 5) bits. The truth table of a 2 bit adder is eight times that of a half adder. But, it can be seen that, half adder occupies 21%, the full adder occupies 54% and the 2 bit adder occupies only 56% of the available slice logic. It is thus seen that the slice logic utilization for a 2 - bit adder is just about 2.6 times that of a half adder. The I/O (Input / Output) blocks used are 3% for the half adder, 7% for the full adder and just 8% (2.33 times that of a half adder) for the 2 bit adder. Thus, it is observed that the scaling in resource utilization is not linearly increasing in proportion of the complexity of the circuit.

18 107 Figure 5.5 Resource utilization on a Virtex 4 FPGA Computational Delay The drastic reduction in computational delay is an imperative advantage of most hardware implementations. Some computational delays reported in literature are presented in Table 5.6. As the presented architecture is designed as a complete SoPC, the computational delays are reduced to a few nanoseconds as presented in Table 5.7. All complicated communication protocols and interfacing delays have been eliminated. The maximum path delay as presented by the synthesizer in generating the output after the initial start signal for the implemented architecture is presented in Table 5.7. Thus, a huge speed up has been achieved by shifting to CHE based hardware.

19 108 Table 5.6 Reported computational delays in literature for EHW Developer Category Computational Delay Sekanina & Friedl (2004) Customised architecture: VRC (3 bit adder) sec Bao et al (2008) Extrinsic (Full adder) 27 sec Vavouras et al (2009) Fernando et al (2010) Intrinsic (Function Optimisation) On chip evolution using Power PC and external RAM memory (Function Optimisation) 2.19 ms ms Table 5.7 Computational delays of the architecture for evolving different circuits on a Virtex 4 FPGA using CHE Evolved Circuit Half adder Full adder Delay using the proposed architecture 4.31ns 4.79ns 2 bit adder 4.79ns Power Estimation of the Evolved Circuits Using the simulator, the HDL codes for the evolved circuits and the conventional circuits have been synthesized and analyzed for power consumption. The results have indicated that there is no over head in terms of power for the evolved circuits. The observations made based on the experimental results can be summarised as follows:

20 109 Simple combinational circuits have been evolved with this architecture Drastic reduction in the computational delay Conservation on the limited number of available I/O blocks Memory requirements for the chromosomes and their fitness remain the same irrespective of the number of generations traversed to reach the optimum Architecture supports evolution with no limit on the number of generations No over head in terms of power for the evolved circuits 5.4 SUMMARY A complete hardware evolution of a GA engine for EHW based on CGP, has been implemented and tested successfully on a single FPGA. A distinct feature of this implementation is that no other dedicated software or hardware resources are utilized. Even the memory block is built within the FPGA. Thus, a SoPC for EHW has been implemented on a single COTS FPGA. Computational delays of the order of few nanoseconds have been achieved. Hence, the presented architecture with its phenomenal reduction in delay, resource utilization and scalability paves a way for further real time implementations of EHW.

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