Due: Instructor: G. Puvvada
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1 EE457 Homework 18 (not too long Due: Instructor: G. Puvvada in the wooden box outside EEB243 The material which was not tested in the midterm is very important for the final exam. The final exam is supposed to be comprehensive. However, I will be less emphasizing topics such as CPU Performance (chapter #2) on the final Part I (on CLAs) Refer to you class notes. In this course, count "the' delay of an exclusive-or gate- as two gate-delays. This is based on the SOP (sum of products) expression of s = {(a'). (b) + (a). (b')} implementation of the XOR gate which requires two AND gates in the first level followed by an OR gate in the second level. We are not counting inverters as a level of gates. The actual VLSI design of an XOR gate does not use this SOP expression and the delay may be less than 2 gate delay. 1.1 (a) Refer to the 16-bit adder on page 4-19 and calculate delay of the adder design. Is it 5 or 7 or 9 gate-delays? Explain how you arrived at your answer. (b) If you take four of these 16-bit adders and build a 64-bit adder using an additional level of carry-lookahead logic, what would be the delay of such a design. (c) What would be the complexity of gates needed in the SOP implementation of the carry-lookahead logic which can receive eight pairs of p's and g's and also a carry-in (co) and produce cl-c8? By complexity of gates, we ean the highest fan-in (number of input pins) warranted for the AND gates and the highest fan-in warranted for the OR gates to implement the design in 2-level AND-OR logic using SOP (sum of products) expressions. 2 Refer to page 4-29 showing a tree of OR gates. Consider the evaluation of B = A63 + A Al + AD Use 4-input OR gates only. What is the delay (in gate-delays) if you arrange OR gates in a linear cascade? What would be the delay if you arrange in a tree fashion? You do not have to draw any of the two arrangements. Part II Question IV.1 from Final Summer 1993 Part III Question 1 from Final Summer 1995 Part IV Question 1 from Final Fall 1995 <== CANCELLED Part V Question 1 from Final Spring 2000 Part V1 Question 1.1 from Final Fall 2001 ======================================================:
2 (:;ii\ IV. Sot 5..-'1-+'),. :. f points) -+g+8+ i ': 2.4 \". Page I /7 8&457 r Su'93
3 Summer 1995 Name: EE457 Final Exam (40%) Instructor: G. Puvvada Date: Aug. 1, '95 Tues. GFS106 Time: 3:30-5:45 PM SSN: Total points: q 5 ( O 11::15 = perfect score) 1 ( G+6, - - 'J points) \3) Unsigned and signed numbers: 11 Design a 4-bit comparator to compare two UNSIGNED numbers A (A3 A2 Al AD) and B (B382 BI BO) using a 4-bit adder-subtractor given below and additional logic as needed. Hint Consider the overflow in unsigned subtraction as you would do in SL TU instruction implementation. - -'3 A1. A\ ;. '."..8';:..&..,,,_. 8.$ Cc. 83, A 82.. A2. CP 'I b r- 'Z - 4 p A\.fl,,...LI.. 8,(J Ao 11: "1. bo"c --] "'.". c..t L ie.'.,t i A<B. fa B A.>B EE457 Final Summer 95 /7
4 1.2 Design a 4-bit comparator to compare two SIGNED numbers X (X3 X2 Xl XO) and Y (Y3 Y2 Yl YO) using a 4-bit adder-subtractor given below and additional logic as needed. Hint: Consider the overflow in signed subtraction as you would do in SL T instruction implementation. I.;il\!) A3 A').. 8..: \1B:".. r'.'.bi.;. A\ 4. 'l' h, E -f "1 "r..,;.-, A"CB fab IA>& I 1(). EE7 Final Swnme: 95 -.,2'/7
5 Spring 2000 EE4S7 Insttuctor: G. Puvvada Final Exam (40%) Date: May 8,2000 MondaySGM124 Name: Time: 2:00- P:.f- 4 :, 0 t.1 SSN: Totalnints: '" "--- (1O, score) 6+ ICot 2D (Smt 1. ( \:) Basic computer arithmetic (c.rry-look-ah8d adder, inaementer, and denter design>: 1.1 An inaementer is a special case of an adder adding the constant 1 (ONE). Instead of using a full CLA adder for inaementation, a simplified inaementer can be designed as shown below. The ONE to be added can be conveyed at the CO ( carry-in) input. However we would like to consider CO as a variable. Note: 5i = (Ai XOR Bi ) XOR Ci = (Ai XOR 0 ) XOR Ci = Ai XOR Ci Pi = Ai OR Bi = Ai OR 0 = Ai gi = Ai AND Bi =AiANDO =0 Ci = 1 if some earlier adder (FA) generates a carry and all intermediate adders (F As) co-operate and propagate, the same. Since 8i is zero here, the Ci can only be true if there is a carry-in (CO) and all intermediate Pi are true. L 1:N;;=::aii;,lii=i!: A 2- A I A 0 Iff t - a ice C C Pt Ps Ps I I s"- Sf 'I u p3 c3 p2 c2 p1 01 po '. " jo lj,.. tt) tj u I p I New CLL INcl - Vcc Write the boolean equations for Cl, C2, C3 produced by the NBW_CLL_INC What is the gate delay of the 4-bit incrementer. Note: Count an XORasa 2-gate delay device. State how you arrived at the value. EE457 Mnal Spring 2{XX) - 1 Pwv8da 2000
6 1.2 Similar to an incrementer, a decrementer is a special case of an adder adding the constant -1 (MINUS ONE). In 2's complement 4-bit signed number system, a minus one is represented as 1111 (all ones). Design a simplified (area efficient, speed efficient) decrementer by simplifying a CLA adder adding Do not assume that the CO is a zero; treat it as a variable. I::ili\ \.E Note: Si = (Ai XOR Bi) XOR Ci = (Ai XOR 1 ) XOR Ci = Ai' XOR Ci = Ai XNOR Ci Pi = Ai OR Bi = Ai OR 1 = gi = Ai AND Hi = Ai AND 1 = Ci = 1 if some earlier adder (FA) generates a carry and all intermediate adders (F As) co-operate and propagate. Since all Pi are here, the Ci can be true if INAW Rit.AII. necl,, A 2.. A. 1 S3 :.c S1,.. II - u,, c..a U, I U g3 c3 -- rnew 92 c2 g1 c1 go JcO CLL DECI -- co 0 u G:. C:-, Write boolean equations for C1, C2, C3, and for the group generate G produced \;J by the NBW_CLL_DEC in the above space Consider a 64-bit decrementer using three levels of the above CLL Number of NEW CLL DEC needed: Number of NEW - BIT-CELL -DEC needed: I-;\ Delay of the 64-bit decrementer in gates: \:.J Note: Count an XOR or an XNOR as a 2-gate delay device The 64-bit decrementer is good to decrement (unsigned numbers only / signed 2'5 oompl numbers only / both unsigned and signed) EE457 Final Spring 2OOJ - 2 / Puvvada 2000
7 Fall 2001 Name: Student ill: EE457 Final Exam (35 Oft) ) _.J r c.to boc) k 1 Qjo UQ Y\C \(. 1 ( I ( points) t S min., g - q Ripple carry adder (RCA), Carry Look-Ahead adder (CLA), delays: r Instrfgctor: Gandhi Puvvada &: 12/ 14/2001, Friday Tke: 2:05-4:35PM THH, Total points: '0 5 Perfect score: CIS I {OS 1.1 Delay of the 2-bit RCA (design#1 on the right) is gate delays. Delay of the 2-bit CLA (design#2 on the right) is gate delays. Delay of a 4-bit RCA is Delay of a 4-bit CLA is gate delays. gate delays Delay of the first 8-bit adder (design #3 below) is gates. Delay of the second 8-bit adder (design #4 below) is gates. EE451 Final Ewn - Pall 2001 Gandhi Puvvada
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