ECE 473 Computer Architecture and Organization Project: Design of a Five Stage Pipelined MIPS-like Processor Project Team TWO Objectives

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1 ECE 473 Computer Architecture and Organization Project: Design of a Five Stage Pipelined MIPS-like Processor Due: December 8, 2011 Instructor: Dr. Yifeng Zhu Project Team This is a team project. All teams should comprise of no more than TWO members. The success of your project will depend greatly on how effectively and cooperatively your group works as a team. Objectives 1. Implements the pipelined MIPS RISC processor core. The following figure is one example implementation. 2. Learn to work as a team to carry out a complex design task requiring task partitioning, effective communication, and cooperation. What to hand in? 1. Project files, submitted via the homework submission website by December 8 (Thursday). 2. Project reports. You are required to submit a project report by December 9 (Friday). 3. Project presentation. You are required to make a ten-minute project presentation in the class on December 8 (Thursday). Special note: The handout (MIPS Reference Data Sheet) has a typo. sll R[rd] = R[rs]<<shamt; It should be R[rd] = R[rt]<<shamt (change rs to rt) srl R[rd] = R[rs]>>shamt; It should be R[rd] = R[rt]>>shamt (change rs to rt) As a result, each operand input of the ALU needs a MUX. 1. Instruction Set You are to design and implement a five-stage 32-bit pipeline MIPS processor that can carry out the instructions specified in Tables 1, 2 and 3. The tables show the instruction subset to be implemented and examples of instruction encoding; the meaning of the instructions remains the same as in MIPS. Table 1: Basic Instruction Set (R-type) R-Type Instruction Instruction OPCode RS RT RD Shamt Funct add $3, $2, $ addu $3, $2, $ sub $3, $2, $ subu $3, $2, $ and $3, $2, $ or $3, $2, $ nor $3, $2, $ slt $3, $2, $ sll $3, $2, srl $3, $2, sra $3, $2, jr $ nop

2 Note: SLT rd, rs, rt. To record the result of a less-than comparison. Compare the contents of GPR rs and GPR rt as signed integers and record the Boolean result of the comparison in GPR rd. If GPR rs is less than GPR rt, the result is 1 (true); otherwise, it is 0 (false). nop: NOP (No Operation) is the assembly idiom used to denote no operation. The actual instruction is interpreted by the hardware as SLL r0, r0, 0. jr rs, To execute a branch to an instruction address in a register. PC rs. Jump to the effective target address in GPR rs. Execute the instruction following the jump, in the branch delay slot, before jumping. sra rd, rt, sa, (shift word right arithmetic) To execute an arithmetic right-shift of a word by a fixed number of bits. The contents of the low-order 32-bit word of GPR rt are shifted right, duplicating the sign-bit (bit 31) in the emptied bits; the word result is placed in GPR rd. The bit-shift amount is specified by sa. srl rd, rt, sa, (shift right logic)to execute a logical right-shift of a word by a fixed number of bits. The contents of the low-order 32-bit word of GPR rt are shifted right, inserting zeros into the emptied bits; the word result is placed in GPR rd. The bit-shift amount is specified by sa. sll and srl (shift left logic and shift right logic). The textbook specifies these two instructions incorrectly. The textbook says R[rd] = R[rs] << sa or R[rd] = R[rs] >> sa. The MIPS standards says R[rd] = R[rt] << sa or R[rd] = R[rt] >> sa. The source register should be rt, instead of rs. Table 2: Basic Instruction Set (I-type) I-Type Instruction Instruction OPCode RS RT Immediate andi $2, $1, ori $2, $1, slti $2, $1, addi $2, $1, subi $2, $1, beq $1, $2, bne $1, $2, lw $1, 20($2) sw $1, 20($2) lui $1, Note: Table 3: Basic Instruction Set (J-type) I-Type Instruction Instruction OPCode Address j L jal L j target. (jump) Jump to the effective target address. jal target. (jump and link) Jump to the effective target address. jal is commonly used for function calls. jal should really be called laj for link and jump : o Step 1 (link): Save address of next instruction into $ra o Step 2 (jump): Jump to the given label Pseudo-instructions While the binary codes provided in this project have already translated the pseudo instructions into real ones, you are still need to understand pseudo-instructions for processor debugging. A pseudo-instruction is not really 2

3 a MIPS instruction but it is allowed in assembly language code. The assembler translates a pseudo instruction into MIPS code. This makes the job of writing this assembly language code easier. For example, la $t0, array where $t0 is pointer into an array of integers. If this integer array is assigned address 0x00aa0bb0, then the assembler will assign the value 0x00aa0bb0 to $t0. However, while the memory address is 32 bits, one machine instruction is only 32 bits wide. Accordingly this assignment can be implemented by using one instruction. As a result, two instructions are required to implement this instruction. lui $t0, 0x00aa # $t0 gets value 0x 00aa 0000 ori $t0, $t0, 0x0bb0 # $t0 gets value 0x 00aa 0bb0 Some other pseudo codes shown in the test program includes: li $s1, 7 lui $1, 0 ori $17, $1, 7 ble $t2, $t3, skip1 slt $1, $11, 10 beq $1, $0, 4 blt $a0, $t0, go_left slt $1, $4, $8 bne $1, $0, 4 la $t0, array lui $t0, 0x00aa # $t0 gets value 0x 00aa 0000 ori $t0, $t0, 0x0bb0 # $t0 gets value 0x 00aa 0bb0 In addition, some non-pseudo instructions are allowed to use immediate numbers, instead of registers, for the sake of conveniences. beq $t4, 0, skip_add ori $1, $0, 0 beq $1, $12, 3 bne $t5, 16, Loop ori $1, $0, 16 bne $1, $13, Instruction Memory and Data Memory In this project, you will use the on-board ROM as the instruction memory and the on-board RAM as the data memory. In addition, we assume that the starting memory address of your instruction segment and data segment are 0x and 0x respectively. In fact, these are specified in MIPS standards. According, you need to make change to the instruction memory module and data memory module to accommodate these requirements. In Quartus II, the shift instructions can be simply implemented as: To_stdlogicvector(To_bitvector(Binput) sll CONV_INTEGER(shamt)) To_stdlogicvector(To_bitvector(Binput) srl CONV_INTEGER(shamt)); 3

4 3. Example Implementation The control signals are also pipelined and the following gives a simple example. Figure 1. An Example of Five Stage Pipelined Processor This above diagram provides an example implementation. There are three controllers, including the main control, the hazard detection unit, and the forward unit. The zero input of the MUX before ID/EX pipeline registers are used to flush out the instruction at the ID/EX stage. The branch is resolved at the ID stage. The forwarding unit will take care of two different types of forwarding operations. The register files allows two operations per cycle: write in the first half cycle and read in the second half cycle. 4

5 4. Smart Compile The compile process may take over twenty minutes. A smart compiler can significantly reduce the compile time. Follow the menu: Processing Compiler Tool Analysis & Synthesis Settings check Use smart compilation 5

6 5. On-board Testing INSTR=FFFFFFFF Value = EEEEEEEE LCD HEX7 HEX6 HEX5 HEX4 HEX4 HEX2 HEX1 HEX0 Toggle swiches Register, Instruction Memory or Data Memory Address Program Counter Clock Counter = Clock Control 0: manual clock 1: 1Hz clock 15,16 = LCD Value 00: Register 01: Data 10: Instruction SW[10-14] Instruction Memory Address SW[5-9] Data Memory Address SW[0-4] Register Address 0 Pushbutton Swiches Manual Clock RESET The project is reset by the push button 0 (KEY[0]). The program counter (HEX5 and HEX4) shows the instruction memory address. The clock counter (HEX0-4) shows how many cycles you design has run and it starts from 0. The LCD has two rows. The first row shows the instruction addressed by the program counter (HEX5 and HEX4). The second row shows the value which is controlled by SW[15-16], which could be a value pointed by a register address SW[0-4], or a data memory address SW[5-9] or a instruction memory address SW[10-14]. The actual address should be shown in HEX7 and HEX6. Your lab should be able to run by using two different clocks: (1) a system 1-Hz clock and (2) a manual clock. Use the switch SW[17] to switch between these two clocks. (If SW[17] = 0, the system 1Hz clock is used. Otherwise the manual clock is used.) Using the system clock allows your code to automatically complete the test programs. The manual clock is generated by the push button 1 (KEY[1]). For each push, generate a HIGH signal for only one second no matter how long the push button is pressed. Note that the LCD still needs the on-board clock. When your program completes, LEDR17 should flash. You can use other LED lights to monitor your control signals. 6

7 6. Milestones & Timeline You have 5 weeks to complete the project. Week # Milestones % of Grades Nov. 10 Pipeline #1: Build the top scheme 10% Thursday You overall diagram should including all components shown in Figure 1, such as pipeline registers, three control units, ALU, register files, instruction memory and data memory, Forwarding from MEM/WB to ALU, Forwarding from EX/MEM to ALU Nov. 17 Thursday Nov. 24 Thanksgiving Nov. 28 Monday Dec. 8 Thursday Dec. 8 Thursday Pipeline #2: pass all required R-type instructions 15% Pipeline #3: pass all required I-Type and J-Type instructions 15% Hazard detection (Read after load) and stall implementation Branch is solved at ID state Hazard detection and stall implementation Pipeline #4: pass the five test programs 50% Write report and do project presentation 10% 7. Bonus Bonus Cool stuff (You define it. Need approval from the instructor before the implementation.) points TBD 8. Project Report Guideline This guideline only gives you some potential items you can address in your project report. You are NOT limited to those listed below. What are the task assignments between you and your project partner? How did you coordinate? Give a table that lists the task assignments and task completion status. Please make it clear and specific. What is the status of your processor design? What problems have you met upon designing, testing and simulation? How did you solve them? What specific design skills or design philosophies you have learned or used in this project? What are your suggestions for me to redesign this project for future ECE 473 students? 9. Project Submission 1. You need to pre-build the FPGA configuration files for all test programs, i.e., when grading, we only need to download your configuration files directly to our Altera FPGA boards without the timeconsuming building process. For example after successfully compiling your project for test program 1, rename the name of your project sof file to test1.sof. During the grading, test1.sof can be directly downloaded to the FPGA boards without time-consuming re-compiling. 2. Submit your report and project files in one compressed file through 7

8 3. submissions are not acceptable due to the large file size and potentially large delay. The server might kill s with a large attachment without notification. 10. Tips: How to Succeed in this Project Based on experience from past semesters, we have several suggestions for you to succeed in this project. 1. Learn VHDL or Verilog. Learn VHDL or Verilog by yourself before you look into the project. Once you know them well, the implementation will be much easier. 2. Work aggressively. This is a heavy project and time consuming. You can NOT finish this project with two or three days, even you spend the whole days on it. 3. Keep you design simple. For example, it is bad idea to allow many component modules to be able to modify the program counter. Complex cross connections between components modules make the debug difficulty. 4. Use vector form simulation to debug. Running your test code on the test boards can quickly tell you whether your design is correct or not. However, it is difficult for debugging due to the limited flexibility. Using waveform simulation can allow you to observe all data and control signals. 5. Make progress gradually. Make a good milestone plan and follow it strictly. 6. Small incremental testing. Make sure each instruction work correctly before you run the test programs. Create a very small program with one or two instructions to test your design. 7. Verification against SPIM or MARS simulator. Compare your running results against the Mars simulation instruction by instruction. Make sure the machine states are consistent. 8

9 Requirements: Milestone 1: R-Type Instructions 10% of Project Grade Due: Thursday, November 10 Implement all components shown in the following diagram. Passing the test programs Figure 1. An Example of Five Stage Pipelined Processor Instruction OPCode RS RT RD Shamt Funct Binary add $3, $2, $ x Test of Basic Diagram Assume the register $i is initialized as a value of i+1. (i.e., $1 = 2, $2 = 3, etc.). Your program should be able to run the following four simple codes (without testing the forwarding and hazard): Test Programs Assembly Codes Binary Codes Results 1 1. add $3, $2, $1 2. nop 3. nop 4. nop 5. nop 2 1. nop 2. add $3, $2, $1 3. nop 4. nop 5. nop 0x : 0x x : 0x x : 0x x c: 0x x : 0x x : 0x x : 0x x c: 0x

10 3 1. nop 2. nop 3. nop 4. add $3, $2, $1 5. nop 4 1. add $3, $2, $1 2. add $6, $5, $4 3. add $9, $8, $7 4. add $12, $11, $10 5. add $15, $14, $13 0x : 0x x : 0x x : 0x x c: 0x x : 0x x : 0x00a x : 0x x c: 0x016a6020 0x : 0x01cd7820 $6 = $9 = $12 = $15 = 2. Test of Forwarding from EX/MEM to ALU Test Programs Assembly Codes Binary Codes Results 5 1. add $3, $2, $1 2. add $4, $3, $1 3. nop 4. nop 5. nop 0x : 0x x : 0x x : 0x x c: 0x add $3, $2, $1 7. add $4, $1, $3 8. nop 9. nop 10. nop 0x : 0x x : 0x x : 0x x c: 0x $4 = $4 = 3. Test of Forwarding from MEM/WB to ALU Test Programs Assembly Codes Binary Codes Results 7 1. add $3, $2, $1 2. nop 3. add $4, $3, $1 4. nop 5. nop 0x : 0x x : 0x x : 0x x c: 0x add $3, $2, $1 2. nop 3. add $4, $1, $3 4. nop 5. nop 9 1. add $3, $2, $1 2. add $3, $4, $5 3. add $4, $1, $3 4. nop 5. nop 0x : 0x x : 0x x : 0x x c: 0x x : 0x x : 0x x : 0x x c: 0x $4 = $4 = $4 = 10

11 Milestone 2: R-Type Instructions 15% of Project Grade Due: Thursday, November 17 In this milestone, your pipeline processor need to successfully run the required R-Type MIPS instructions required in the following table. R-Type Instruction Instruction OPCode RS RT RD Shamt Funct add $3, $2, $ addu $3, $2, $ sub $3, $2, $ subu $3, $2, $ and $3, $2, $ or $3, $2, $ nor $3, $2, $ slt $3, $2, $ sll $3, $2, srl $3, $2, jr $ nop Test program (It does not have any logic meaning.) #Assume $1 = -30 (0xFFFFFFE2), $2 = 56 (0x ). Set $1 and $2 before running the test. 1 add $3, $2, $1 2 addu $3, $2, $1 3 sub $3, $2, $1 4 subu $3, $2, $1 5 and $3, $2, $1 6 or $3, $2, $1 7 nor $3, $2, $1 8 slt $3, $2, $1 9 sll $3, $2, 1 10 srl $3, $2, 1 11 jr $2 12 nop 11

12 Instruction Address Code Value of $3 1 add $3, $2, $1 0x x addu $3, $2, $1 0x x sub $3, $2, $1 0x x subu $3, $2, $1 0x c 0x and $3, $2, $1 0x x or $3, $2, $1 0x x nor $3, $2, $1 0x x slt $3, $2, $1 0x c 0x a 9 sll $3, $2, 1 0x x srl $3, $2, 1 0x x jr $2 0x c 0x PC = 12 nop 0x x N/A Simulate the test program and print the diagram. The diagram needs to show at least PC, 32-bit Instruction, and value of $3. 12

13 Milestone 3: I-Type and J-Type Instructions 15% of Project Due: Monday, November 28 In this milestone, your pipeline processor need to successfully run the required I-Type and J- Type MIPS instructions required in the following table. I-Type Instruction Instruction OPCode RS RT Immediate andi $2, $1, ori $2, $1, addi $2, $1, beq $1, $2, bne $1, $2, lw $1, 20($2) sw $1, 20($2) lui $1, J-Type Instruction Instruction OPCode Address j L jal L Test program for arithmetic ori $1, $0, 0x1 ori $2, $0, 0x2 ori $3, $0, 0x3 ori $4, $0, 0x4 andi $5, $1, 0x10 addi $5, $3, 0x13 Simulate the test program and print the diagram. The diagram needs to show at least PC, 32-bit Instruction, and value of $5. Print out your simulation diagram. Instruction Address Code Results 1 ori $1, $0, 1 0x x $1 = 2 ori $2, $0, 2 0x x $2 = 3 ori $3, $0, 3 0x x ori $4, $0, 4 0x c 0x $4 = 5 andi $5, $1, 16 0x x $5 = 6 addi $5, $3, 19 0x x $5 = 13

14 2. Test program for beq ori $1, $0, 1 ori $2, $0, 1 beq $1, $2, L nop ori $4,$0, -1 L: ori $3, $0, 1 If the codes run correctly, then $4=0 and $3=1. If $4=-1, then your project does not jump correctly. Print out your simulation diagram. Instruction Address Code Results 1 ori $1, $0, 1 0x x $1 = 2 ori $2, $0, 1 0x x $2 = 3 beq $1, $2, L 0x x PC = 4 nop 0x c 0x ori $4, $0, -1 0x x3404ffff $4 = 6 ori $3, $0, 1 0x x Test program for bne ori $1, $0, 1 ori $2, $0, 2 bne $1, $2, L nop ori $4,$0, -1 L: ori $3, $0, 1 If the codes run correctly, then $4=0 and $3=1. If $4=-1, then your project does not jump correctly. Print out your simulation diagram. Instruction Address Code Results 1 ori $1, $0, 1 0x x $1 = 2 ori $2, $0, 2 0x x $2 = 3 bne $1, $2, L 0x x PC = 4 nop 0x c 0x ori $4, $0, -1 0x x3404ffff $4 = 6 L: ori $3, $0, 1 0x x Test program for jump ori $1, $0, 1 j, L nop ori $4,$0, -1 L: ori $3, $0, 1 14

15 If the codes run correctly, then $4=0 and $3=1. If $4=-1, then your project does not jump correctly. Print out your simulation diagram. Instruction Address Code Results 1 ori $1, $0, 1 0x x $1 = 2 j L 0x x PC = 3 nop 0x x ori $4, $0, -1 0x c 0x3404ffff $4 = 5 L: ori $3, $0, 1 0x x Test program for jump-and-link ori $1, $0, 1 jal, L nop ori $4,$0, -1 L: ori $3, $0, 1 The jal instruction saves the return address in register $31. This register is also called $ra (where "ra" means return address). If the codes run correctly, then $4=0 and $3=1. If $4=-1, then your project does not jump correctly. In addition, $31 should be correctly set. Print out your simulation diagram. Instruction Address Code Value of $4, $3, and $31 1 ori $1, $0, 1 0x x jal L 0x x0c PC = $31 = 3 nop 0x x ori $4, $0, -1 0x c 0x3404ffff $4 = 5 L: ori $3, $0, 1 0x x

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