Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web: Ph:

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1 Serial : 2BS_CS_C_Computer Orgnisation_248 Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web: info@madeeasy.in Ph: CLASS TEST 28- COMPUTER SCIENCE & IT Subject : Computer Organization Date of test : 24//28 Answer Key. (c) 7. (a) 3. (b). (b) 25. (b) 2. (c) 8. (d) 4. (b) 2. (c) 26. (c) 3. (c). (c) 5. (c) 2. (b) 27. (b) 4. (b). (b) 6. (d) 22. (d) 28. (a) 5. (b). (d) 7. (a) 23. (b) 2. (d) 6. (a) 2. (c) 8. (c) 24. (a) 3. (b)

2 CT-28 CS Computer Organization 7 Detailed Explanations. (c) PC holds the value of next instruction to be executed. We store the value of PC to MBR and value of stack pointer to MAR. Then store the value of PC which is available in MBR to location addressed by MAR. Atlast vector address return to the PC. This can be done in interrupt subprogram initialization. 2. (c) Execution time for pipeline = (k + n ) tp where k = Number of stages n = Number of instruction tp = Execution time = Max (all stages) P = [8 + 5 ] 8 = 456 P 2 = [5 + 5 ] 5 = 252 Time saved using P 2 = = 536 nsec =.536 µsec 3. (c) In relative addressing mode content of the program counter is added to the address part of the instruction to get the effective address. 4. (b) ADD R, R, 2 R 3 SUB R, 3 R, R 2 ADD R, 2 R, R 3 ADD R, R, 2 R 3 RAW (In-Out) dependancy between consicutive instruction is considered only. 5. (b) For second it take byte 64k So for 64 kbyte it takes = = 64 µsec Main memory latency = 64 µsec Total time required to fetch = 64 µsec + 64 µsec = 28 µsec 6. (a) S : Cache solely works on principle of locality i.e., temporal locality and spatial locality. S 2 : The performance of a system depends on the indirect proportion of memory accesses satisfied by cache. 7. (a) Opcode Register Memory Opcode bit = log 2 7 = 8 Register address bit = log 2 37 = 6 Memory address bit = 32 (8 + 6) = 8 = 2 8 words = bytes = 2 2 bytes = MB 32

3 8 Computer Science & IT 8. (d) 2 s Complement of 72 is Append at LSB and start from right end taking pair of two symbols which are encoded as. +. (c) Actual Booth Multiplier Recorded + Average CPI = Σ C i I i = = =.87. (b) CISC processor contain less registers and larger instruction set.. (d) IF ID EX MA WB IF ID EX MA WB S = Stall 4 cycles are required. IF ID S S S EX MA WB IF ID S S S S S S EX MA WB 2. (c) Number of lines = 8 K 6 2 Number of sets = Physical address size = 28 bits 2 way set associative cache. Address format 28 bit Tag SO WO 6 bit log 2 log26 = 4 bit CFED B

4 CT-28 CS Computer Organization 3. (b) Main m/m size = 28 M byte = 2 27 byte = 27 bits Cache memory size = 6 kbytes Block size = 32 bytes Number of lines (N) = 4 6 kb=52 2 = = kb 2 Number of Sets (S) = N 2 = = 2 2 P Way 2 27 Tag Sets Word Offset 7 5 bits 7 log 2(2 ) log 2(32) = 5 bits = 7 bits TAG bits = 27 (7 + 5) = 5 bits 4. (b) Stages of Pipeline WB EX ID IF I I 3 I 3 I 4 I 4 I 4 I 2 I 3 I 3 I I 2 I 3 I 2 I I I 2 I 2 I 3 I 4 I 4 I 4 I I 2 I 3 I 3 I Number of Clock Cycles 5. (c) Number of sets = 2 = mod = 2 Hence the block 232 will map to set (d) Sum = Z =, C =, O =, S = 7. (a) Number of bits for control signals in vertical programming: log 2 (2) + log 2 () + log 2 (4) + log 2 (27) + log 2 (7) = = 4 bits 256 CW = 8 bits VCW: Branch condition VCW size = = 22 bits Vertical control memory size = bits = bytes 8 = 74 bytes Flag Control field Control memory address 4 8

5 Computer Science & IT 8. (c) 32 op code Source Source 2 6 K words 4 bits needed for addressing Number of op-codes possible = 2 4 = 6 Remaining op-codes = 6 2 = 4 Number of one address instructions = = 64 K. (b) Speed up = 4 = t n tp = CP I CP I n P # instruction Cycle time # instruction Cycle time CPI n ( ) (5) n p CPI n = 2 = 4 = (c) Choice A is "register" addressing, which is supported by this architecture. Choice B is also typically covered when manufacturers speak of "register" addressing, which is supported by this architecture. Choice C is "immediate" (or "literal") addressing, which is not supported by this architecture. Choice D is "direct" (or "absolute") addressing, which is supported by this architecture. Choice E is "indirect" (or "memory indirect") addressing, which is supported by this architecture. 2. (b) Time taken by I/O device = 6 MB 28sec 28 kb = 22. (d) (i) Percentage time CPU is busy = = 82.5 The address decoder enables the device to recognize it s address when this address appears on the address lines. (ii) Control circuitry is required to coordinate I/O transfers. (iii) The data register holds the data being transferred to or from the processor. The status register contains information relevant to the operation of the I/O device. Bus Address lines Data lines Control lines Address decoder Control circuit Data & Status registers Input device

6 CT-28 CS Computer Organization 23. (b) The required probability = C 3 (.35) 3 (.65) 7 = (a) 4 way set associative Number of lines = 28 Number of sets = 28 4 = 32 Block size = 64 words TAG Set offset Word offset 2 (5 + 6) bits 5 bits 6 bits A : In addresses bit numbers ( 4) will decide the set number in cache memory. A 8, B 6, C, D 25. (b) Average Number of stalls per instruction = (# misses per instruction in L Hit time in L 2 ) + (# misses per instruction in L 2 Miss penalty of L 2 ) 2.5 memory references per instruction 2.5 instructions for references = 4 instructions. Average number of stalls per instruction = = = cycles. 26. (c). Since the cache line size is 8 bytes, the smallest unit of data transfer into cache from L2 cache or memory is 8 bytes. So if we have a miss for A[], both A[] and A[] get fetched into cache. 2. The cache is addressed by the lower bits of the address. However the address is byte address, and since a cache line can hold 8 bytes, the lower three bits of the address are used to address bytes inside a cache line. Since the cache is 2K bytes large, it has 2K/8 = 256 cache lines, which are addressed by 8 bits. Hence: bits -2 form the "offset", which is used to address inside a cache line bits 3 through of the address form the cache line address. Bits -32 form the TAG. (assuming a 32 bit architecture) Now, Consider the sequence : (2 iterations of the loop ) load A[] causes A[] and A[] at cache line load B[] *also addresses cache line * - so overwrites A[] & A[] above store A[] Nothing happens to cache (no write allocate) -> 8 bytes are written (8 is the unit of transfer) load A[] Accesses the SAME cache line as A[] So we load A[] and A[] again into line load B[2] addresses cache line - load B[2] and B[3] into cache line store A[] Again nothing happens as above.

7 2 Computer Science & IT So the pattern might be obvious : At every iteration of the loop, B[2*i] accesses a new cache line, and A overwrites the cache lines every two iterations. Since the loop is 256 iterations, B will just reach cache line 255 when the loop will finish. Since A has been erasing B half as fast, we would have A in the top half of the cache and B in the bottom half. Thus the cache contains : A[]-A[255] (In the top half) and B[256]- B[5] in the bottom half. Also, since the cache is write through, the entries in the cache will always be the freshly written entries. Since this is write through, we have to write 256 words = 24 bytes (all of A) back to the next level (L2 cache or memory). Assuming that the minimum transfer from a cache to a lower level is a cache line, this translates to 248 bytes. 27. (b) I/O ports are placed at addresses on bus and are accessed just like other memory location in computers that uses memory mapped I/O. 28. (a) Increase in the associativity leads to increase in the number of tag comparisons. Hence it leads to increase in cache access time. 2. (d) S : Separate I/O address space does not necessarily mean that I/O address lines are physically separated from the memory address lines. A special signal on the bus indicates that the requested read or write transfer is an I/O operation. S 2 : The address decoder, the data and status register and control circuitry required to coordinate I/O transfers constitute the interface circuit (Hence true). 3. (b). For a single instruction time taken on pipeline CPU is always greater than or equal to the non-pipeline. 2. When all stages have same delay and buffer latency is zero then for a single instruction execution time of pipeline CPU is equal to the execution time of non-pipeline CPU.