0. Overview of this standard Design entities and configurations... 5

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1 Contents 0. Overview of this standard Intent and scope of this standard Structure and terminology of this standard Syntactic description Semantic description Front matter, examples, notes, references, and annexes Design entities and configurations Entity declarations Entity header Generics Ports Entity declarative part Entity statement part Architecture bodies Architecture declarative part Architecture statement part Configuration declarations Block configuration Component configuration Subprograms and packages Subprogram declarations Formal parameters Constant and variable parameters Signal parameter File parameters Subprogram bodies Subprogram overloading Operator overloading Signatures Resolution functions Package declarations Package bodies Conformance rules Types Scalar types Enumeration types Predefined enumeration types Integer types Predefined integer types Physical types Predefined physical types Floating point types Predefined floating point types Composite types v

2 3.2.1 Array types Index constraints and discrete ranges Predefined array types Record types Access types Incomplete type declarations Allocation and deallocation of objects File types File operations Protected types Protected type declarations Protected type bodies Declarations Type declarations Subtype declarations Objects Object declarations Constant declarations Signal declarations Variable declarations File declarations Interface declarations Interface lists Association lists Alias declarations Object aliases Nonobject aliases Attribute declarations Component declarations Group template declarations Group declarations Specifications Attribute specification Configuration specification Binding indication Entity aspect Generic map and port map aspects Default binding indication Disconnection specification Names Names Simple names Selected names Indexed names Slice names Attribute names vi

3 7. Expressions Rules for expressions Operators Logical operators Relational operators Shift operators Adding operators Sign operators Multiplying operators Miscellaneous operators Operands Literals Aggregates Record aggregates Array aggregates Function calls Qualified expressions Type conversions Allocators Static expressions Locally static primaries Globally static primaries Universal expressions Sequential statements Wait statement Assertion statement Report statement Signal assignment statement Updating a projected output waveform Variable assignment statement Array variable assignments Procedure call statement If statement Case statement Loop statement Next statement Exit statement Return statement Null statement Concurrent statements Block statement Process statement Concurrent procedure call statements Concurrent assertion statements Concurrent signal assignment statements Conditional signal assignments Selected signal assignments Component instantiation statements Instantiation of a component vii

4 9.6.2 Instantiation of a design entity Generate statements Scope and visibility Declarative region Scope of declarations Visibility Use clauses The context of overload resolution Design units and their analysis Design units Design libraries Context clauses Order of analysis Elaboration and execution Elaboration of a design hierarchy Elaboration of a block header The generic clause The generic map aspect The port clause The port map aspect Elaboration of a declarative part Elaboration of a declaration Subprogram declarations and bodies Type declarations Subtype declarations Object declarations Alias declarations Attribute declarations Component declarations Elaboration of a specification Attribute specifications Configuration specifications Disconnection specifications Elaboration of a statement part Block statements Generate statements Component instantiation statements Other concurrent statements Dynamic elaboration Execution of a model Drivers Propagation of signal values Updating implicit signals The simulation cycle viii

5 13. Lexical elements Character set Lexical elements, separators, and delimiters Identifiers Basic identifiers Extended identifiers Abstract literals Decimal literals Based literals Character literals String literals Bit string literals Comments Reserved words Allowable replacements of characters Predefined language environment Predefined attributes Package STANDARD Package TEXTIO Annex A (informative) Syntax Summary Annex B (informative) Glossary Annex C (informative) Potentially nonportable constructs Annex D (informative) Bibliography Index ix

The Designer's Guide to VHDL Second Edition

The Designer's Guide to VHDL Second Edition Peter J. Ashenden EDA CONSULTANT, ASHENDEN DESIGNS PTY. VISITING RESEARCH FELLOW, ADELAIDE UNIVERSITY Cl MORGAN KAUFMANN PUBLISHERS An Imprint of Elsevier SAN