COMPUTER ORGANIZATION AND DESIGN


 Horace Flynn
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1 COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 3 Arithmetic for Computers
2 Arithmetic for Computers Operations on integers Addition and subtraction Multiplication and division Dealing with overflow Floatingpoint real numbers Representation and operations 3.1 Introduction Chapter 3 Arithmetic for Computers 2
3 Integer Addition Example: Addition and Subtraction Overflow if result out of range Adding +ve and ve operands, no overflow Adding two +ve operands Overflow if result sign is 1 Adding two ve operands Overflow if result sign is 0 Chapter 3 Arithmetic for Computers 3
4 Integer Subtraction Add negation of second operand Example: 7 6 = 7 + ( 6) +7: : : Overflow if result out of range Subtracting two +ve or two ve operands, no overflow Subtracting +ve from ve operand Overflow if result sign is 0 Subtracting ve from +ve operand Overflow if result sign is 1 Chapter 3 Arithmetic for Computers 4
5 Dealing with Overflow Overflow occurs when the result of an operation cannot be represented in 32bits, i.e., when the sign bit contains a value bit of the result and not the proper sign bit When adding operands with different signs or when subtracting operands with the same sign, overflow can never occur Operation Operand A Operand B Result indicating overflow A + B 0 0 < 0 A + B < 0 < 0 0 A  B 0 < 0 < 0 A  B < 0 0 0
6 Dealing with Overflow Overflow occurs when the result of an operation cannot be represented in 32bits, i.e., when the sign bit contains a value bit of the result and not the proper sign bit When adding operands with different signs or when subtracting operands with the same sign, overflow can never occur Operation Operand A Operand B Result indicating overflow A + B 0 0 < 0 A + B < 0 < 0 0 A  B 0 < 0 < 0 A  B < MIPS signals overflow with an exception (aka interrupt) an unscheduled procedure call where the EPC contains the address of the instruction that caused the exception
7 2 s Comp  Detecting Overflow When adding two's complement numbers, overflow will only occur if the numbers being added have the same sign the sign of the result is different If we perform the addition a n1 a n2... a 1 a 0 +b n1 b n2 b 1 b s n1 s n2 s 1 s 0 Overflow can be detected as V an bn 1 sn 1 + an 1 bn 1 Overflow can also be detected as V = 1 sn 1 = c n cn 1 where c n1 and c n are the carry in and carry out of the most significant bit
8 Unsigned  Detecting Overflow For unsigned numbers, overflow occurs if there is carry out of the most significant bit. V = c n For example, 1001 = = = 1 With the MIPS architecture Overflow exceptions occur for two s complement arithmetic add, sub, addi Overflow exceptions do not occur for unsigned arithmetic addu, subu, addiu
9 Dealing with Overflow Some languages (e.g., C) ignore overflow Use MIPS addu, addui, subu instructions Other languages (e.g., Ada, Fortran) require raising an exception Use MIPS add, addi, sub instructions On overflow, invoke exception handler Save PC in exception program counter (EPC) register Jump to predefined handler address mfc0 (move from coprocessor reg) instruction can retrieve EPC value, to return after corrective action Chapter 3 Arithmetic for Computers 8
10 MIPS Arithmetic Logic Unit (ALU) Must support the Arithmetic/Logic operations of the ISA add, addi, addiu, addu sub, subu mult, multu, div, divu sqrt and, andi, nor, or, ori, xor, xori beq, bne, slt, slti, sltiu, sltu A B zero ovf 1 ALU m (operation) result
11 MIPS Arithmetic Logic Unit (ALU) Must support the Arithmetic/Logic operations of the ISA add, addi, addiu, addu sub, subu mult, multu, div, divu sqrt and, andi, nor, or, ori, xor, xori beq, bne, slt, slti, sltiu, sltu With special handling for sign extend addi, addiu, slti, sltiu zero extend andi, ori, xori overflow detection add, addi, sub A B zero ovf 1 ALU m (operation) result
12 Arithmetic for Multimedia Graphics and media processing operates on vectors of 8bit and 16bit data Use 64bit adder, with partitioned carry chain Operate on 8 8bit, 4 16bit, or 2 32bit vectors SIMD (singleinstruction, multipledata) Saturating operations On overflow, result is largest representable value eg., clipping in audio, saturation in video Chapter 3 Arithmetic for Computers 10
13 Multiply Binary multiplication is just a bunch of right shifts and adds n multiplicand multiplier n partial product array double precision product 2n
14 Multiply Binary multiplication is just a bunch of right shifts and adds n multiplicand multiplier n partial product array can be formed in parallel and added in parallel for faster multiplication double precision product 2n
15 Multiplication Start with longmultiplication approach 3.3 Multiplication multiplicand multiplier product Length of product is the sum of operand lengths Chapter 3 Arithmetic for Computers 12
16 Multiplication Hardware Multiplicand is zero extended (unsigned mul) Initially 0 Chapter 3 Arithmetic for Computers 13
17 Multiplication Example (Version 1) Consider: , Product = bit multiplicand and multiplier are used in this example Multiplicand is zero extended because it is unsigned Iteration Multiplicand Multiplier Product 0 Initialize
18 Multiplication Example (Version 1) Consider: , Product = bit multiplicand and multiplier are used in this example Multiplicand is zero extended because it is unsigned Iteration Multiplicand Multiplier Product 0 Initialize Multiplier[0] = 1 => ADD
19 Multiplication Example (Version 1) Consider: , Product = bit multiplicand and multiplier are used in this example Multiplicand is zero extended because it is unsigned Iteration Multiplicand Multiplier Product 0 Initialize Multiplier[0] = 1 => ADD + SLL Multiplicand and SRL Multiplier
20 Multiplication Example (Version 1) Consider: , Product = bit multiplicand and multiplier are used in this example Multiplicand is zero extended because it is unsigned Iteration Multiplicand Multiplier Product 0 Initialize Multiplier[0] = 1 => ADD + SLL Multiplicand and SRL Multiplier Multiplier[0] = 0 => Do Nothing
21 Multiplication Example (Version 1) Consider: , Product = bit multiplicand and multiplier are used in this example Multiplicand is zero extended because it is unsigned Iteration Multiplicand Multiplier Product 0 Initialize Multiplier[0] = 1 => ADD + SLL Multiplicand and SRL Multiplier Multiplier[0] = 0 => Do Nothing SLL Multiplicand and SRL Multiplier
22 Multiplication Example (Version 1) Consider: , Product = bit multiplicand and multiplier are used in this example Multiplicand is zero extended because it is unsigned Iteration Multiplicand Multiplier Product 0 Initialize Multiplier[0] = 1 => ADD + SLL Multiplicand and SRL Multiplier Multiplier[0] = 0 => Do Nothing SLL Multiplicand and SRL Multiplier Multiplier[0] = 1 => ADD
23 Multiplication Example (Version 1) Consider: , Product = bit multiplicand and multiplier are used in this example Multiplicand is zero extended because it is unsigned Iteration Multiplicand Multiplier Product 0 Initialize Multiplier[0] = 1 => ADD + SLL Multiplicand and SRL Multiplier Multiplier[0] = 0 => Do Nothing SLL Multiplicand and SRL Multiplier Multiplier[0] = 1 => ADD + SLL Multiplicand and SRL Multiplier
24 Multiplication Example (Version 1) Consider: , Product = bit multiplicand and multiplier are used in this example Multiplicand is zero extended because it is unsigned Iteration Multiplicand Multiplier Product 0 Initialize Multiplier[0] = 1 => ADD + SLL Multiplicand and SRL Multiplier Multiplier[0] = 0 => Do Nothing SLL Multiplicand and SRL Multiplier Multiplier[0] = 1 => ADD + SLL Multiplicand and SRL Multiplier Multiplier[0] = 1 => ADD
25 Multiplication Example (Version 1) Consider: , Product = bit multiplicand and multiplier are used in this example Multiplicand is zero extended because it is unsigned Iteration Multiplicand Multiplier Product 0 Initialize Multiplier[0] = 1 => ADD + SLL Multiplicand and SRL Multiplier Multiplier[0] = 0 => Do Nothing SLL Multiplicand and SRL Multiplier Multiplier[0] = 1 => ADD + SLL Multiplicand and SRL Multiplier Multiplier[0] = 1 => ADD + SLL Multiplicand and SRL Multiplier
26 Observation on Version 1 of Multiply Hardware in version 1 can be optimized Rather than shifting the multiplicand to the left Instead, shift the product to the right Has same net effect and produces same results Reduce Hardware Multiplicand register can be reduced to 32 bits We can also reduce the adder size to 32 bits One cycle per iteration Shifting and addition can be done simultaneously
27 Version 2 of Multiplication Hardware Product = HI and LO registers, HI=0 Product is shifted right Reduced 32bit Multiplicand & Adder Start Multiplicand = 1 Multiplier[0]? = 0 32 bits 32 bits 32bit ALU add HI = HI + Multiplicand 33 bits carry 32 bits HI 64 bits LO shift right write shift right Control Shift Product = (HI,LO) Right 1 bit Shift Multiplier Right 1 bit 32 nd Repetition? No Multiplier 32 bits Multiplier[0] Done Yes
28 Refined Version of Multiply Hardware Eliminate Multiplier Register Initialize LO = Multiplier, HI=0 Product = HI and LO registers Start LO=Multiplier, HI=0 = 1 LO[0]? = 0 32 bits Multiplicand 32 bits HI = HI + Multiplicand 32bit ALU 33 bits add Shift Product = (HI,LO) Right 1 bit carry 32 bits HI 64 bits LO shift right write LO[0] Control 32 nd Repetition? Done Yes No
29 Multiply Example (Refined Version) Consider: , Product = bit multiplicand and multiplier are used in this example 4bit adder produces a 5bit sum (with carry) Iteration Multiplicand Carry Product = HI, LO 0 Initialize (LO = Multiplier, HI=0)
30 Multiply Example (Refined Version) Consider: , Product = bit multiplicand and multiplier are used in this example 4bit adder produces a 5bit sum (with carry) Iteration Multiplicand Carry Product = HI, LO 0 Initialize (LO = Multiplier, HI=0) LO[0] = 1 => ADD
31 Multiply Example (Refined Version) Consider: , Product = bit multiplicand and multiplier are used in this example 4bit adder produces a 5bit sum (with carry) Iteration Multiplicand Carry Product = HI, LO 0 Initialize (LO = Multiplier, HI=0) LO[0] = 1 => ADD Shift Right Product = (HI, LO)
32 Multiply Example (Refined Version) Consider: , Product = bit multiplicand and multiplier are used in this example 4bit adder produces a 5bit sum (with carry) Iteration Multiplicand Carry Product = HI, LO 0 Initialize (LO = Multiplier, HI=0) LO[0] = 1 => ADD + Shift Right Product = (HI, LO) LO[0] = 0 => Do Nothing
33 Multiply Example (Refined Version) Consider: , Product = bit multiplicand and multiplier are used in this example 4bit adder produces a 5bit sum (with carry) Iteration Multiplicand Carry Product = HI, LO 0 Initialize (LO = Multiplier, HI=0) LO[0] = 1 => ADD + Shift Right Product = (HI, LO) LO[0] = 0 => Do Nothing Shift Right Product = (HI, LO)
34 Multiply Example (Refined Version) Consider: , Product = bit multiplicand and multiplier are used in this example 4bit adder produces a 5bit sum (with carry) Iteration Multiplicand Carry Product = HI, LO 0 Initialize (LO = Multiplier, HI=0) LO[0] = 1 => ADD + Shift Right Product = (HI, LO) LO[0] = 0 => Do Nothing Shift Right Product = (HI, LO) LO[0] = 1 => ADD
35 Multiply Example (Refined Version) Consider: , Product = bit multiplicand and multiplier are used in this example 4bit adder produces a 5bit sum (with carry) Iteration Multiplicand Carry Product = HI, LO 0 Initialize (LO = Multiplier, HI=0) LO[0] = 1 => ADD + Shift Right Product = (HI, LO) LO[0] = 0 => Do Nothing Shift Right Product = (HI, LO) LO[0] = 1 => ADD Shift Right Product = (HI, LO)
36 Multiply Example (Refined Version) Consider: , Product = bit multiplicand and multiplier are used in this example 4bit adder produces a 5bit sum (with carry) Iteration Multiplicand Carry Product = HI, LO 0 Initialize (LO = Multiplier, HI=0) LO[0] = 1 => ADD + Shift Right Product = (HI, LO) LO[0] = 0 => Do Nothing Shift Right Product = (HI, LO) LO[0] = 1 => ADD Shift Right Product = (HI, LO) LO[0] = 1 => ADD
37 Multiply Example (Refined Version) Consider: , Product = bit multiplicand and multiplier are used in this example 4bit adder produces a 5bit sum (with carry) Iteration Multiplicand Carry Product = HI, LO 0 Initialize (LO = Multiplier, HI=0) LO[0] = 1 => ADD + Shift Right Product = (HI, LO) LO[0] = 0 => Do Nothing Shift Right Product = (HI, LO) LO[0] = 1 => ADD Shift Right Product = (HI, LO) LO[0] = 1 => ADD Shift Right Product = (HI, LO)
38 Faster Multiplier Uses multiple adders Cost/performance tradeoff Can be pipelined Several multiplication performed in parallel Chapter 3 Arithmetic for Computers 20
39 MIPS Multiplication Two 32bit registers for product HI: mostsignificant 32 bits LO: leastsignificant 32bits Instructions mult rs, rt / multu rs, rt 64bit product in HI/LO mfhi rd / mflo rd Move from HI/LO to rd Can test HI value to see if product overflows 32 bits mul rd, rs, rt Leastsignificant 32 bits of product > rd Chapter 3 Arithmetic for Computers 21
40 Unsigned Division (Paper & Pencil) 11 =
41 Division divisor quotient dividend remainder nbit operands yield nbit quotient and remainder Check for 0 divisor Long division approach If divisor dividend bits 1 bit in quotient, subtract Otherwise 0 bit in quotient, bring down next dividend bit Restoring division Do the subtract, and if remainder goes < 0, add divisor back Signed division Divide using absolute values Adjust sign of quotient and remainder as required 3.4 Division Chapter 3 Arithmetic for Computers 23
42 Division Hardware Initially divisor in left half Initially dividend Chapter 3 Arithmetic for Computers 24
43 Division Example Dividend = 0111 Divisor = 0010
44 Optimized Divider Uses two registers: HI and LO Initialize: HI = Remainder = 0 and LO = Dividend Shift (HI, LO) LEFT by 1 bit (also Shift Quotient LEFT) Shift the remainder and dividend registers together LEFT Compute: Difference = Remainder Divisor If (Difference 0) then Remainder = Difference Set Least significant Bit of Quotient Observation to Reduce Hardware: LO register can be also used to store the computed Quotient
45 Optimized Divider Initialize: HI = 0, LO = Dividend Results: HI = Remainder LO = Quotient Chapter 3 Arithmetic for Computers 27
46 Unsigned Integer Division Example Example: / (4bit dividend & divisor) Result Quotient = and Remainder = bit registers for Remainder and Divisor (4bit ALU) Iteration HI LO Divisor Difference 0 Initialize
47 Unsigned Integer Division Example Example: / (4bit dividend & divisor) Result Quotient = and Remainder = bit registers for Remainder and Divisor (4bit ALU) Iteration HI LO Divisor 0 Initialize : Shift Left, Diff = HI  Divisor Difference
48 Unsigned Integer Division Example Example: / (4bit dividend & divisor) Result Quotient = and Remainder = bit registers for Remainder and Divisor (4bit ALU) Iteration HI LO Divisor 0 Initialize : Shift Left, Diff = HI  Divisor : Diff < 0 => Do Nothing Difference
49 Unsigned Integer Division Example Example: / (4bit dividend & divisor) Result Quotient = and Remainder = bit registers for Remainder and Divisor (4bit ALU) Iteration HI LO Divisor 0 Initialize : Shift Left, Diff = HI  Divisor : Diff < 0 => Do Nothing 1: Shift Left, Diff = HI  Divisor Difference
50 Unsigned Integer Division Example Example: / (4bit dividend & divisor) Result Quotient = and Remainder = bit registers for Remainder and Divisor (4bit ALU) Iteration Initialize 2: Diff < 0 => Do Nothing : Rem = Diff, set lsb of LO HI LO Divisor : Shift Left, Diff = HI  Divisor : Shift Left, Diff = HI  Divisor Difference
51 Unsigned Integer Division Example Example: / (4bit dividend & divisor) Result Quotient = and Remainder = bit registers for Remainder and Divisor (4bit ALU) Iteration Initialize 2: Diff < 0 => Do Nothing : Rem = Diff, set lsb of LO HI LO Divisor : Shift Left, Diff = HI  Divisor : Shift Left, Diff = HI  Divisor : Shift Left, Diff = HI  Divisor Difference
52 Unsigned Integer Division Example Example: / (4bit dividend & divisor) Result Quotient = and Remainder = bit registers for Remainder and Divisor (4bit ALU) Iteration Initialize 2: Diff < 0 => Do Nothing 2: Rem = Diff, set lsb of LO : Diff < 0 => Do Nothing HI LO Divisor : Shift Left, Diff = HI  Divisor : Shift Left, Diff = HI  Divisor : Shift Left, Diff = HI  Divisor Difference
53 Unsigned Integer Division Example Example: / (4bit dividend & divisor) Result Quotient = and Remainder = bit registers for Remainder and Divisor (4bit ALU) Iteration Initialize 2: Diff < 0 => Do Nothing 2: Rem = Diff, set lsb of LO : Diff < 0 => Do Nothing HI LO Divisor : Shift Left, Diff = HI  Divisor : Shift Left, Diff = HI  Divisor : Shift Left, Diff = HI  Divisor : Shift Left, Diff = HI  Divisor Difference
54 Unsigned Integer Division Example Example: / (4bit dividend & divisor) Result Quotient = and Remainder = bit registers for Remainder and Divisor (4bit ALU) Iteration Initialize 2: Diff < 0 => Do Nothing 2: Rem = Diff, set lsb of LO : Diff < 0 => Do Nothing 2: Diff < 0 => Do Nothing HI LO Divisor : Shift Left, Diff = HI  Divisor : Shift Left, Diff = HI  Divisor : Shift Left, Diff = HI  Divisor : Shift Left, Diff = HI  Divisor Difference
55 Combined Multiplier and Divider One cycle per partialremainder subtraction Looks a lot like a multiplier! Same hardware can be used for both Chapter 3 Arithmetic for Computers 29
56 Faster Division Can t use parallel hardware as in multiplier Subtraction is conditional on sign of remainder Faster dividers (e.g. SRT devision) generate multiple quotient bits per step Still require multiple steps Chapter 3 Arithmetic for Computers 30
57 MIPS Division Use HI/LO registers for result HI: 32bit remainder LO: 32bit quotient Instructions div rs, rt / divu rs, rt No overflow or divideby0 checking Software must perform checks if required Use mfhi, mflo to access result Chapter 3 Arithmetic for Computers 31
58 Representing Big (and Small) Numbers What if we want to encode approx. age of the earth? 4,600,000,000 or 4.6 x 10 9 weight in kg of one a.m.u. (atomic mass unit) or 1.6 x There is no way we can encode either of them in a 32bit integer Floating point representation (1) sign x F x 2 E Still have to fit everything in 32 bits (single precision)
59 Floating Point Representation for nonintegral numbers Including very small and very large numbers Like scientific notation 3.5 Floating Point In binary normalized not normalized ±1.xxxxxxx 2 2 yyyy Types float and double in C Chapter 3 Arithmetic for Computers 33
60 Floating Point Standard Defined by IEEE Std Developed in response to divergence of representations Portability issues for scientific code Now almost universally adopted Two representations Single precision (32bit) Double precision (64bit) Chapter 3 Arithmetic for Computers 34
61 IEEE FloatingPoint Format single: 8 bits double: 11 bits S Exponent single: 23 bits double: 52 bits Fraction x = ( 1) S (1+ Fraction) 2 (Exponent Bias) S: sign bit (0 nonnegative, 1 negative) Normalized significand: 1.0 significand < 2.0 Always has a leading prebinarypoint 1 bit, so no need to represent it explicitly (hidden bit) Significand is Fraction with the 1. restored Exponent: excess representation: actual exponent + Bias Ensures exponent is unsigned Single: Bias = 127; Double: Bias = 1023 Chapter 3 Arithmetic for Computers 35
62 IEEE FloatingPoint Format All 0 All 0 All 0 All 0 All 1 All 1 All 1 All 1 Chapter 3 Arithmetic for Computers 36
63 SinglePrecision Range Exponents and reserved Smallest value Exponent: actual exponent = = 126 Fraction: significand = 1.0 ± ± Largest value exponent: actual exponent = = +127 Fraction: significand 2.0 ± ± Chapter 3 Arithmetic for Computers 37
64 DoublePrecision Range Exponents and reserved Smallest value Exponent: actual exponent = = 1022 Fraction: significand = 1.0 ± ± Largest value Exponent: actual exponent = = Fraction: significand 2.0 ± ± Chapter 3 Arithmetic for Computers 38
65 FloatingPoint Precision Relative precision all fraction bits are significant Single: approx 2 23 Equivalent to 23 log decimal digits of precision Double: approx 2 52 Equivalent to 52 log decimal digits of precision Chapter 3 Arithmetic for Computers 39
66 FloatingPoint Example Represent = ( 1) S = 1 Fraction = Exponent = 1 + Bias Single: = 126 = Double: = 1022 = Single: Double: Chapter 3 Arithmetic for Computers 40
67 FloatingPoint Example What number is represented by the singleprecision float S = 1 Fraction = Exponent = = 129 x = ( 1) 1 ( ) 2 ( ) = ( 1) = 5.0 Chapter 3 Arithmetic for Computers 41
68 Representable FP Numbers Negative numbers Positive numbers max FLP min min + FLP max ± Sparser Denser Denser Sparser O verflow region Underflow regions O verflow region Midway example Underflow example Typical example O verflow example Chapter 3 Arithmetic for Computers 42
69 Zero Biased exponent=0 Fraction = 0 Hidden bit = 0. Two representations for 0 (single precision) x = ( 1) 0x x S (0 + 0) 2 Bias = ± 0.0 Chapter 3 Arithmetic for Computers 43
70 Denormal Numbers Exponent = hidden bit is 0 x = ( 1) S (0 + Fraction) 2 ( Bias 1) Smaller than normal numbers allow for gradual underflow, with diminishing precision Chapter 3 Arithmetic for Computers 44
71 Denormalized Example Find the decimal equivalent of IEEE 754 number Determine the sign: 0, the number is positive Calculate the exponent exponent of all 0s means the number is denormalized exponent is therefore 126 Convert the significand to decimal remember to add the implicit bit (this is 0. because the number is denormalized) ( ) 2 = ( ) = x Chapter 3 Arithmetic for Computers 45
72 Infinities and NaNs Exponent = , Fraction = ±Infinity Can be used in subsequent calculations, avoiding need for overflow check Exponent = , Fraction NotaNumber (NaN) Indicates illegal or undefined result e.g., 0.0 / 0.0 Can be used in subsequent calculations Chapter 3 Arithmetic for Computers 46
73 NaNs 1. Operations with at least one NaN operand 2. Indeterminate forms divisions 0/0 and ± /± multiplications 0 ± and ± 0 additions + ( ), ( ) + and equivalent subtractions 3. Real operations with complex results square root of a negative number. logarithm of a negative number inverse sine or cosine of a number that is less than 1 or greater than +1. Chapter 3 Arithmetic for Computers 47
74 FloatingPoint Addition Consider a 4digit decimal example Align decimal points Shift number with smaller exponent Add significands = Normalize result & check for over/underflow Round and renormalize if necessary Chapter 3 Arithmetic for Computers 48
75 FloatingPoint Addition Now consider a 4digit binary example ( ) 1. Align binary points Shift number with smaller exponent Add significands = Normalize result & check for over/underflow , with no over/underflow 4. Round and renormalize if necessary (no change) = Chapter 3 Arithmetic for Computers 49
76 Floating Point Addition Example Consider adding: (1.111) (1.011) For simplicity, we assume 4 bits of precision (or 3 bits of fraction)
77 Floating Point Addition Example Consider adding: (1.111) (1.011) For simplicity, we assume 4 bits of precision (or 3 bits of fraction) Exponents are not equal
78 Floating Point Addition Example Consider adding: (1.111) (1.011) For simplicity, we assume 4 bits of precision (or 3 bits of fraction) Exponents are not equal Shift the significand of the lesser exponent right until its exponent matches the larger number
79 Floating Point Addition Example Consider adding: (1.111) (1.011) For simplicity, we assume 4 bits of precision (or 3 bits of fraction) Exponents are not equal Shift the significand of the lesser exponent right until its exponent matches the larger number (1.011) = (0.1011) = ( ) 2 2 1
80 Floating Point Addition Example Consider adding: (1.111) (1.011) For simplicity, we assume 4 bits of precision (or 3 bits of fraction) Exponents are not equal Shift the significand of the lesser exponent right until its exponent matches the larger number (1.011) = (0.1011) = ( ) Difference between the two exponents = 1 ( 3) = 2
81 Floating Point Addition Example Consider adding: (1.111) (1.011) For simplicity, we assume 4 bits of precision (or 3 bits of fraction) Exponents are not equal Shift the significand of the lesser exponent right until its exponent matches the larger number (1.011) = (0.1011) = ( ) Difference between the two exponents = 1 ( 3) = 2 So, shift right by 2 bits
82 Floating Point Addition Example Consider adding: (1.111) (1.011) For simplicity, we assume 4 bits of precision (or 3 bits of fraction) Exponents are not equal Shift the significand of the lesser exponent right until its exponent matches the larger number (1.011) = (0.1011) = ( ) Difference between the two exponents = 1 ( 3) = 2 So, shift right by 2 bits Now, add the significands: Carry
83 Addition Example cont d So, (1.111) (1.011) = ( ) 2 2 1
84 Addition Example cont d So, (1.111) (1.011) = ( ) However, result ( ) is NOT normalized
85 Addition Example cont d So, (1.111) (1.011) = ( ) However, result ( ) is NOT normalized Normalize result: ( ) = ( ) 2 2 0
86 Addition Example cont d So, (1.111) (1.011) = ( ) However, result ( ) is NOT normalized Normalize result: ( ) = ( ) In this example, we have a carry So, shift right by 1 bit and increment the exponent
87 Addition Example cont d So, (1.111) (1.011) = ( ) However, result ( ) is NOT normalized Normalize result: ( ) = ( ) In this example, we have a carry So, shift right by 1 bit and increment the exponent Round the significand to fit in appropriate number of bits We assumed 4 bits of precision or 3 bits of fraction
88 Addition Example cont d So, (1.111) (1.011) = ( ) However, result ( ) is NOT normalized Normalize result: ( ) = ( ) In this example, we have a carry So, shift right by 1 bit and increment the exponent Round the significand to fit in appropriate number of bits We assumed 4 bits of precision or 3 bits of fraction Round to nearest: ( ) 2 (1.001)
89 Addition Example cont d So, (1.111) (1.011) = ( ) However, result ( ) is NOT normalized Normalize result: ( ) = ( ) In this example, we have a carry So, shift right by 1 bit and increment the exponent Round the significand to fit in appropriate number of bits We assumed 4 bits of precision or 3 bits of fraction Round to nearest: ( ) 2 (1.001) 2 Renormalize if rounding generates a carry
90 Addition Example cont d So, (1.111) (1.011) = ( ) However, result ( ) is NOT normalized Normalize result: ( ) = ( ) In this example, we have a carry So, shift right by 1 bit and increment the exponent Round the significand to fit in appropriate number of bits We assumed 4 bits of precision or 3 bits of fraction Round to nearest: ( ) 2 (1.001) 2 Renormalize if rounding generates a carry Detect overflow / underflow If exponent becomes too large (overflow) or too small (underflow) Represent overflow/underflow accordingly
91 Floating Point Subtraction Example Consider: (1.000) (1.000) We assume again: 4 bits of precision (or 3 bits of fraction)
92 Floating Point Subtraction Example Consider: (1.000) (1.000) We assume again: 4 bits of precision (or 3 bits of fraction) Shift right significand of the lesser exponent
93 Floating Point Subtraction Example Consider: (1.000) (1.000) We assume again: 4 bits of precision (or 3 bits of fraction) Shift right significand of the lesser exponent Difference between the two exponents = 2 ( 3) = 5
94 Floating Point Subtraction Example Consider: (1.000) (1.000) We assume again: 4 bits of precision (or 3 bits of fraction) Shift right significand of the lesser exponent Difference between the two exponents = 2 ( 3) = 5 Shift right by 5 bits: (1.000) = ( ) 2 2 2
95 Floating Point Subtraction Example Consider: (1.000) (1.000) We assume again: 4 bits of precision (or 3 bits of fraction) Shift right significand of the lesser exponent Difference between the two exponents = 2 ( 3) = 5 Shift right by 5 bits: (1.000) = ( ) Convert subtraction into addition to 2's complement
96 Floating Point Subtraction Example Consider: (1.000) (1.000) We assume again: 4 bits of precision (or 3 bits of fraction) Shift right significand of the lesser exponent Difference between the two exponents = 2 ( 3) = 5 Shift right by 5 bits: (1.000) = ( ) Convert subtraction into addition to 2's complement Sign
97 Floating Point Subtraction Example Consider: (1.000) (1.000) We assume again: 4 bits of precision (or 3 bits of fraction) Shift right significand of the lesser exponent Difference between the two exponents = 2 ( 3) = 5 Shift right by 5 bits: (1.000) = ( ) Convert subtraction into addition to 2's complement Sign 2 s Complement
98 Floating Point Subtraction Example Consider: (1.000) (1.000) We assume again: 4 bits of precision (or 3 bits of fraction) Shift right significand of the lesser exponent Difference between the two exponents = 2 ( 3) = 5 Shift right by 5 bits: (1.000) = ( ) Convert subtraction into addition to 2's complement Sign 2 s Complement
99 Floating Point Subtraction Example Consider: (1.000) (1.000) We assume again: 4 bits of precision (or 3 bits of fraction) Shift right significand of the lesser exponent Difference between the two exponents = 2 ( 3) = 5 Shift right by 5 bits: (1.000) = ( ) Convert subtraction into addition to 2's complement Sign 2 s Complement Since result is negative, convert result from 2's complement to signmagnitude
100 Floating Point Subtraction Example Consider: (1.000) (1.000) We assume again: 4 bits of precision (or 3 bits of fraction) Shift right significand of the lesser exponent Difference between the two exponents = 2 ( 3) = 5 Shift right by 5 bits: (1.000) = ( ) Convert subtraction into addition to 2's complement Sign 2 s Complement Since result is negative, convert result from 2's complement to signmagnitude 2 s Complement
101 Subtraction Example cont d So, (1.000) (1.000) =
102 Subtraction Example cont d So, (1.000) (1.000) = Normalize result: =
103 Subtraction Example cont d So, (1.000) (1.000) = Normalize result: = Round the significand to fit in appropriate number of bits We assumed 4 bits of precision or 3 bits of fraction
104 Subtraction Example cont d So, (1.000) (1.000) = Normalize result: = Round the significand to fit in appropriate number of bits We assumed 4 bits of precision or 3 bits of fraction Round to nearest: (1.1111) 2 (10.000)
105 Subtraction Example cont d So, (1.000) (1.000) = Normalize result: = Round the significand to fit in appropriate number of bits We assumed 4 bits of precision or 3 bits of fraction Round to nearest: (1.1111) 2 (10.000) 2 Renormalize: rounding generated a carry =
106 Subtraction Example cont d So, (1.000) (1.000) = Normalize result: = Round the significand to fit in appropriate number of bits We assumed 4 bits of precision or 3 bits of fraction Round to nearest: (1.1111) 2 (10.000) 2 Renormalize: rounding generated a carry = Result would have been accurate if more fraction bits are used
107 Floating Point Subtraction Example Consider: (1.000) (1.100) We assume again: 4 bits of precision (or 3 bits of fraction)
108 Floating Point Subtraction Example Consider: (1.000) (1.100) We assume again: 4 bits of precision (or 3 bits of fraction) Shift right significand of the lesser exponent
109 Floating Point Subtraction Example Consider: (1.000) (1.100) We assume again: 4 bits of precision (or 3 bits of fraction) Shift right significand of the lesser exponent Difference between the two exponents = 3 ( 4) = 1
110 Floating Point Subtraction Example Consider: (1.000) (1.100) We assume again: 4 bits of precision (or 3 bits of fraction) Shift right significand of the lesser exponent Difference between the two exponents = 3 ( 4) = 1 Shift right by 1 bits: (1.100) = (0.1100) 2 23
111 Floating Point Subtraction Example Consider: (1.000) (1.100) We assume again: 4 bits of precision (or 3 bits of fraction) Shift right significand of the lesser exponent Difference between the two exponents = 3 ( 4) = 1 Shift right by 1 bits: (1.100) = (0.1100) Convert subtraction into addition to 2's complement
112 Floating Point Subtraction Example Consider: (1.000) (1.100) We assume again: 4 bits of precision (or 3 bits of fraction) Shift right significand of the lesser exponent Difference between the two exponents = 3 ( 4) = 1 Shift right by 1 bits: (1.100) = (0.1100) Convert subtraction into addition to 2's complement Sign
113 Floating Point Subtraction Example Consider: (1.000) (1.100) We assume again: 4 bits of precision (or 3 bits of fraction) Shift right significand of the lesser exponent Difference between the two exponents = 3 ( 4) = 1 Shift right by 1 bits: (1.100) = (0.1100) Convert subtraction into addition to 2's complement Sign 2 s Complement
114 Floating Point Subtraction Example Consider: (1.000) (1.100) We assume again: 4 bits of precision (or 3 bits of fraction) Shift right significand of the lesser exponent Difference between the two exponents = 3 ( 4) = 1 Shift right by 1 bits: (1.100) = (0.1100) Convert subtraction into addition to 2's complement Sign 2 s Complement
115 Subtraction Example cont d So, (1.000) (1.100) =
116 Subtraction Example cont d So, (1.000) (1.100) = Normalize result: =
117 Subtraction Example cont d So, (1.000) (1.100) = Normalize result: = For subtraction, we can have leading zeros
118 Subtraction Example cont d So, (1.000) (1.100) = Normalize result: = For subtraction, we can have leading zeros Round the significand to fit in appropriate number of bits We assumed 4 bits of precision or 3 bits of fraction Answer:
119 FP Adder Hardware Much more complex than integer adder Doing it in one clock cycle would take too long Much longer than integer operations Slower clock would penalize all instructions FP adder usually takes several cycles Can be pipelined Chapter 3 Arithmetic for Computers 57
120 FP Adder Hardware Step 1 Step 2 Step 3 Step 4 Chapter 3 Arithmetic for Computers 58
121 FP Adder Hardware Chapter 3 Arithmetic for Computers 59
122 FloatingPoint Multiplication Consider a 4digit decimal example Add exponents For biased exponents, subtract bias from sum New exponent = = 5 2. Multiply significands = Normalize result & check for over/underflow Round and renormalize if necessary Determine sign of result from signs of operands Chapter 3 Arithmetic for Computers 61
123 FloatingPoint Multiplication Now consider a 4digit binary example ( ) 1. Add exponents Unbiased: = 3 Biased: ( ) + ( ) = = Multiply significands = Normalize result & check for over/underflow (no change) with no over/underflow 4. Round and renormalize if necessary (no change) 5. Determine sign: +ve ve ve = Chapter 3 Arithmetic for Computers 62
124 FP Arithmetic Hardware FP multiplier is of similar complexity to FP adder But uses a multiplier for significands instead of an adder FP arithmetic hardware usually does Addition, subtraction, multiplication, division, reciprocal, squareroot FP integer conversion Operations usually takes several cycles Can be pipelined Chapter 3 Arithmetic for Computers 63
125 FP Instructions in MIPS FP hardware is coprocessor 1 Adjunct processor that extends the ISA Separate FP registers 32 singleprecision: $f0, $f1, $f31 Paired for doubleprecision: $f0/$f1, $f2/$f3, Release 2 of MIPs ISA supports bit FP reg s FP instructions operate only on FP registers Programs generally don t do integer ops on FP data, or vice versa More registers with minimal codesize impact FP load and store instructions lwc1, ldc1, swc1, sdc1 e.g., ldc1 $f8, 32($sp) Chapter 3 Arithmetic for Computers 65
126 FP Instructions in MIPS Singleprecision arithmetic add.s, sub.s, mul.s, div.s add.s $f0, $f1, $f6 #$f0 = $f1 + $f6 Doubleprecision arithmetic add.d, sub.d, mul.d, div.d add.d $f0, $f2, $f6 #$f0:$f1 = $f2:$f3 + $f6:$f7 mul.d $f4, $f4, $f6 Single and doubleprecision comparison c.xx.s, c.xx.d (xx is eq, lt, le, ) Sets or clears FP conditioncode bit (0 to 7) c.lt.s $f3, $f4 #if($f3 < $f4) cond=1; else cond=0 Branch on FP condition code true or false bc1t, bc1f bc1t TargetLabel #if(cond==1) go to TargetLabel Chapter 3 Arithmetic for Computers 66
127 FP Example: F to C C code: float f2c (float fahr) { return ((5.0/9.0)*(fahr )); } fahr in $f12, result in $f0, literals in global memory space Compiled MIPS code: f2c: lwc1 $f16, const5($gp) lwc1 $f18, const9($gp) div.s $f16, $f16, $f18 lwc1 $f18, const32($gp) sub.s $f18, $f12, $f18 mul.s $f0, $f16, $f18 jr $ra Chapter 3 Arithmetic for Computers 67
128 Accurate Arithmetic IEEE Std 754 specifies additional rounding control Extra bits of precision (guard, round, sticky) Choice of rounding modes Allows programmer to finetune numerical behavior of a computation Not all FP units implement all options Most programming languages and FP libraries just use defaults Tradeoff between hardware complexity, performance, and market requirements Chapter 3 Arithmetic for Computers 71
129 Support for Accurate Arithmetic IEEE 754 FP rounding modes Always round up (toward + ) Always round down (toward  ) Truncate (toward zero) Round to nearest even (RTNE)
130 Support for Accurate Arithmetic IEEE 754 FP rounding modes Always round up (toward + ) Always round down (toward  ) Truncate (toward zero) Round to nearest even (RTNE) Rounding (except for truncation) requires the hardware to include extra F bits during calculations Guard bit used to provide one F bit when shifting left to normalize a result (e.g., when normalizing F after division or subtraction) Round bit used to improve rounding accuracy Sticky bit used to support Round to nearest even; is set to a 1 whenever a 1 bit shifts (right) through it (e.g., when aligning F during addition/subtraction) sticky F = 1. xxxxxxxxxxxxxxxxxxxxxxx G R S OR of the discarded bits
131 Rounding Examples Number To + To To Zero Chapter 3 Arithmetic for Computers 73
132 RTNE Examples GRS  Action (after first normalization if required) 0xx  round down = do nothing (x means any bit value, 0 or 1) this is a tie: round up if the bit just before G is 1, else round down = do nothing round up (increment by 1) round up (increment by 1) round up (increment by 1) Sig GRS Increment? Rounded N N N Y Y Y Chapter 3 Arithmetic for Computers 74
133 Guard Bit Guard bit: guards against loss of a significant bit Only one guard bit is needed to maintain accuracy of result Shifted left (if needed) during normalization as last fraction bit
134 Guard Bit Guard bit: guards against loss of a significant bit Only one guard bit is needed to maintain accuracy of result Shifted left (if needed) during normalization as last fraction bit Example on the need of a guard bit:
135 Guard Bit Guard bit: guards against loss of a significant bit Only one guard bit is needed to maintain accuracy of result Shifted left (if needed) during normalization as last fraction bit Example on the need of a guard bit: (subtraction)
136 Guard Bit Guard bit: guards against loss of a significant bit Only one guard bit is needed to maintain accuracy of result Shifted left (if needed) during normalization as last fraction bit Example on the need of a guard bit: (subtraction) (shift right 7 bits)
137 Guard Bit Guard bit: guards against loss of a significant bit Only one guard bit is needed to maintain accuracy of result Shifted left (if needed) during normalization as last fraction bit Example on the need of a guard bit: (subtraction) (shift right 7 bits) (2's complement)
138 Guard Bit Guard bit: guards against loss of a significant bit Only one guard bit is needed to maintain accuracy of result Shifted left (if needed) during normalization as last fraction bit Example on the need of a guard bit: (subtraction) (shift right 7 bits) Guard bit do not discard (2's complement)
139 Guard Bit Guard bit: guards against loss of a significant bit Only one guard bit is needed to maintain accuracy of result Shifted left (if needed) during normalization as last fraction bit Example on the need of a guard bit: (subtraction) (shift right 7 bits) Guard bit do not discard (2's complement) (add significands)
140 Guard Bit Guard bit: guards against loss of a significant bit Only one guard bit is needed to maintain accuracy of result Shifted left (if needed) during normalization as last fraction bit Example on the need of a guard bit: (subtraction) (shift right 7 bits) Guard bit do not discard (2's complement) (add significands) (normalized)
141 Guard Bit Guard bit: guards against loss of a significant bit Only one guard bit is needed to maintain accuracy of result Shifted left (if needed) during normalization as last fraction bit Example on the need of a guard bit: (subtraction) (shift right 7 bits) Guard bit do not discard (2's complement) (add significands) (normalized)
142 Round and Sticky Bits Two extra bits are needed for rounding Rounding performed after normalizing a result significand Round bit: appears after the guard bit Sticky bit: appears after the round bit (OR of all additional bits)
143 Round and Sticky Bits Two extra bits are needed for rounding Rounding performed after normalizing a result significand Round bit: appears after the guard bit Sticky bit: appears after the round bit (OR of all additional bits) Consider the same example of previous slide:
144 Round and Sticky Bits Two extra bits are needed for rounding Rounding performed after normalizing a result significand Round bit: appears after the guard bit Sticky bit: appears after the round bit (OR of all additional bits) Consider the same example of previous slide: (2's complement)
145 Round and Sticky Bits Two extra bits are needed for rounding Rounding performed after normalizing a result significand Round bit: appears after the guard bit Sticky bit: appears after the round bit (OR of all additional bits) Consider the same example of previous slide: (2's complement) (sum)
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