Blog -

Size: px
Start display at page:

Download "Blog -"

Transcription

1 . Instruction Codes Every different processor type has its own design (different registers, buses, microoperations, machine instructions, etc) Modern processor is a very complex device It contains Many registers, Multiple arithmetic units, for both integer and floating point calculations, The ability to pipeline several consecutive instructions to speed execution, etc The Basic Computer has two components, a processor and memory. The memory has 496 words in it, 496 = 2 2, so it takes 2 bits to select a word in memory. Each word is 6 bits long Program -A sequence of (machine) instructions. (Machine) Instruction - A group of bits that tell the computer to perform a specific operation (a sequence of micro-operation). The instructions of a program, along with any needed data are stored in memory. The CPU reads the next instruction from memory. It is placed in an Instruction egister (I). Control circuitry in control unit then translates the instruction into the sequence of microoperations necessary to implement it. Instruction Formats & Addressing modes: A computer instruction is often divided into two parts: An opcode (Operation Code) that specifies the operation for that instruction and an address that specifies the registers and/or locations in memory to use for that operation In the Basic Computer, since the memory contains 496 (= 2 2 ) words, we needs 2 bit to specify which memory address this instruction will use. In the Basic Computer, bit 5 of the instruction specifies the addressing mode (: direct addressing, : indirect addressing). Since the memory words, and hence the instructions, are 6 bits long. The address field of an instruction can represent either Direct address - the address in memory of the data to use (the address of the operand), (or) Indirect address- the address in memory of the address in memory of the data to use. Effective Address (EA) - The address, that can be directly used without modification to access an operand for a computation-type instruction, or as the target address for a branch-type instruction. Eg: Direct Addressing EA is 457, and Indirect Addressing EA is 35.

2 2. Computer egisters Since memory is 4K in size, it requires 2 address bits. Each word of memory contains 6 bits of data. The address register (A) is 2 bits wide, since this system requires that many bits in order to access memory. Similarly, the program counter (PC) is also 2 bits wide. Each data word is 6 bits wide. The Data egister (D) must also be 6 bits wide, since it receives data from and sends data to memory. The accumulator (AC) acts on 6 bits of data. The Instruction egister (I) receives instruction codes from memory which are 6 bits wide. T is a temporary register. Only the CPU can cause it to be accessed. The programmer cannot directly manipulate the contents of T. Most CPU s have one or more temporary registers which it uses to perform instructions. The input and output registers (INP and OUT) are 8 bits wide each. For this CPU, I/O instructions only transfer 8 bits of data at a time. The 3-bit sequence counter (SC) is used to generate the correct timing (T) states. Other -bit registers are the carry out (E), the indirect register (I), the interrupt enable (IEN) and the input and output flags (FGI and FGO). These are shown as below: P C A Memor y 496 x 6 5 I 5 T 7 7 OUT INP 5 5 D A C CP U egisters with bits are showed as below: Label Bits egister Name Description D 6 Data egister Holds memory operand A 2 Address egister Holds address for memory AC 6 Accumulator Processor register I 6 Instruction egister Holds instruction code PC 2 Program Counter Holds address of instruction T 6 Temporary egister Holds temporary data INP 8 Input egister Holds input character OUT 8 Output egister Holds output character Common Bus: The registers in the Basic Computer are connected using a bus. This gives a savings in circuitry over complete connections between registers. It can be showed as below:

3 Fig: Common Bus System This is the internal design of the CPU for the Basic Computer. The CPU is designed around an internal common bus with a common clock. Each register can place its data onto the bus, and has internal tri-state buffers on the outputs. The control unit must make sure that at most one register (or memory unit) places data onto the bus at one time. The memory unit is external to the CPU. It always receives its address from the address register (A) and makes its data available to the CPU bus. It receives data from the CPU bus as well. ead and write signals are supplied by the control unit. The address registers, program counter (PC) and data register (D) each load data onto and receive data from the system bus. Each has a load, increment and clear signal derived from the control unit. These signals are synchronous; each register combines these signals with the system clock to activate the proper function. Since A and PC are only 2- bits each, they use the low order 2 bits of the bus. The accumulator makes its data available on the bus but does not receive data from the bus. Instead, it receives data solely from an ALU, labeled Adder and Logic in the diagram. To load data into AC, place it onto the bus via D and pass it directly through the ALU. The synchronous load, increment and clear signals act as in the previous registers. Note that E, the -bit carry flag, also receives its data from the ALU. The input register, INP, receives data from an external input port, not shown here, and makes its data available only to AC. The output register makes its data available to the output port via hardware not shown here. We will examine these two components in more detail later in this module. The instruction register, I, can only be loaded; it cannot be incremented nor cleared. Its output is used to generate Di and Ti. We will look at that hardware later in this module. T is a temporary register. The CPU uses this register to store intermediate results of operations. It is not accessible by the external programs. It is loaded, incremented and cleared like the other registers. 3. Computer Instructions formats Computer Instructions are classified into three types, based on the Mode bit and Op-code field. Those are; ) Memory eference: As their name implies, memory reference instructions are those that reference memory. Some read data from memory, others write data to memory, and one instruction does both. For these instructions, the most significant bit is the indirect bit. If this bit is, the instruction must use indirect memory addressing. That is, the address given is not the address of the operand. It is the address of a memory location which contains the address of the operand. The next three bits are the OP field, or operation field. These three bits may take on any value except for ; that is reserved for other instructions. The OP field tells the CPU which instruction is to be performed.

4 Finally, the 2 low order bits contain the memory address to be used by this instruction (or in the case of indirection the address of a memory location which contains the address to be used by this instruction). 2) egister eference: egister reference instructions are those which access data and manipulate the contents of registers. They do not access memory. These instructions are executed in one clock cycle. Note that the 2 low-order bits serve a different function depending on the instruction format used. 3) I/O Instructions: This class of instructions accesses I/O devices. The instructions in this class also enable and disable interrupts. Since this computer only allows for a single input device and a single output device, no address information is needed. 4. Instruction Cycle In Basic Computer, a machine instruction is executed in the following cycle:. Fetch an instruction from memory. 2. Decode the instruction. 3. ead the effective address from memory if the instruction has an indirect address. 4. Execute the instruction. After an instruction is executed, the cycle starts again at step, for the next instruction. Note: Every different processor has its own (different) instruction cycle. Fig: Hardware Circuit for Fetch phase. Determine the Instruction: After decoding phase, we are finding which type of instruction is it? This can be shown in diagrammatically as shown below:

5 Fig: Determine the Instruction If we show the clock pulses for finding the Effective Address (EA), then it can be as Memory eference Instruction: The AND instruction performs a bit-wise logical AND. The ADD instruction performs a regular addition. The LDA and STA are regular load and store instructions. The BUN (branch unconditional) is a jump instruction. The BSA is used to call subroutines in the Basic Computer. The ISZ instruction is used for program loops. Note the semicolon in this instruction. It means that the first part is performed, then the second part is performed in the following clock cycle. Later in this module, we will examine exactly how each of these instructions is implemented on the Basic Computer.

6 LDA: Load to AC D 2 T 4 : D M[A] D 2 T 5 : AC D, SC STA: Store AC D 3 T 4 : M[A] AC, SC BUN: Branch Unconditionally D 4 T 4 : PC A, SC BSA: Branch and Save eturn Address M[A] PC, PC A + egister eference Instruction: Each register reference instruction is performed in a single clock cycle. Each instruction manipulates the contents of a register within the CPU, so the relatively time consuming accesses to memory are avoided. There are 2 register reference instructions overall, each of which is encoded by one of the 2 low order bits of the instruction code.

7 I/O Instruction and Interrupt: The input/output instructions, like the register reference instructions, are performed in a single clock cycle. Note that there are no instructions to set FGI or FGO to. These flags are set by external hardware when input data is ready or output data is requested. When the CPU performs the proper input or output instruction (INP or OUT), it resets the flag to allow for future I/O data transfers. Possible I/O Instructions are specified below Open communication only when some data has to be passed. When it getting an interrupt, - The I/O interface, instead of the CPU, monitors the I/O device. - When the interface founds that the I/O device is ready for data transfer, it generates an interrupt request to the CPU - Upon detecting an interrupt, the CPU stops momentarily the task it is doing, branches to the service routine to process the data transfer, and then returns to the task it was performing. The T signals occur in sequence and are never skipped over. The only two options during a T-state are to proceed to the next T-state or to return to T state. The D signals decode the instruction and are used to select the correct execute routine. I is used to select the indirect routine and also to select the correct execute routine for nonmemory reference instructions. is used for interrupt processing flip-flop.

8 - The interrupt cycle is a HW implementation of a branch and save return address operation. - At the beginning of the next instruction cycle, the instruction that is read from memory is in address. - At memory address, the programmer must store a branch instruction that sends the control to an interrupt service routine - The instruction that returns the control to the original program is "indirect BUN ". The fetch and decode phases of the instruction cycle must be modified eplace T, T, T2 with 'T, 'T, 'T2 The interrupt cycle: T: A, T PC T: M[A] T, PC T2: PC PC +, IEN,, SC.

BASIC COMPUTER ORGANIZATION AND DESIGN

BASIC COMPUTER ORGANIZATION AND DESIGN 1 BASIC COMPUTER ORGANIZATION AND DESIGN Instruction Codes Computer Registers Computer Instructions Timing and Control Instruction Cycle Memory Reference Instructions Input-Output and Interrupt Complete

More information

Computer Organization (Autonomous)

Computer Organization (Autonomous) Computer Organization (Autonomous) UNIT II Sections - A & D Prepared by Anil Kumar Prathipati, Asst. Prof., Dept. of CSE. SYLLABUS Basic Computer Organization and Design: Instruction codes Stored Program

More information

csitnepal Unit 3 Basic Computer Organization and Design

csitnepal Unit 3 Basic Computer Organization and Design Unit 3 Basic Computer Organization and Design Introduction We introduce here a basic computer whose operation can be specified by the resister transfer statements. Internal organization of the computer

More information

CHAPTER 5 Basic Organization and Design Outline Instruction Codes Computer Registers Computer Instructions Timing and Control Instruction Cycle

CHAPTER 5 Basic Organization and Design Outline Instruction Codes Computer Registers Computer Instructions Timing and Control Instruction Cycle CS 224: Computer Organization S.KHABET CHAPTER 5 Basic Organization and Design Outline Instruction Codes Computer Registers Computer Instructions Timing and Control Instruction Cycle Memory Reference Instructions

More information

BASIC COMPUTER ORGANIZATION AND DESIGN

BASIC COMPUTER ORGANIZATION AND DESIGN BASIC COMPUTER ORGANIZATION AND DESIGN Instruction Codes Computer Registers Computer Instructions Timing and Control Instruction Cycle Memory Reference Instructions Input-Output and Interrupt Complete

More information

Basic Computer Organization - Designing your first computer. Acknowledgment: Most of the slides are adapted from Prof. Hyunsoo Yoon s slides.

Basic Computer Organization - Designing your first computer. Acknowledgment: Most of the slides are adapted from Prof. Hyunsoo Yoon s slides. Basic Computer Organization - Designing your first computer Acknowledgment: Most of the slides are adapted from Prof. Hyunsoo Yoon s slides. 1 This week- BASIC COMPUTER ORGANIZATION AND DESIGN Instruction

More information

UNIT:2 BASIC COMPUTER ORGANIZATION AND DESIGN

UNIT:2 BASIC COMPUTER ORGANIZATION AND DESIGN 1 UNIT:2 BASIC COMPUTER ORGANIZATION AND DESIGN BASIC COMPUTER ORGANIZATION AND DESIGN 2.1 Instruction Codes 2.2 Computer Registers AC or Accumulator, Data Register or DR, the AR or Address Register, program

More information

Unit II Basic Computer Organization

Unit II Basic Computer Organization 1. Define the term. Internal Organization-The internal organization of a digital system is defined by the sequence of microoperations it performs on data stored in its registers. Program- A program is

More information

COMPUTER ORGANIZATION

COMPUTER ORGANIZATION COMPUTER ORGANIZATION INDEX UNIT-II PPT SLIDES Srl. No. Module as per Session planner Lecture No. PPT Slide No. 1. Register Transfer language 2. Register Transfer Bus and memory transfers 3. Arithmetic

More information

BASIC COMPUTER ORGANIZATION AND DESIGN

BASIC COMPUTER ORGANIZATION AND DESIGN 1 BASIC COMPUTER ORGANIZATION AND DESIGN Instruction Codes Computer Registers Computer Instructions Timing and Control Instruction Cycle Memory Reference Instructions Input-Output and Interrupt Complete

More information

Chapter 5. Computer Architecture Organization and Design. Computer System Architecture Database Lab, SANGJI University

Chapter 5. Computer Architecture Organization and Design. Computer System Architecture Database Lab, SANGJI University Chapter 5. Computer Architecture Organization and Design Computer System Architecture Database Lab, SANGJI University Computer Architecture Organization and Design Instruction Codes Computer Registers

More information

COMPUTER ARCHITECTURE AND ORGANIZATION Register Transfer and Micro-operations 1. Introduction A digital system is an interconnection of digital

COMPUTER ARCHITECTURE AND ORGANIZATION Register Transfer and Micro-operations 1. Introduction A digital system is an interconnection of digital Register Transfer and Micro-operations 1. Introduction A digital system is an interconnection of digital hardware modules that accomplish a specific information-processing task. Digital systems vary in

More information

5-1 Instruction Codes

5-1 Instruction Codes Chapter 5: Lo ai Tawalbeh Basic Computer Organization and Design 5-1 Instruction Codes The Internal organization of a digital system is defined by the sequence of microoperations it performs on data stored

More information

Basic Computer Organization and Design Part 2/3

Basic Computer Organization and Design Part 2/3 Basic Computer Organization and Design Part 2/3 Adapted by Dr. Adel Ammar Computer Organization Basic Computer Instructions Basic Computer Instruction Format Memory-Reference Instructions (OP-code = 000

More information

Computer Architecture and Organization: L06: Instruction Cycle

Computer Architecture and Organization: L06: Instruction Cycle Computer Architecture and Organization: L06: Instruction Cycle By: A. H. Abdul Hafez Abdul.hafez@hku.edu.tr, ah.abdulhafez@gmail.com 1 Outlines 1. Fetch and decode 2. Determine the Type of Instruction

More information

CHAPTER SIX BASIC COMPUTER ORGANIZATION AND DESIGN

CHAPTER SIX BASIC COMPUTER ORGANIZATION AND DESIGN CHAPTER SIX BASIC COMPUTER ORGANIZATION AND DESIGN 6.1. Instruction Codes The organization of a digital computer defined by: 1. The set of registers it contains and their function. 2. The set of instructions

More information

Computer Organization and Design

Computer Organization and Design CSE211 Computer Organization and Design Lecture : 3 Tutorial: 1 Practical: 0 Credit: 4 KIDS Labs 1 Unit 1 : Basics of Digital Electronics Introduction Logic Gates Flip Flops Decoder Encoder Multiplexers

More information

Micro-Operations. execution of a sequence of steps, i.e., cycles

Micro-Operations. execution of a sequence of steps, i.e., cycles Micro-Operations Instruction execution execution of a sequence of steps, i.e., cycles Fetch, Indirect, Execute & Interrupt cycles Cycle - a sequence of micro-operations Micro-operations data transfer between

More information

Chapter 16. Control Unit Operation. Yonsei University

Chapter 16. Control Unit Operation. Yonsei University Chapter 16 Control Unit Operation Contents Micro-Operation Control of the Processor Hardwired Implementation 16-2 Micro-Operations Micro-Operations Micro refers to the fact that each step is very simple

More information

Darshan Institute of Engineering & Technology for Diploma Studies Unit - 1

Darshan Institute of Engineering & Technology for Diploma Studies Unit - 1 Darshan Institute of Engineering & Technology for Diploma Studies Unit - 1 1. Draw and explain 4 bit binary arithmetic or adder circuit diagram. A binary parallel adder is digital function that produces

More information

William Stallings Computer Organization and Architecture

William Stallings Computer Organization and Architecture William Stallings Computer Organization and Architecture Chapter 16 Control Unit Operations Rev. 3.2 (2009-10) by Enrico Nardelli 16-1 Execution of the Instruction Cycle It has many elementary phases,

More information

Programming Level A.R. Hurson Department of Computer Science Missouri University of Science & Technology Rolla, Missouri

Programming Level A.R. Hurson Department of Computer Science Missouri University of Science & Technology Rolla, Missouri Programming Level A.R. Hurson Department of Computer Science Missouri University of Science & Technology Rolla, Missouri 65409 hurson@mst.edu A.R. Hurson 1 Programming Level Computer: A computer with a

More information

Computer architecture Assignment 3

Computer architecture Assignment 3 Computer architecture Assignment 3 1- An instruction at address 14E in the basic computer has I=0, an operation code of the AND instruction, and an address part equal to 109(all numbers are in hexadecimal).

More information

Computer Architecture

Computer Architecture Computer Architecture Lecture 1: Digital logic circuits The digital computer is a digital system that performs various computational tasks. Digital computers use the binary number system, which has two

More information

Digital System Design Using Verilog. - Processing Unit Design

Digital System Design Using Verilog. - Processing Unit Design Digital System Design Using Verilog - Processing Unit Design 1.1 CPU BASICS A typical CPU has three major components: (1) Register set, (2) Arithmetic logic unit (ALU), and (3) Control unit (CU) The register

More information

Class Notes. Dr.C.N.Zhang. Department of Computer Science. University of Regina. Regina, SK, Canada, S4S 0A2

Class Notes. Dr.C.N.Zhang. Department of Computer Science. University of Regina. Regina, SK, Canada, S4S 0A2 Class Notes CS400 Part VI Dr.C.N.Zhang Department of Computer Science University of Regina Regina, SK, Canada, S4S 0A2 C. N. Zhang, CS400 83 VI. CENTRAL PROCESSING UNIT 1 Set 1.1 Addressing Modes and Formats

More information

There are four registers involved in the fetch cycle: MAR, MBR, PC, and IR.

There are four registers involved in the fetch cycle: MAR, MBR, PC, and IR. CS 320 Ch. 20 The Control Unit Instructions are broken down into fetch, indirect, execute, and interrupt cycles. Each of these cycles, in turn, can be broken down into microoperations where a microoperation

More information

Computer Architecture

Computer Architecture http://www.bsccsit.com/ Computer Architecture CSC. 201 Third Semester Prepared By: Arjun Singh Saud Special thanks to Mr. Arjun Singh Saud for providing this valuable note! Chapter 1 Data representation

More information

SCRAM Introduction. Philipp Koehn. 19 February 2018

SCRAM Introduction. Philipp Koehn. 19 February 2018 SCRAM Introduction Philipp Koehn 19 February 2018 This eek 1 Fully work through a computer circuit assembly code Simple but Complete Random Access Machine (SCRAM) every instruction is 8 bit 4 bit for op-code:

More information

Computer Architecture Programming the Basic Computer

Computer Architecture Programming the Basic Computer 4. The Execution of the EXCHANGE Instruction The EXCHANGE routine reads the operand from the effective address and places it in DR. The contents of DR and AC are interchanged in the third microinstruction.

More information

Processing Unit CS206T

Processing Unit CS206T Processing Unit CS206T Microprocessors The density of elements on processor chips continued to rise More and more elements were placed on each chip so that fewer and fewer chips were needed to construct

More information

Basic Processing Unit: Some Fundamental Concepts, Execution of a. Complete Instruction, Multiple Bus Organization, Hard-wired Control,

Basic Processing Unit: Some Fundamental Concepts, Execution of a. Complete Instruction, Multiple Bus Organization, Hard-wired Control, UNIT - 7 Basic Processing Unit: Some Fundamental Concepts, Execution of a Complete Instruction, Multiple Bus Organization, Hard-wired Control, Microprogrammed Control Page 178 UNIT - 7 BASIC PROCESSING

More information

Chapter 3 : Control Unit

Chapter 3 : Control Unit 3.1 Control Memory Chapter 3 Control Unit The function of the control unit in a digital computer is to initiate sequences of microoperations. When the control signals are generated by hardware using conventional

More information

CPU Structure and Function

CPU Structure and Function CPU Structure and Function Chapter 12 Lesson 17 Slide 1/36 Processor Organization CPU must: Fetch instructions Interpret instructions Fetch data Process data Write data Lesson 17 Slide 2/36 CPU With Systems

More information

Module 5 - CPU Design

Module 5 - CPU Design Module 5 - CPU Design Lecture 1 - Introduction to CPU The operation or task that must perform by CPU is: Fetch Instruction: The CPU reads an instruction from memory. Interpret Instruction: The instruction

More information

Advanced Parallel Architecture Lesson 3. Annalisa Massini /2015

Advanced Parallel Architecture Lesson 3. Annalisa Massini /2015 Advanced Parallel Architecture Lesson 3 Annalisa Massini - 2014/2015 Von Neumann Architecture 2 Summary of the traditional computer architecture: Von Neumann architecture http://williamstallings.com/coa/coa7e.html

More information

Blog - https://anilkumarprathipati.wordpress.com/

Blog - https://anilkumarprathipati.wordpress.com/ Control Memory 1. Introduction The function of the control unit in a digital computer is to initiate sequences of microoperations. When the control signals are generated by hardware using conventional

More information

Microprocessor Architecture

Microprocessor Architecture Microprocessor - 8085 Architecture 8085 is pronounced as "eighty-eighty-five" microprocessor. It is an 8-bit microprocessor designed by Intel in 1977 using NMOS technology. It has the following configuration

More information

Midterm Examination # 2 Wednesday, March 18, Duration of examination: 75 minutes

Midterm Examination # 2 Wednesday, March 18, Duration of examination: 75 minutes Page 1 of 8 School of Computer Science 60-265-01 Computer Architecture and Digital Design Winter 2009 Midterm Examination # 2 Wednesday, March 18, 2009 Student Name: First Name Family Name Student ID Number:

More information

William Stallings Computer Organization and Architecture

William Stallings Computer Organization and Architecture William Stallings Computer Organization and Architecture Chapter 11 CPU Structure and Function Rev. 3.2.1 (2005-06) by Enrico Nardelli 11-1 CPU Functions CPU must: Fetch instructions Decode instructions

More information

C.P.U Organization. Memory Unit. Central Processing Unit (C.P.U) Input-Output Processor (IOP) Figure (1) Digital Computer Block Diagram

C.P.U Organization. Memory Unit. Central Processing Unit (C.P.U) Input-Output Processor (IOP) Figure (1) Digital Computer Block Diagram C.P.U Organization 1.1 Introduction A computer system is sometimes subdivided into two functional entities "Hardware" and "Software". The H/W of the computer consists of all the electronic components and

More information

Advanced Parallel Architecture Lesson 3. Annalisa Massini /2015

Advanced Parallel Architecture Lesson 3. Annalisa Massini /2015 Advanced Parallel Architecture Lesson 3 Annalisa Massini - Von Neumann Architecture 2 Two lessons Summary of the traditional computer architecture Von Neumann architecture http://williamstallings.com/coa/coa7e.html

More information

Faculty of Engineering Systems & Biomedical Dept. First Year Cairo University Sheet 6 Computer I

Faculty of Engineering Systems & Biomedical Dept. First Year Cairo University Sheet 6 Computer I aculty of Engineering Systems & Biomedical Dept. irst Year Cairo University Sheet 6 Computer I 1. Choose rue or alse for each of the following statements a) In a direct addressing mode instruction, the

More information

Computer Organization and Architecture

Computer Organization and Architecture Computer Organization and Architecture Dr Binu P Chacko Associate Professor Department of Computer Science Prajyoti Niketan College, Pudukad, THRISSUR Instruction Codes Computer organization is defined

More information

Part A Questions 1. What is an ISP? ISP stands for Instruction Set Processor. This unit is simply called as processor which executes machine instruction and coordinates the activities of other units..

More information

CPU Structure and Function

CPU Structure and Function Computer Architecture Computer Architecture Prof. Dr. Nizamettin AYDIN naydin@yildiz.edu.tr nizamettinaydin@gmail.com http://www.yildiz.edu.tr/~naydin CPU Structure and Function 1 2 CPU Structure Registers

More information

MICROPROGRAMMED CONTROL

MICROPROGRAMMED CONTROL MICROPROGRAMMED CONTROL Hardwired Control Unit: When the control signals are generated by hardware using conventional logic design techniques, the control unit is said to be hardwired. Micro programmed

More information

William Stallings Computer Organization and Architecture. Chapter 11 CPU Structure and Function

William Stallings Computer Organization and Architecture. Chapter 11 CPU Structure and Function William Stallings Computer Organization and Architecture Chapter 11 CPU Structure and Function CPU Structure CPU must: Fetch instructions Interpret instructions Fetch data Process data Write data Registers

More information

Introduction to Computers - Chapter 4

Introduction to Computers - Chapter 4 Introduction to Computers - Chapter 4 Since the invention of the transistor and the first digital computer of the 1940s, computers have been increasing in complexity and performance; however, their overall

More information

Assembly Language Programming of 8085

Assembly Language Programming of 8085 Assembly Language Programming of 8085 Topics 1. Introduction 2. Programming model of 8085 3. Instruction set of 8085 4. Example Programs 5. Addressing modes of 8085 6. Instruction & Data Formats of 8085

More information

1 MALP ( ) Unit-1. (1) Draw and explain the internal architecture of 8085.

1 MALP ( ) Unit-1. (1) Draw and explain the internal architecture of 8085. (1) Draw and explain the internal architecture of 8085. The architecture of 8085 Microprocessor is shown in figure given below. The internal architecture of 8085 includes following section ALU-Arithmetic

More information

CPU Structure and Function. Chapter 12, William Stallings Computer Organization and Architecture 7 th Edition

CPU Structure and Function. Chapter 12, William Stallings Computer Organization and Architecture 7 th Edition CPU Structure and Function Chapter 12, William Stallings Computer Organization and Architecture 7 th Edition CPU must: CPU Function Fetch instructions Interpret/decode instructions Fetch data Process data

More information

The von Neumann Architecture. IT 3123 Hardware and Software Concepts. The Instruction Cycle. Registers. LMC Executes a Store.

The von Neumann Architecture. IT 3123 Hardware and Software Concepts. The Instruction Cycle. Registers. LMC Executes a Store. IT 3123 Hardware and Software Concepts February 11 and Memory II Copyright 2005 by Bob Brown The von Neumann Architecture 00 01 02 03 PC IR Control Unit Command Memory ALU 96 97 98 99 Notice: This session

More information

The functional block diagram of 8085A is shown in fig.4.1.

The functional block diagram of 8085A is shown in fig.4.1. Lecture-13 Internal Architecture of Intel 05A The functional block diagram of 05A is shown in fig.4.1. INTA INTR RST7.5 RST5.5 RST6.5 TRAP SOD SID INTERRUPT SERIAL I/O (Internal Bus) FR(S) IR() B() C()

More information

UNIT-II. Part-2: CENTRAL PROCESSING UNIT

UNIT-II. Part-2: CENTRAL PROCESSING UNIT Page1 UNIT-II Part-2: CENTRAL PROCESSING UNIT Stack Organization Instruction Formats Addressing Modes Data Transfer And Manipulation Program Control Reduced Instruction Set Computer (RISC) Introduction:

More information

EE 3170 Microcontroller Applications

EE 3170 Microcontroller Applications EE 3170 Microcontroller Applications Lecture 4 : Processors, Computers, and Controllers - 1.2 (reading assignment), 1.3-1.5 Based on slides for ECE3170 by Profs. Kieckhafer, Davis, Tan, and Cischke Outline

More information

Lecture1: introduction. Outline: History overview Central processing unite Register set Special purpose address registers Datapath Control unit

Lecture1: introduction. Outline: History overview Central processing unite Register set Special purpose address registers Datapath Control unit Lecture1: introduction Outline: History overview Central processing unite Register set Special purpose address registers Datapath Control unit 1 1. History overview Computer systems have conventionally

More information

CPU ARCHITECTURE. QUESTION 1 Explain how the width of the data bus and system clock speed affect the performance of a computer system.

CPU ARCHITECTURE. QUESTION 1 Explain how the width of the data bus and system clock speed affect the performance of a computer system. CPU ARCHITECTURE QUESTION 1 Explain how the width of the data bus and system clock speed affect the performance of a computer system. ANSWER 1 Data Bus Width the width of the data bus determines the number

More information

QUESTION BANK. EE 6502 / Microprocessor and Microcontroller. Unit I Processor. PART-A (2-Marks)

QUESTION BANK. EE 6502 / Microprocessor and Microcontroller. Unit I Processor. PART-A (2-Marks) QUESTION BANK EE 6502 / Microprocessor and Microcontroller Unit I- 8085 Processor PART-A (2-Marks) YEAR/SEM : III/V 1. What is meant by Level triggered interrupt? Which are the interrupts in 8085 level

More information

Chapter 4. MARIE: An Introduction to a Simple Computer. Chapter 4 Objectives. 4.1 Introduction. 4.2 CPU Basics

Chapter 4. MARIE: An Introduction to a Simple Computer. Chapter 4 Objectives. 4.1 Introduction. 4.2 CPU Basics Chapter 4 Objectives Learn the components common to every modern computer system. Chapter 4 MARIE: An Introduction to a Simple Computer Be able to explain how each component contributes to program execution.

More information

STRUCTURE OF DESKTOP COMPUTERS

STRUCTURE OF DESKTOP COMPUTERS Page no: 1 UNIT 1 STRUCTURE OF DESKTOP COMPUTERS The desktop computers are the computers which are usually found on a home or office desk. They consist of processing unit, storage unit, visual display

More information

1. INTRODUCTION TO MICROPROCESSOR AND MICROCOMPUTER ARCHITECTURE:

1. INTRODUCTION TO MICROPROCESSOR AND MICROCOMPUTER ARCHITECTURE: 1. INTRODUCTION TO MICROPROCESSOR AND MICROCOMPUTER ARCHITECTURE: A microprocessor is a programmable electronics chip that has computing and decision making capabilities similar to central processing unit

More information

Computer Architecture 2/26/01 Lecture #

Computer Architecture 2/26/01 Lecture # Computer Architecture 2/26/01 Lecture #9 16.070 On a previous lecture, we discussed the software development process and in particular, the development of a software architecture Recall the output of the

More information

1. Internal Architecture of 8085 Microprocessor

1. Internal Architecture of 8085 Microprocessor Practical 1 Date : AIM : Introduction Of Microprocessor 8085. 1. Internal Architecture of 8085 Microprocessor Control Unit Generates signals within µp to carry out the instruction, which has been decoded.

More information

Architecture & Instruction set of 8085 Microprocessor and 8051 Micro Controller

Architecture & Instruction set of 8085 Microprocessor and 8051 Micro Controller of 8085 microprocessor 8085 is pronounced as "eighty-eighty-five" microprocessor. It is an 8-bit microprocessor designed by Intel in 1977 using NMOS technology. It has the following configuration 8-bit

More information

General purpose registers These are memory units within the CPU designed to hold temporary data.

General purpose registers These are memory units within the CPU designed to hold temporary data. Von Neumann Architecture Single processor is used Each instruction in a program follows a linear sequence of fetch decode execute cycle Program and data are held in same main memory Stored program Concept

More information

Fig: Computer memory with Program, data, and Stack. Blog - NEC (Autonomous) 1

Fig: Computer memory with Program, data, and Stack. Blog -   NEC (Autonomous) 1 Central Processing Unit 1. Stack Organization A useful feature that is included in the CPU of most computers is a stack or last in, first out (LIFO) list. A stack is a storage device that stores information

More information

MICROPROCESSOR B.Tech. th ECE

MICROPROCESSOR B.Tech. th ECE MICROPROCESSOR B.Tech. th ECE Submitted by: Er. Amita Sharma Dept. of ECE 11/24/2014 2 Microprocessor Architecture The microprocessor can be programmed to perform functions on given data by writing specific

More information

1. Internal Architecture of 8085 Microprocessor

1. Internal Architecture of 8085 Microprocessor 1. Internal Architecture of 8085 Microprocessor Control Unit Generates signals within up to carry out the instruction, which has been decoded. In reality causes certain connections between blocks of the

More information

CHAPTER 8: Central Processing Unit (CPU)

CHAPTER 8: Central Processing Unit (CPU) CS 224: Computer Organization S.KHABET CHAPTER 8: Central Processing Unit (CPU) Outline Introduction General Register Organization Stack Organization Instruction Formats Addressing Modes 1 Major Components

More information

Microcontroller Systems

Microcontroller Systems µcontroller systems 1 / 43 Microcontroller Systems Engineering Science 2nd year A2 Lectures Prof David Murray david.murray@eng.ox.ac.uk www.robots.ox.ac.uk/ dwm/courses/2co Michaelmas 2014 µcontroller

More information

COA. Prepared By: Dhaval R. Patel Page 1. Q.1 Define MBR.

COA. Prepared By: Dhaval R. Patel Page 1. Q.1 Define MBR. Q.1 Define MBR. MBR( Memory buffer register) A Memory Buffer Register (MBR) is the register in a computers processor that stores the data being transferred to and from the devices It allowing the processor

More information

UNIT- 5. Chapter 12 Processor Structure and Function

UNIT- 5. Chapter 12 Processor Structure and Function UNIT- 5 Chapter 12 Processor Structure and Function CPU Structure CPU must: Fetch instructions Interpret instructions Fetch data Process data Write data CPU With Systems Bus CPU Internal Structure Registers

More information

Computer Organization II CMSC 3833 Lecture 33

Computer Organization II CMSC 3833 Lecture 33 Term MARIE Definition Machine Architecture that is Really Intuitive and Easy 4.8.1 The Architecture Figure s Architecture Characteristics: Binary, two s complement Stored program, fixed word length Word

More information

Computer Organisation CS303

Computer Organisation CS303 Computer Organisation CS303 Module Period Assignments 1 Day 1 to Day 6 1. Write a program to evaluate the arithmetic statement: X=(A-B + C * (D * E-F))/G + H*K a. Using a general register computer with

More information

PART A (22 Marks) 2. a) Briefly write about r's complement and (r-1)'s complement. [8] b) Explain any two ways of adding decimal numbers.

PART A (22 Marks) 2. a) Briefly write about r's complement and (r-1)'s complement. [8] b) Explain any two ways of adding decimal numbers. Set No. 1 IV B.Tech I Semester Supplementary Examinations, March - 2017 COMPUTER ARCHITECTURE & ORGANIZATION (Common to Electronics & Communication Engineering and Electronics & Time: 3 hours Max. Marks:

More information

The Itanium Bit Microprocessor Report

The Itanium Bit Microprocessor Report The Itanium - 1986 8 Bit Microprocessor Report By PRIYANK JAIN (02010123) Group # 11 Under guidance of Dr. J. K. Deka & Dr. S. B. Nair Department of Computer Science & Engineering Indian Institute of Technology,

More information

Introduction to Microprocessor

Introduction to Microprocessor Introduction to Microprocessor The microprocessor is a general purpose programmable logic device. It is the brain of the computer and it performs all the computational tasks, calculations data processing

More information

Microcomputer Architecture and Programming

Microcomputer Architecture and Programming IUST-EE (Chapter 1) Microcomputer Architecture and Programming 1 Outline Basic Blocks of Microcomputer Typical Microcomputer Architecture The Single-Chip Microprocessor Microprocessor vs. Microcontroller

More information

2 MARKS Q&A 1 KNREDDY UNIT-I

2 MARKS Q&A 1 KNREDDY UNIT-I 2 MARKS Q&A 1 KNREDDY UNIT-I 1. What is bus; list the different types of buses with its function. A group of lines that serves as a connecting path for several devices is called a bus; TYPES: ADDRESS BUS,

More information

Roll No TCS 402/TIT 402

Roll No TCS 402/TIT 402 Roll No TCS 402/TIT 402 Mid Term Examination March 2016 B.Tech (IV Semester) Computer Organization Time: Two (2) Hrs. Maximum Marks: 60 NOTE: (i) (ii) (iii) (iv) This question paper contains three questions

More information

Chapter 2 Logic Gates and Introduction to Computer Architecture

Chapter 2 Logic Gates and Introduction to Computer Architecture Chapter 2 Logic Gates and Introduction to Computer Architecture 2.1 Introduction The basic components of an Integrated Circuit (IC) is logic gates which made of transistors, in digital system there are

More information

Control unit. Input/output devices provide a means for us to make use of a computer system. Computer System. Computer.

Control unit. Input/output devices provide a means for us to make use of a computer system. Computer System. Computer. Lecture 6: I/O and Control I/O operations Control unit Microprogramming Zebo Peng, IDA, LiTH 1 Input/Output Devices Input/output devices provide a means for us to make use of a computer system. Computer

More information

Control Unit: The control unit provides the necessary timing and control Microprocessor resembles a CPU exactly.

Control Unit: The control unit provides the necessary timing and control Microprocessor resembles a CPU exactly. Unit I 8085 and 8086 PROCESSOR Introduction to microprocessor A microprocessor is a clock-driven semiconductor device consisting of electronic logic circuits manufactured by using either a large-scale

More information

Introduction to CPU Design

Introduction to CPU Design ١ Introduction to CPU Design Computer Organization & Assembly Language Programming Dr Adnan Gutub aagutub at uqu.edu.sa [Adapted from slides of Dr. Kip Irvine: Assembly Language for Intel-Based Computers]

More information

Chapter 4 The Von Neumann Model

Chapter 4 The Von Neumann Model Chapter 4 The Von Neumann Model The Stored Program Computer 1943: ENIAC Presper Eckert and John Mauchly -- first general electronic computer. (or was it John V. Atananasoff in 1939?) Hard-wired program

More information

CHAPTER 5 : Introduction to Intel 8085 Microprocessor Hardware BENG 2223 MICROPROCESSOR TECHNOLOGY

CHAPTER 5 : Introduction to Intel 8085 Microprocessor Hardware BENG 2223 MICROPROCESSOR TECHNOLOGY CHAPTER 5 : Introduction to Intel 8085 Hardware BENG 2223 MICROPROCESSOR TECHNOLOGY The 8085A(commonly known as the 8085) : Was first introduced in March 1976 is an 8-bit microprocessor with 16-bit address

More information

Architecture of 8085 microprocessor

Architecture of 8085 microprocessor Architecture of 8085 microprocessor 8085 consists of various units and each unit performs its own functions. The various units of a microprocessor are listed below Accumulator Arithmetic and logic Unit

More information

Register Transfer and Micro-operations

Register Transfer and Micro-operations Register Transfer Language Register Transfer Bus Memory Transfer Micro-operations Some Application of Logic Micro Operations Register Transfer and Micro-operations Learning Objectives After reading this

More information

CISC Processor Design

CISC Processor Design CISC Processor Design Virendra Singh Indian Institute of Science Bangalore virendra@computer.org Lecture 3 SE-273: Processor Design Processor Architecture Processor Architecture CISC RISC Jan 21, 2008

More information

Chapter 4. The Processor

Chapter 4. The Processor Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS implementations A simplified

More information

M. Sc (CS) (II Semester) Examination, Subject: Computer System Architecture Paper Code: M.Sc-CS-203. Time: Three Hours] [Maximum Marks: 60

M. Sc (CS) (II Semester) Examination, Subject: Computer System Architecture Paper Code: M.Sc-CS-203. Time: Three Hours] [Maximum Marks: 60 M. Sc (CS) (II Semester) Examination, 2012-13 Subject: Computer System Architecture Paper Code: M.Sc-CS-203 Time: Three Hours] [Maximum Marks: 60 Note: Question Number 1 is compulsory. Answer any four

More information

COMPUTER ORGANIZATION AND ARCHITECTURE

COMPUTER ORGANIZATION AND ARCHITECTURE Page 1 1. Which register store the address of next instruction to be executed? A) PC B) AC C) SP D) NONE 2. How many bits are required to address the 128 words of memory? A) 7 B) 8 C) 9 D) NONE 3. is the

More information

Chapter 4. MARIE: An Introduction to a Simple Computer

Chapter 4. MARIE: An Introduction to a Simple Computer Chapter 4 MARIE: An Introduction to a Simple Computer Chapter 4 Objectives Learn the components common to every modern computer system. Be able to explain how each component contributes to program execution.

More information

MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI UNIT I THE 8085 & 8086 MICROPROCESSORS. PART A (2 Marks)

MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI UNIT I THE 8085 & 8086 MICROPROCESSORS. PART A (2 Marks) MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI-621213. UNIT I THE 8085 & 8086 MICROPROCESSORS PART A (2 Marks) 1. Give the significance of SIM and RIM instruction available in 8085. [NOV/DEC 2006] Instruction

More information

INTELLIGENCE PLUS CHARACTER - THAT IS THE GOAL OF TRUE EDUCATION UNIT-I

INTELLIGENCE PLUS CHARACTER - THAT IS THE GOAL OF TRUE EDUCATION UNIT-I UNIT-I 1. List and explain the functional units of a computer with a neat diagram 2. Explain the computer levels of programming languages 3. a) Explain about instruction formats b) Evaluate the arithmetic

More information

Chapter 1: Basics of Microprocessor [08 M]

Chapter 1: Basics of Microprocessor [08 M] Microprocessor: Chapter 1: Basics of Microprocessor [08 M] It is a semiconductor device consisting of electronic logic circuits manufactured by using either a Large scale (LSI) or Very Large Scale (VLSI)

More information

Microprocessors/Microcontrollers

Microprocessors/Microcontrollers Microprocessors/Microcontrollers A central processing unit (CPU) fabricated on one or more chips, containing the basic arithmetic, logic, and control elements of a computer that are required for processing

More information

Micro-programmed Control Ch 15

Micro-programmed Control Ch 15 Micro-programmed Control Ch 15 Micro-instructions Micro-programmed Control Unit Sequencing Execution Characteristics 1 Hardwired Control (4) Complex Fast Difficult to design Difficult to modify Lots of

More information

Problem Set 1 Solutions

Problem Set 1 Solutions CSE 260 Digital Computers: Organization and Logical Design Jon Turner Problem Set 1 Solutions 1. Give a brief definition of each of the following parts of a computer system: CPU, main memory, floating

More information