Introduc)on to GPU Programming

Size: px

Start display at page:

Download "Introduc)on to GPU Programming"

Loreen Robertson
5 years ago
Views:

1 Introduc)on to GPU Programming Mubashir Adnan Qureshi h3p:// h3p://developer.download.nvidia.com/cuda/training/nvidia_gpu_compu)ng_webinars_cuda_memory_op)miza)on.pdf

2 Tutorial Goals NVIDIA GPU architecture NVIDIA GPU application development flow Write and run simple NVIDIA GPU kernels in CUDA Be aware of performance limiting factors and understand performance tuning strategies 2

3 Introduction Why use Graphics Processing Units (GPUs) for general-purpose computing Modern GPU architecture NVIDIA GPU programming overview CUDA C OpenCL 3

4 GPU vs. CPU Silicon Use 4 Graph is courtesy of NVIDIA

5 5 Figure is courtesy of NVIDIA NVIDIA GPU Architecture N mul)processors called SMs Each has M cores called SPs SIMD Same instruc)on executed on SPs Device shared across all SMs

6 NVIDIA GeForce9400M G GPU TPC Geometry controller SM I cache MT issue C cache SFU SFU Shared SMC SM I cache MT issue C cache SFU SFU Shared Texture units Texture L1 128-bit interconnect L2 ROP ROP L2 16 streaming processors arranged as 2 streaming multiprocessors At 0.8 GHz this provides 54 GFLOPS in singleprecision (SP) 128-bit interface to offchip GDDR3 21 GB/s bandwidth DRAM DRAM 6

7 NVIDIA Tesla C1060 GPU SM I cache MT issue C cache SFU SFU Shared L2 ROP DRAM TPC 1 Geometry controller SMC SM I cache MT issue C cache SFU SFU Shared Texture units Texture L1 DRAM SM I cache MT issue C cache SFU SFU Shared SM I cache MT issue C cache SFU SFU Shared 512-bit interconnect DRAM DRAM DRAM DRAM TPC 10 Geometry controller SMC SM I cache MT issue C cache SFU SFU Shared Texture units Texture L1 DRAM SM I cache MT issue C cache SFU SFU Shared ROP L2 DRAM 240 streaming processors arranged as 30 streaming mul)processors At 1.3 GHz this provides 1 TFLOPS SP 86.4 GFLOPS DP 512-bit interface to off-chip GDDR3 102 GB/s bandwidth 7

8 12 Graph is courtesy of NVIDIA NVIDIA Tesla S1070 Computing Server 4 T10 GPUs 4 GB GDDR3 SDRAM 4 GB GDDR3 SDRAM Power supply Tesla GPU Tesla GPU Thermal management PCI x16 NVIDIA SWITCH NVIDIA SWITCH PCI x16 System monitoring Tesla GPU 4 GB GDDR3 SDRAM Tesla GPU 4 GB GDDR3 SDRAM

9 GPU Use/Programming GPU libraries NVIDIA s CUDA BLAS and FFT libraries Many 3 rd party libraries Low abstraction lightweight GPU programming toolkits CUDA C OpenCL 9

10 nvcc Any source file containing CUDA C language extensions must be compiled with nvcc nvcc is a compiler driver that invokes many other tools to accomplish the job Basic nvcc usage nvcc <filename>.cu [-o <executable>] Builds release mode nvcc -deviceemu <filename>.cu Builds device emula)on mode (all code runs on CPU) nvprof <executable> Profiles the code 10

11 Anatomy of a GPU Applica)on Host side Device side 30

12 Reference CPU Version void vecadd(int N, float* A, float* B, float* C) } { for (int i = 0; i < N; i++) C[i] = A[i] + B[i]; Computational kernel int main(int argc, char **argv) { int N = 16384; // default vector size float *A = (float*)malloc(n * sizeof(float)); float *B = (float*)malloc(n * sizeof(float)); float *C = (float*)malloc(n * sizeof(float)); vecadd(n, A, B, C); // call compute kernel Memory allocation Kernel invocation free(a); free(b); free(c); Memory de-allocation } 12

13 Adding GPU support Host CPU GPU card GPU Host Memory A B Device Memory ga gb C gc 13

14 Memory Spaces CPU and GPU have separate spaces Data is moved across PCIe bus Use func[ons to allocate/set/copy on GPU Host (CPU) manages device (GPU) cudamalloc(void** pointer, size_t nbytes) cudafree(void* pointer) cudamemcpy(void* dst, void* src, size_t nbytes, enum cudamemcpykind direc[on); returns after the copy is complete blocks CPU thread un[l all bytes have been copied does not start copying un[l previous CUDA calls complete enum cudamemcpykind cudamemcpyhosttodevice cudamemcpydevicetohost cudamemcpydevicetodevice 14

15 Adding GPU support int main(int argc, char **argv) { int N = 16384; // default vector size float *A = (float*)malloc(n * sizeof(float)); float *B = (float*)malloc(n * sizeof(float)); float *C = (float*)malloc(n * sizeof(float)); float *devptra, *devptrb, *devptrc; cudamalloc((void**)&devptra, N * sizeof(float)); cudamalloc((void**)&devptrb, N * sizeof(float)); cudamalloc((void**)&devptrc, N * sizeof(float)); Memory allocation on the GPU card Copy data from the CPU (host) to the GPU (device) cudamemcpy(devptra, A, N * sizeof(float), cudamemcpyhosttodevice); cudamemcpy(devptrb, B, N * sizeof(float), cudamemcpyhosttodevice); 15

16 Adding GPU support vecadd<<<n/512, 512>>>(devPtrA, devptrb, devptrc); Kernel invocation cudamemcpy(c, devptrc, N * sizeof(float), cudamemcpydevicetohost); cudafree(devptra); cudafree(devptrb); cudafree(devptrc); Copy results from device to the host } free(a); free(b); free(c); Device de-allocation 16

17 GPU Kernel CPU version void vecadd(int N, float* A, float* B, float* C) { for (int i = 0; i < N; i++) C[i] = A[i] + B[i]; } GPU version global void vecadd(float* A, float* B, float* C) { int i = blockidx.x * blockdim.x + threadidx.x; C[i] = A[i] + B[i]; } 17

CUDA Programming Model A CUDA kernel is executed by threadid an array of

uses to compute addresses and make control decisions Threads are arranged

of shared Grid Thread Block 0 Shared Thread Block 1 Shared float x =

18 CUDA Programming Model A CUDA kernel is executed by threadid an array of threads All threads run the same code (SIMD) Each thread has an ID that it uses to compute addresses and make control decisions Threads are arranged as a grid of thread blocks Threads within a block have access to a segment of shared Grid Thread Block 0 Shared Thread Block 1 Shared float x = input[threadid]; float y = func(x); output[threadid] = y; Thread Block N-1 Shared 18

19 Kernel Invoca)on Syntax grid & thread block dimensionality vecadd<<<32, 512>>>(devPtrA, devptrb, devptrc); Grid Thread Block 0 Thread Block 1 Thread Block N-1 Shared Shared Shared int i = blockidx.x * blockdim.x + threadidx.x; block ID within a grid number of threads per block thread ID within a thread block 19

20 Mapping Threads to the Hardware Blocks of threads are transparently assigned to SMs A block of threads executes on one SM & does not migrate Several blocks can reside concurrently on one SM Blocks must be independent Any possible interleaving of blocks should be valid Blocks may coordinate but not synchronize Thread blocks can run in any order Device Kernel grid Block 0 Block 1 Device Block 2 Block 3 Block 0 Block 1 Block 2 Block 3 Block 4 Block 5 Block 6 Block 7 time Block 0 Block 1 Block 2 Block 3 Block 4 Block 5 Block 6 Block 7 Block 4 Block 5 Block 6 Block 7 Each block can execute in any order relative to other blocks. 20 Slide is courtesy of NVIDIA

21 GPU Memory Hierarchy Global (device) Accessible by all threads as well as host (CPU) Data life)me is from alloca)on to dealloca)on Device 0 Host cudamemcpy() Device 1 21

22 GPU Memory Hierarchy Global (device) Kernel 0 Thread Block 0 Thread Block 1 Thread Block N-1 Kernel 1 Per-device Global Memory Thread Block 0 Thread Block 1 Thread Block N-1 22

GPU Memory Hierarchy Local storage Each thread has

compiler) Data life)me = thread life)me Shared

by threads within that block Data life)me = block

23 GPU Memory Hierarchy Local storage Each thread has own local storage Mostly registers (managed by the compiler) Data life)me = thread life)me Shared Each thread block has own shared Accessible only by threads within that block Data life)me = block life)me Per-thread local Thread Block Per-block shared 23

GPU Memory Hierarchy Host CPU chipset DRAM DRAM local global constant texture Device GPU Mul)processor Mul)processor Mul)processor registers shared constant and texture caches Memory Loca[on Cached

24 GPU Memory Hierarchy Host CPU chipset DRAM DRAM local global constant texture Device GPU Mul)processor Mul)processor Mul)processor registers shared constant and texture caches Memory Loca[on Cached Access Scope Life[me Register On-chip N/A R/W One thread Thread Local Off-chip No R/W One thread Thread Shared On-chip N/A R/W All threads in a block Block Global Off-chip No R/W All threads + host Applica[on Constant Off-chip Yes R All threads + host Applica[on Texture Off-chip Yes R All threads + host Applica[on 24

25 GPU Kernel CPU version void vecadd(int N, float* A, float* B, float* C) { for (int i = 0; i < N; i++) C[i] = A[i] + B[i]; } GPU version global void vecadd(float* A, float* B, float* C) { int i = blockidx.x * blockdim.x + threadidx.x; C[i] = A[i] + B[i]; } 25

26 Op)mizing Algorithms for GPUs Maximize independent parallelism Maximize arithme)c intensity (math/bandwidth) Some)mes it s be3er to recompute than to cache GPU GPU spends its transistors on ALUs, not Do more computa)on on the GPU to avoid costly data transfers Even low parallelism computa)ons can some)mes be faster than transferring back and forth to host

27 Op)mize Memory Access Coalesced vs. Non-coalesced = order of magnitude Global/Local device Con)guous threads accessing con)guous Shared Memory Hundreds of )mes faster than global Threads can cooperate via shared Use it to avoid non-coalesced access

Introduction to GPU Programming

Introduction to GPU Programming Volodymyr (Vlad) Kindratenko Innovative Systems Laboratory @ NCSA Institute for Advanced Computing Applications and Technologies (IACAT) Tutorial Goals Become familiar with