Exam in Computer Engineering

Size: px
Start display at page:

Download "Exam in Computer Engineering"

Transcription

1 Exam in Computer Engineering Kurskod D0013E/SMD137/SMD082/SMD066 Tentamensdatum Skrivtid Maximalt resultat 50 poäng Godkänt resultat 25 poäng Jourhavande lärare Andrey Kruglyak Tel Tillåtna hjälpmedel, allowed utilities Pennor och sudd, pens and erasers. Lycka till!

2 1 Arithemtics 10p. A. 2p) Translate the binary floating-point number to decimal scientific notation (normalized form), given S = 0, E =128, F = 011. Excess 127; actual exponent is e = E 127, N = (-1) S * (1.F [bit-string])*2 e B. 3p) Perform the floating operation R = A + B according to the IEEE spec for single precision numbers: A = (S = 0, E =127, F = 101), B = (S = 1, E =128, F = 11) For full points, explain your calculations step by step. C. 5p) As an exercise implement (code) an operation that multiplies r1 (assume unsigned integer) by 24 using a minimal number of native MIPS instructions (shifts, adds, subs, etc...). The result should be stored in r2. You may use t0, t1 as scrap registers. (Hint, using adds only will give you merely 1 point... you can do much better) S E F

3 2 MIPS-nopipe 10p $t3 has the initial value of 1. 0X !! addiu!! $t1, $zero, 0x1002 0X loop:!addiu!! $t1, $t1, 1 0x !! lb!! $t2, 0($t1) 0x C!! sb!! $t3, -1($t1) 0x !! addu!! $t3, $t3, $t2 0x !! bnez! $t3, loop 0x ! loop2: b loop2 0x C A. 3p. Mark in the MIPS-Nopipe model the state for each MUX with an arrow indicating the signal propagationm when lb $t2, 0($t1) is executed for the first time in the combined IM/ DE/EX/DM stage. Mark the type of extension carried out in the sign/zero extend box. B. 2p. For D, E,F, G and H (the inputs are numbered started from top), mark ( lb $t2, 0 ($t1) is in the combined IM,DE,EX,DM stage, the first time). C. 5p. Mark in the Memory After, the contents after running the program (you need only to indicate the actual memory updates.) Memory: Before Memory after: 0x x x x...!! 0x x0100FFFF 0x x...! 0x xFFFFFFFF 0x x...! 0x C 0x x C 0x...! E H G F D

4 3 MIPS-pipe 10p $t3 has the initial value of 1. Initial memory contents is same as for assignment 2 (before execution). 0X !! addiu!! $t1, $zero, 0x1002 0X loop:!addiu!! $t1, $t1, 1 0x !! lb!! $t2, 0($t1) 0x C!! sb!! $t3, -1($t1) 0x !! addu!! $t3, $t3, $t2 0x !! bnez! $t3, loop 0x ! loop2: b loop2 0x C A. 2p. Add nop instruction(s) such that the program will behave as in assignment 2. You should only input nop s where necessary. B. 4p. Mark in the MIPS-Pipe model the output-value for synchronizers (a..j), when the MIPS instruction sb $t3, -1($t1) is executed for the first time in the DE stage. Use the value X for don t care if the value is not of importance to the corresponding instruction. opcode(x) (e.g. opcode(bnez $t3, loop) ) can be used for the binary representation of the bnez $t3, loop instruction. regnr(r) (e.g. regnr($t1) ) can be used to represent the address of register $t1 in the register file. C. 4p. Same as B but one clock cycle later (addu $t3, $t3, $t2) is executed for the first time in the DE stage. e f g k l n a b h c d i j m o

5 4 TLB and Cache 10p. Give the answers to [A]..[T] below, 0.5p for each correct answer. Virtual memory is implemented using a TLB. Assume the virtual address is 32 bits and we have 1 GByte (G = 1024*1024*1024) RAM (physical memory) and a fixed page size of 4 kbyte (k = 1024). We have [A] bits used for page offset, [B] bits used for virtual page number and [C] bits for physical page number. Assume a fully associative TLB with 8 lines. For parallel tag comparison we need [D] comparators, each [E] bits wide. The total tag memory requirement is [F] bits (this is the total number of tag-bits in the TLB). Memory access can be improved by a cache. Assume 1 GByte RAM, the address buss is [G] bits and the memory is byte addressed (i.e. address LSB points to a Byte). We have 512 kbyte cache data memory (first level cache). Each line holds 8 data words. Our cache have [H] lines. The LSB bits [I]..0 gives line offset. Assume the cache to be direct mapped. The address bits [J]..[K] are used as tag, address bits [L]..[M] points to a cache line. In the cache we will need [N] k-bit memory for the tag fields. For tag comparison we need [O] comparator(s), each [P] bits wide. Assume the cache to be set associative, where each set is 8 lines. The address bits [Q]..[R] are used as tag, address bits [S]..[T] points to a cache line.

6 5 Misc 10p. Mark correct alternative (1p for correct, -1/2p for incorrect). Please read the questions carefully. (You may never get less than 0p on this assignment.) If not stated otherwise, the architecture is the MIPS as used in the labs. A. A misaligned instruction memory address will cause a) an overflow exception b) a cache miss B. An arithmetic error (e.g., overflow) will cause a) no exception if Interrupts are disabled b) an exception even if Interrupts are disabled C. A TLB lookup error will a) cause an exception (i.e., the kernel will be invoked) b) always render a cache miss D. The TLB performs a) virtual to physical page number translation b) physical to virtual page number translation E. Virtual memory a) requires the system to be programmed in C b) improves performance of arithmetic operations F. The RFE instruction is used to a) push the mode stack (e.g., when the kernel is entered) b) pop the mode stack (e.g., on exiting the kernel) G. An interrupt can occur (i.e, invoke the kernel) if a) only if the cpu is in kernel mode b) only if the cpu is in user mode H. The dirty bit in a cache line indicates a) if there is an inconsistency between the cache and the next level in the memory hierarchy b) if there is an inconsistency between the cache and the internal register in the CPU I. Increased set associativity (larger sets) in the cache a) reduces risk of conflicts b) increases risk of conflicts J. Instruction addresses in a loop (assume a high number of iterations), have a) only temporal locality b) both temporal and spatial locality

7 Lycka till

8 Op Codes "expr" is any expression which can be reduced to a constant at assembly-time. "addr" has the form "expr" or else "expr(reg)". Often you will have to write "0(reg)". "rd,rs,rt" are registers (named or numbered), begin with a dollar sign. "label" is a reference to a label in your program. "SX(expr)" is the 16-bit immediate field sign-extended "ZX(expr)" is the 16-bit immediate field zero-extended ADD rd rs rt # rd := rs + rt, overflow will trap ADDI rt rs expr # rt := rs + SX(expr), overflow will trap ADDU rd rs rt # rd := rs + rt, no trap on overflow ADDIU rt rs expr # rt := rs + SX(expr), no trap on overflow AND rd rs rt # rd := rs & rt ANDI rt rs expr # rt := rs & ZX(expr) BEQ rs rt label # branch if contents rs equals rt's BGEZ rs label # branch if contents rs >= 0 BGEZAL rs label # branch if contents rs >= 0, link reg 31 BGTZ rs label # branch if contents rs > 0 BLEZ rs label # branch if contents rs <= 0 BLTZ rs label # branch if contents rs < 0 BLTZAL rs label # branch if contents rs < 0, link reg 31 BNE rs rt label # branch if contents rs not equal to rt's JALR rd rs # branch to address in rs, link to reg rd JR rs # branch to address in rs LB rt addr # load byte, sign-extended LBU rt addr # load byte, zero-extended LH rt addr # load halfword, sign-extended LHU rt addr # load halfword, zero-extended LUI rt expr # rt := (expr shifted left 16 bits) LW rt addr # load 32-bit word, word-aligned MFC0 rt rd # (kernel mode) rt := (CP0:rd) MTC0 rt rd # (kernel mode) (CP0:rd) := rt NOP # no operation NOR rd rs rt # rd := ~( rs rt ) OR rd rs rt # rd := rs rt ORI rt rs expr # rt := rs ZX(expr) RFE # return from exception (kernel mode) SB rt addr # store 8-bit byte SH rt addr # store 16-bit halfword, halfword-aligned SLL rd rt expr # rd := rt logical-shifted-left expr bits SLLV rd rt rs # rd := rt logical-shifted-left by value in rs SLT rd rs rt # rd := rs < rt, signed SLTI rt rs expr # rt := rs < SX(expr), signed SLTIU rt rs expr # rt := rs < SX(expr), unsigned (yes, SX) SLTU rd rs rt # rd := rs < rt, unsigned SRA rd rt expr # rd := rt arith-rightshifted expr bits SRAV rd rt rs # rd := rt arith-rightshifted by val in rs SRL rd rt expr # rd := rt logical-rightshifted expr bits SRLV rd rt rs # rd := rt logical-rightshifted by val in rs SUB rd rs rt # rd := rs - rt, overflow will trap SUBU rd rs rt # rd := rs - rt, no trap on overflow SW rt addr # store 32-bit word, word-aligned SYSCALL # trap to supervisor XOR rd rs rt # rd := rs ^ rt XORI rt rs expr # rt := rs ^ ZX(expr) note: SLLV, SRAV, SRLV shift amount is l.o. 5 bits of reg rs SIMULATOR-SPECIFIC OPCODE HALT # needed for simulator

TENTAMEN Luleå tekniska universitet

TENTAMEN Luleå tekniska universitet TENTAMEN Luleå tekniska universitet Kurskod: D0013E Kursnamn: Mikrodatorteknik Tentamensdatum: 2014-10-29 Skrivtid: 4 timmar Tillåtna hjälpmedel: Jourhavande lärare m fullständigt telefonnr: Per Lindgren

More information

TENTAMEN Luleå tekniska universitet

TENTAMEN Luleå tekniska universitet TENTAMEN Luleå tekniska universitet Kurskod: D0013E Kursnamn: Mikrodatorteknik Tentamensdatum: 2014-10-29 Skrivtid: 4 timmar Tillåtna hjälpmedel: Jourhavande lärare m fullständigt telefonnr: Per Lindgren

More information

MIPS Reference Guide

MIPS Reference Guide MIPS Reference Guide Free at PushingButtons.net 2 Table of Contents I. Data Registers 3 II. Instruction Register Formats 4 III. MIPS Instruction Set 5 IV. MIPS Instruction Set (Extended) 6 V. SPIM Programming

More information

Computer Architecture. The Language of the Machine

Computer Architecture. The Language of the Machine Computer Architecture The Language of the Machine Instruction Sets Basic ISA Classes, Addressing, Format Administrative Matters Operations, Branching, Calling conventions Break Organization All computers

More information

MIPS Instruction Format

MIPS Instruction Format MIPS Instruction Format MIPS uses a 32-bit fixed-length instruction format. only three different instruction word formats: There are Register format Op-code Rs Rt Rd Function code 000000 sssss ttttt ddddd

More information

MIPS Instruction Reference

MIPS Instruction Reference Page 1 of 9 MIPS Instruction Reference This is a description of the MIPS instruction set, their meanings, syntax, semantics, and bit encodings. The syntax given for each instruction refers to the assembly

More information

EEM 486: Computer Architecture. Lecture 2. MIPS Instruction Set Architecture

EEM 486: Computer Architecture. Lecture 2. MIPS Instruction Set Architecture EEM 486: Computer Architecture Lecture 2 MIPS Instruction Set Architecture EEM 486 Overview Instruction Representation Big idea: stored program consequences of stored program Instructions as numbers Instruction

More information

MIPS Instruction Set

MIPS Instruction Set MIPS Instruction Set Prof. James L. Frankel Harvard University Version of 7:12 PM 3-Apr-2018 Copyright 2018, 2017, 2016, 201 James L. Frankel. All rights reserved. CPU Overview CPU is an acronym for Central

More information

The MIPS Instruction Set Architecture

The MIPS Instruction Set Architecture The MIPS Set Architecture CPS 14 Lecture 5 Today s Lecture Admin HW #1 is due HW #2 assigned Outline Review A specific ISA, we ll use it throughout semester, very similar to the NiosII ISA (we will use

More information

F. Appendix 6 MIPS Instruction Reference

F. Appendix 6 MIPS Instruction Reference F. Appendix 6 MIPS Instruction Reference Note: ALL immediate values should be sign extended. Exception: For logical operations immediate values should be zero extended. After extensions, you treat them

More information

RTL Model of a Two-Stage MIPS Processor

RTL Model of a Two-Stage MIPS Processor RTL Model of a Two-Stage MIPS Processor 6.884 Laboratory February 4, 5 - Version 45 Introduction For the first lab assignment, you are to write an RTL model of a two-stage pipelined MIPS processor using

More information

Mips Code Examples Peter Rounce

Mips Code Examples Peter Rounce Mips Code Examples Peter Rounce P.Rounce@cs.ucl.ac.uk Some C Examples Assignment : int j = 10 ; // space must be allocated to variable j Possibility 1: j is stored in a register, i.e. register $2 then

More information

101 Assembly. ENGR 3410 Computer Architecture Mark L. Chang Fall 2009

101 Assembly. ENGR 3410 Computer Architecture Mark L. Chang Fall 2009 101 Assembly ENGR 3410 Computer Architecture Mark L. Chang Fall 2009 What is assembly? 79 Why are we learning assembly now? 80 Assembly Language Readings: Chapter 2 (2.1-2.6, 2.8, 2.9, 2.13, 2.15), Appendix

More information

Reduced Instruction Set Computer (RISC)

Reduced Instruction Set Computer (RISC) Reduced Instruction Set Computer (RISC) Reduced Instruction Set Computer (RISC) Focuses on reducing the number and complexity of instructions of the machine. Reduced number of cycles needed per instruction.

More information

Project Part A: Single Cycle Processor

Project Part A: Single Cycle Processor Curtis Mayberry Andrew Kies Mark Monat Iowa State University CprE 381 Professor Joseph Zambreno Project Part A: Single Cycle Processor Introduction The second part in the three part MIPS Processor design

More information

Question 0. Do not turn this page until you have received the signal to start. (Please fill out the identification section above) Good Luck!

Question 0. Do not turn this page until you have received the signal to start. (Please fill out the identification section above) Good Luck! CSC B58 Winter 2017 Final Examination Duration 2 hours and 50 minutes Aids allowed: none Last Name: Student Number: UTORid: First Name: Question 0. [1 mark] Read and follow all instructions on this page,

More information

Reduced Instruction Set Computer (RISC)

Reduced Instruction Set Computer (RISC) Reduced Instruction Set Computer (RISC) Focuses on reducing the number and complexity of instructions of the ISA. RISC Goals RISC: Simplify ISA Simplify CPU Design Better CPU Performance Motivated by simplifying

More information

CSc 256 Midterm 2 Fall 2011

CSc 256 Midterm 2 Fall 2011 CSc 256 Midterm 2 Fall 2011 NAME: 1a) You are given a MIPS branch instruction: x: beq $12, $0, y The address of the label "y" is 0x400468. The memory location at "x" contains: address contents 0x40049c

More information

ECE 2035 Programming HW/SW Systems Fall problems, 7 pages Exam Two 23 October 2013

ECE 2035 Programming HW/SW Systems Fall problems, 7 pages Exam Two 23 October 2013 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information

Computer Architecture. MIPS Instruction Set Architecture

Computer Architecture. MIPS Instruction Set Architecture Computer Architecture MIPS Instruction Set Architecture Instruction Set Architecture An Abstract Data Type Objects Registers & Memory Operations Instructions Goal of Instruction Set Architecture Design

More information

MIPS Assembly Language. Today s Lecture

MIPS Assembly Language. Today s Lecture MIPS Assembly Language Computer Science 104 Lecture 6 Homework #2 Midterm I Feb 22 (in class closed book) Outline Assembly Programming Reading Chapter 2, Appendix B Today s Lecture 2 Review: A Program

More information

Today s Lecture. MIPS Assembly Language. Review: What Must be Specified? Review: A Program. Review: MIPS Instruction Formats

Today s Lecture. MIPS Assembly Language. Review: What Must be Specified? Review: A Program. Review: MIPS Instruction Formats Today s Lecture Homework #2 Midterm I Feb 22 (in class closed book) MIPS Assembly Language Computer Science 14 Lecture 6 Outline Assembly Programming Reading Chapter 2, Appendix B 2 Review: A Program Review:

More information

M2 Instruction Set Architecture

M2 Instruction Set Architecture M2 Instruction Set Architecture Module Outline Addressing modes. Instruction classes. MIPS-I ISA. High level languages, Assembly languages and object code. Translating and starting a program. Subroutine

More information

A Processor. Kevin Walsh CS 3410, Spring 2010 Computer Science Cornell University. See: P&H Chapter , 4.1-3

A Processor. Kevin Walsh CS 3410, Spring 2010 Computer Science Cornell University. See: P&H Chapter , 4.1-3 A Processor Kevin Walsh CS 3410, Spring 2010 Computer Science Cornell University See: P&H Chapter 2.16-20, 4.1-3 Let s build a MIPS CPU but using Harvard architecture Basic Computer System Registers ALU

More information

MIPS ISA. 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support

MIPS ISA. 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support Components of an ISA EE 357 Unit 11 MIPS ISA 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support SUBtract instruc. vs. NEGate + ADD instrucs. 3. Registers accessible

More information

ECE Exam I February 19 th, :00 pm 4:25pm

ECE Exam I February 19 th, :00 pm 4:25pm ECE 3056 Exam I February 19 th, 2015 3:00 pm 4:25pm 1. The exam is closed, notes, closed text, and no calculators. 2. The Georgia Tech Honor Code governs this examination. 3. There are 4 questions and

More information

TSK3000A - Generic Instructions

TSK3000A - Generic Instructions TSK3000A - Generic Instructions Frozen Content Modified by Admin on Sep 13, 2017 Using the core set of assembly language instructions for the TSK3000A as building blocks, a number of generic instructions

More information

Processor. Han Wang CS3410, Spring 2012 Computer Science Cornell University. See P&H Chapter , 4.1 4

Processor. Han Wang CS3410, Spring 2012 Computer Science Cornell University. See P&H Chapter , 4.1 4 Processor Han Wang CS3410, Spring 2012 Computer Science Cornell University See P&H Chapter 2.16 20, 4.1 4 Announcements Project 1 Available Design Document due in one week. Final Design due in three weeks.

More information

SPIM Instruction Set

SPIM Instruction Set SPIM Instruction Set This document gives an overview of the more common instructions used in the SPIM simulator. Overview The SPIM simulator implements the full MIPS instruction set, as well as a large

More information

EE108B Lecture 3. MIPS Assembly Language II

EE108B Lecture 3. MIPS Assembly Language II EE108B Lecture 3 MIPS Assembly Language II Christos Kozyrakis Stanford University http://eeclass.stanford.edu/ee108b 1 Announcements Urgent: sign up at EEclass and say if you are taking 3 or 4 units Homework

More information

Anne Bracy CS 3410 Computer Science Cornell University. See P&H Chapter: , , Appendix B

Anne Bracy CS 3410 Computer Science Cornell University. See P&H Chapter: , , Appendix B Anne Bracy CS 3410 Computer Science Cornell University The slides are the product of many rounds of teaching CS 3410 by Professors Weatherspoon, Bala, Bracy, and Sirer. See P&H Chapter: 2.16-2.20, 4.1-4.4,

More information

CSc 256 Midterm 2 Spring 2012

CSc 256 Midterm 2 Spring 2012 CSc 256 Midterm 2 Spring 2012 NAME: 1a) You are given this MIPS assembly language instruction (i.e., pseudo- instruction): ble $12, 0x20004880, there Translate this MIPS instruction to an efficient sequence

More information

Computer Architecture Experiment

Computer Architecture Experiment Computer Architecture Experiment Jiang Xiaohong College of Computer Science & Engineering Zhejiang University Architecture Lab_jxh 1 Topics 0 Basic Knowledge 1 Warm up 2 simple 5-stage of pipeline CPU

More information

ece4750-parc-isa.txt

ece4750-parc-isa.txt ========================================================================== PARC Instruction Set Architecture ========================================================================== # Author : Christopher

More information

Mark Redekopp, All rights reserved. EE 357 Unit 11 MIPS ISA

Mark Redekopp, All rights reserved. EE 357 Unit 11 MIPS ISA EE 357 Unit 11 MIPS ISA Components of an ISA 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support SUBtract instruc. vs. NEGate + ADD instrucs. 3. Registers accessible

More information

Q1: /30 Q2: /25 Q3: /45. Total: /100

Q1: /30 Q2: /25 Q3: /45. Total: /100 ECE 2035(A) Programming for Hardware/Software Systems Fall 2013 Exam One September 19 th 2013 This is a closed book, closed note texam. Calculators are not permitted. Please work the exam in pencil and

More information

Anne Bracy CS 3410 Computer Science Cornell University. [K. Bala, A. Bracy, E. Sirer, and H. Weatherspoon]

Anne Bracy CS 3410 Computer Science Cornell University. [K. Bala, A. Bracy, E. Sirer, and H. Weatherspoon] Anne Bracy CS 3410 Computer Science Cornell University [K. Bala, A. Bracy, E. Sirer, and H. Weatherspoon] Understanding the basics of a processor We now have the technology to build a CPU! Putting it all

More information

Flow of Control -- Conditional branch instructions

Flow of Control -- Conditional branch instructions Flow of Control -- Conditional branch instructions You can compare directly Equality or inequality of two registers One register with 0 (>,

More information

ECE 2035 Programming HW/SW Systems Spring problems, 6 pages Exam One 4 February Your Name (please print clearly)

ECE 2035 Programming HW/SW Systems Spring problems, 6 pages Exam One 4 February Your Name (please print clearly) Your Name (please print clearly) This exam will be conducted according to the Georgia Tech Honor Code. I pledge to neither give nor receive unauthorized assistance on this exam and to abide by all provisions

More information

Overview. Introduction to the MIPS ISA. MIPS ISA Overview. Overview (2)

Overview. Introduction to the MIPS ISA. MIPS ISA Overview. Overview (2) Introduction to the MIPS ISA Overview Remember that the machine only understands very basic instructions (machine instructions) It is the compiler s job to translate your high-level (e.g. C program) into

More information

CSc 256 Midterm (green) Fall 2018

CSc 256 Midterm (green) Fall 2018 CSc 256 Midterm (green) Fall 2018 NAME: Problem 1 (5 points): Suppose we are tracing a C/C++ program using a debugger such as gdb. The code showing all function calls looks like this: main() { bat(5);

More information

CS 4200/5200 Computer Architecture I

CS 4200/5200 Computer Architecture I CS 4200/5200 Computer Architecture I MIPS Instruction Set Architecture Dr. Xiaobo Zhou Department of Computer Science CS420/520 Lec3.1 UC. Colorado Springs Adapted from UCB97 & UCB03 Review: Organizational

More information

INSTRUCTION SET COMPARISONS

INSTRUCTION SET COMPARISONS INSTRUCTION SET COMPARISONS MIPS SPARC MOTOROLA REGISTERS: INTEGER 32 FIXED WINDOWS 32 FIXED FP SEPARATE SEPARATE SHARED BRANCHES: CONDITION CODES NO YES NO COMPARE & BR. YES NO YES A=B COMP. & BR. YES

More information

MIPS Coding Snippets. Prof. James L. Frankel Harvard University. Version of 9:32 PM 14-Feb-2016 Copyright 2016 James L. Frankel. All rights reserved.

MIPS Coding Snippets. Prof. James L. Frankel Harvard University. Version of 9:32 PM 14-Feb-2016 Copyright 2016 James L. Frankel. All rights reserved. MIPS Coding Snippets Prof. James L. Frankel Harvard University Version of 9:32 PM 14-Feb-2016 Copyright 2016 James L. Frankel. All rights reserved. Loading a 32-bit constant into a register # Example loading

More information

Kernel Registers 0 1. Global Data Pointer. Stack Pointer. Frame Pointer. Return Address.

Kernel Registers 0 1. Global Data Pointer. Stack Pointer. Frame Pointer. Return Address. The MIPS Register Set The MIPS R2000 CPU has 32 registers. 31 of these are general-purpose registers that can be used in any of the instructions. The last one, denoted register zero, is defined to contain

More information

Midterm. Sticker winners: if you got >= 50 / 67

Midterm. Sticker winners: if you got >= 50 / 67 CSC258 Week 8 Midterm Class average: 4.2 / 67 (6%) Highest mark: 64.5 / 67 Tests will be return in office hours. Make sure your midterm mark is correct on MarkUs Solution posted on the course website.

More information

Examples of branch instructions

Examples of branch instructions Examples of branch instructions Beq rs,rt,target #go to target if rs = rt Beqz rs, target #go to target if rs = 0 Bne rs,rt,target #go to target if rs!= rt Bltz rs, target #go to target if rs < 0 etc.

More information

ECE 2035 Programming HW/SW Systems Spring problems, 6 pages Exam Two 11 March Your Name (please print) total

ECE 2035 Programming HW/SW Systems Spring problems, 6 pages Exam Two 11 March Your Name (please print) total Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information

Computer Architecture Instruction Set Architecture part 2. Mehran Rezaei

Computer Architecture Instruction Set Architecture part 2. Mehran Rezaei Computer Architecture Instruction Set Architecture part 2 Mehran Rezaei Review Execution Cycle Levels of Computer Languages Stored Program Computer/Instruction Execution Cycle SPIM, a MIPS Interpreter

More information

software hardware Which is easier to change/design???

software hardware Which is easier to change/design??? CS152 Computer Architecture and Engineering Lecture 2 Review of MIPS ISA and Performance January 27, 2003 John Kubiatowicz (http.cs.berkeley.edu/~kubitron) lecture slides: http://inst.eecs.berkeley.edu/~cs152/

More information

ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam One 22 September Your Name (please print clearly) Signed.

ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam One 22 September Your Name (please print clearly) Signed. Your Name (please print clearly) This exam will be conducted according to the Georgia Tech Honor Code. I pledge to neither give nor receive unauthorized assistance on this exam and to abide by all provisions

More information

Instruction Set Architecture of. MIPS Processor. MIPS Processor. MIPS Registers (continued) MIPS Registers

Instruction Set Architecture of. MIPS Processor. MIPS Processor. MIPS Registers (continued) MIPS Registers CSE 675.02: Introduction to Computer Architecture MIPS Processor Memory Instruction Set Architecture of MIPS Processor CPU Arithmetic Logic unit Registers $0 $31 Multiply divide Coprocessor 1 (FPU) Registers

More information

The MIPS R2000 Instruction Set

The MIPS R2000 Instruction Set The MIPS R2000 Instruction Set Arithmetic and Logical Instructions In all instructions below, Src2 can either be a register or an immediate value (a 16 bit integer). The immediate forms of the instructions

More information

Instruction Set Architecture part 1 (Introduction) Mehran Rezaei

Instruction Set Architecture part 1 (Introduction) Mehran Rezaei Instruction Set Architecture part 1 (Introduction) Mehran Rezaei Overview Last Lecture s Review Execution Cycle Levels of Computer Languages Stored Program Computer/Instruction Execution Cycle SPIM, a

More information

CPS311 - COMPUTER ORGANIZATION. A bit of history

CPS311 - COMPUTER ORGANIZATION. A bit of history CPS311 - COMPUTER ORGANIZATION A Brief Introduction to the MIPS Architecture A bit of history The MIPS architecture grows out of an early 1980's research project at Stanford University. In 1984, MIPS computer

More information

MIPS Assembly Language Programming

MIPS Assembly Language Programming MIPS Assembly Language Programming Bob Britton Chapter 1 The MIPS Architecture My objective in teaching assembly language is to introduce students to the fundamental concepts of contemporary computer architecture.

More information

CSc 256 Final Fall 2016

CSc 256 Final Fall 2016 CSc 256 Final Fall 2016 NAME: Problem 1 (25 points) Translate the C/C++ function func() into MIPS assembly language. The prototype is: void func(int arg0, int *arg1); arg0-arg1 are in $a0- $a1 respectively.

More information

Week 10: Assembly Programming

Week 10: Assembly Programming Week 10: Assembly Programming Arithmetic instructions Instruction Opcode/Function Syntax Operation add 100000 $d, $s, $t $d = $s + $t addu 100001 $d, $s, $t $d = $s + $t addi 001000 $t, $s, i $t = $s +

More information

ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam One 19 September 2012

ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam One 19 September 2012 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information

Lec 10: Assembler. Announcements

Lec 10: Assembler. Announcements Lec 10: Assembler Kavita Bala CS 3410, Fall 2008 Computer Science Cornell University Announcements HW 2 is out Due Wed after Fall Break Robot-wide paths PA 1 is due next Wed Don t use incrementor 4 times

More information

CS 351 Exam 2 Mon. 11/2/2015

CS 351 Exam 2 Mon. 11/2/2015 CS 351 Exam 2 Mon. 11/2/2015 Name: Rules and Hints The MIPS cheat sheet and datapath diagram are attached at the end of this exam for your reference. You may use one handwritten 8.5 11 cheat sheet (front

More information

ECE232: Hardware Organization and Design. Computer Organization - Previously covered

ECE232: Hardware Organization and Design. Computer Organization - Previously covered ECE232: Hardware Organization and Design Part 6: MIPS Instructions II http://www.ecs.umass.edu/ece/ece232/ Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Computer Organization

More information

A Processor! Hakim Weatherspoon CS 3410, Spring 2010 Computer Science Cornell University. See: P&H Chapter , 4.1-3

A Processor! Hakim Weatherspoon CS 3410, Spring 2010 Computer Science Cornell University. See: P&H Chapter , 4.1-3 A Processor! Hakim Weatherspoon CS 3410, Spring 2010 Computer Science Cornell University See: P&H Chapter 2.16-20, 4.1-3 Announcements! HW2 available later today HW2 due in one week and a half Work alone

More information

ECE 2035 A Programming Hw/Sw Systems Fall problems, 8 pages Final Exam 8 December 2014

ECE 2035 A Programming Hw/Sw Systems Fall problems, 8 pages Final Exam 8 December 2014 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information

Review: Organization. CS152 Computer Architecture and Engineering Lecture 2. Review of MIPS ISA and Design Concepts

Review: Organization. CS152 Computer Architecture and Engineering Lecture 2. Review of MIPS ISA and Design Concepts Review: Organization Processor Input CS52 Computer Architecture and Engineering Lecture 2 Control Review of MIPS ISA and Design Concepts path Output January 26, 24 John Kubiatowicz (http.cs.berkeley.edu/~kubitron)

More information

Mark Redekopp, All rights reserved. EE 352 Unit 3 MIPS ISA

Mark Redekopp, All rights reserved. EE 352 Unit 3 MIPS ISA EE 352 Unit 3 MIPS ISA Instruction Set Architecture (ISA) Defines the software interface of the processor and memory system Instruction set is the vocabulary the HW can understand and the SW is composed

More information

Recap from Last Time. CSE 2021: Computer Organization. Levels of Programming. The RISC Philosophy 5/19/2011

Recap from Last Time. CSE 2021: Computer Organization. Levels of Programming. The RISC Philosophy 5/19/2011 CSE 2021: Computer Organization Recap from Last Time load from disk High-Level Program Lecture-3 Code Translation-1 Registers, Arithmetic, logical, jump, and branch instructions MIPS to machine language

More information

CISC 662 Graduate Computer Architecture. Lecture 4 - ISA MIPS ISA. In a CPU. (vonneumann) Processor Organization

CISC 662 Graduate Computer Architecture. Lecture 4 - ISA MIPS ISA. In a CPU. (vonneumann) Processor Organization CISC 662 Graduate Computer Architecture Lecture 4 - ISA MIPS ISA Michela Taufer http://www.cis.udel.edu/~taufer/courses Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture,

More information

ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam Two 23 October Your Name (please print clearly) Signed.

ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam Two 23 October Your Name (please print clearly) Signed. Your Name (please print clearly) This exam will be conducted according to the Georgia Tech Honor Code. I pledge to neither give nor receive unauthorized assistance on this exam and to abide by all provisions

More information

5/17/2012. Recap from Last Time. CSE 2021: Computer Organization. The RISC Philosophy. Levels of Programming. Stored Program Computers

5/17/2012. Recap from Last Time. CSE 2021: Computer Organization. The RISC Philosophy. Levels of Programming. Stored Program Computers CSE 2021: Computer Organization Recap from Last Time load from disk High-Level Program Lecture-2 Code Translation-1 Registers, Arithmetic, logical, jump, and branch instructions MIPS to machine language

More information

ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam Two 21 October 2016

ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam Two 21 October 2016 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information

MACHINE LANGUAGE. To work with the machine, we need a translator.

MACHINE LANGUAGE. To work with the machine, we need a translator. LECTURE 2 Assembly MACHINE LANGUAGE As humans, communicating with a machine is a tedious task. We can t, for example, just say add this number and that number and store the result here. Computers have

More information

ICS 233 COMPUTER ARCHITECTURE. MIPS Processor Design Multicycle Implementation

ICS 233 COMPUTER ARCHITECTURE. MIPS Processor Design Multicycle Implementation ICS 233 COMPUTER ARCHITECTURE MIPS Processor Design Multicycle Implementation Lecture 23 1 Add immediate unsigned Subtract unsigned And And immediate Or Or immediate Nor Shift left logical Shift right

More information

CISC 662 Graduate Computer Architecture. Lecture 4 - ISA

CISC 662 Graduate Computer Architecture. Lecture 4 - ISA CISC 662 Graduate Computer Architecture Lecture 4 - ISA Michela Taufer http://www.cis.udel.edu/~taufer/courses Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture,

More information

Assembly Programming

Assembly Programming Designing Computer Systems Assembly Programming 08:34:48 PM 23 August 2016 AP-1 Scott & Linda Wills Designing Computer Systems Assembly Programming In the early days of computers, assembly programming

More information

EE 109 Unit 8 MIPS Instruction Set

EE 109 Unit 8 MIPS Instruction Set 1 EE 109 Unit 8 MIPS Instruction Set 2 Architecting a vocabulary for the HW INSTRUCTION SET OVERVIEW 3 Instruction Set Architecture (ISA) Defines the software interface of the processor and memory system

More information

Outline. EEL-4713 Computer Architecture Multipliers and shifters. Deriving requirements of ALU. MIPS arithmetic instructions

Outline. EEL-4713 Computer Architecture Multipliers and shifters. Deriving requirements of ALU. MIPS arithmetic instructions Outline EEL-4713 Computer Architecture Multipliers and shifters Multiplication and shift registers Chapter 3, section 3.4 Next lecture Division, floating-point 3.5 3.6 EEL-4713 Ann Gordon-Ross.1 EEL-4713

More information

ENCM 369 Winter 2013: Reference Material for Midterm #2 page 1 of 5

ENCM 369 Winter 2013: Reference Material for Midterm #2 page 1 of 5 ENCM 369 Winter 2013: Reference Material for Midterm #2 page 1 of 5 MIPS/SPIM General Purpose Registers Powers of Two 0 $zero all bits are zero 16 $s0 local variable 1 $at assembler temporary 17 $s1 local

More information

MIPS Instructions: 64-bit Core Subset

MIPS Instructions: 64-bit Core Subset MIPS Instructions: 64-bit Core Subset Spring 2008 General notes: a. R s, R t, and R d specify 64-bit general purpose registers b. F s, F t, and F d specify 64-bit floating point registers c. C d specifies

More information

CS3350B Computer Architecture MIPS Instruction Representation

CS3350B Computer Architecture MIPS Instruction Representation CS3350B Computer Architecture MIPS Instruction Representation Marc Moreno Maza http://www.csd.uwo.ca/~moreno/cs3350_moreno/index.html Department of Computer Science University of Western Ontario, Canada

More information

ECE 2035 A Programming Hw/Sw Systems Spring problems, 8 pages Final Exam 29 April 2015

ECE 2035 A Programming Hw/Sw Systems Spring problems, 8 pages Final Exam 29 April 2015 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information

EE 109 Unit 13 MIPS Instruction Set. Instruction Set Architecture (ISA) Components of an ISA INSTRUCTION SET OVERVIEW

EE 109 Unit 13 MIPS Instruction Set. Instruction Set Architecture (ISA) Components of an ISA INSTRUCTION SET OVERVIEW 1 2 EE 109 Unit 13 MIPS Instruction Set Architecting a vocabulary for the HW INSTRUCTION SET OVERVIEW 3 4 Instruction Set Architecture (ISA) Defines the of the processor and memory system Instruction set

More information

Computer Organization & Design

Computer Organization & Design Computer Organization & Design Peng Liu ( 刘鹏 ) College of Information Science & Electronic Engineering Zhejiang University, Hangzhou 310027, China liupeng@zju.edu.cn Lecture 2 MIPS Instruction Set Architecture

More information

MIPS%Assembly% E155%

MIPS%Assembly% E155% MIPS%Assembly% E155% Outline MIPS Architecture ISA Instruction types Machine codes Procedure call Stack 2 The MIPS Register Set Name Register Number Usage $0 0 the constant value 0 $at 1 assembler temporary

More information

ECE 15B Computer Organization Spring 2010

ECE 15B Computer Organization Spring 2010 ECE 15B Computer Organization Spring 2010 Dmitri Strukov Lecture 7: Procedures I Partially adapted from Computer Organization and Design, 4 th edition, Patterson and Hennessy, and classes taught by and

More information

ECE 2035 Programming HW/SW Systems Spring problems, 6 pages Exam Three 10 April 2013

ECE 2035 Programming HW/SW Systems Spring problems, 6 pages Exam Three 10 April 2013 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information

Instruction Set Principles. (Appendix B)

Instruction Set Principles. (Appendix B) Instruction Set Principles (Appendix B) Outline Introduction Classification of Instruction Set Architectures Addressing Modes Instruction Set Operations Type & Size of Operands Instruction Set Encoding

More information

MIPS Assembly Language

MIPS Assembly Language MIPS Assembly Language Chapter 15 S. Dandamudi Outline MIPS architecture Registers Addressing modes MIPS instruction set Instruction format Data transfer instructions Arithmetic instructions Logical/shift/rotate/compare

More information

ECE 2035 A Programming Hw/Sw Systems Fall problems, 8 pages Final Exam 9 December 2015

ECE 2035 A Programming Hw/Sw Systems Fall problems, 8 pages Final Exam 9 December 2015 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information

Lecture 2. Instructions: Language of the Computer (Chapter 2 of the textbook)

Lecture 2. Instructions: Language of the Computer (Chapter 2 of the textbook) Lecture 2 Instructions: Language of the Computer (Chapter 2 of the textbook) Instructions: tell computers what to do Chapter 2 Instructions: Language of the Computer 2 Introduction Chapter 2.1 Chapter

More information

Computer Architecture

Computer Architecture CS3350B Computer Architecture Winter 2015 Lecture 4.2: MIPS ISA -- Instruction Representation Marc Moreno Maza www.csd.uwo.ca/courses/cs3350b [Adapted from lectures on Computer Organization and Design,

More information

ECE 2035 Programming Hw/Sw Systems Fall problems, 10 pages Final Exam 9 December 2013

ECE 2035 Programming Hw/Sw Systems Fall problems, 10 pages Final Exam 9 December 2013 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information

MIPS Assembly Programming

MIPS Assembly Programming COMP 212 Computer Organization & Architecture COMP 212 Fall 2008 Lecture 8 Cache & Disk System Review MIPS Assembly Programming Comp 212 Computer Org & Arch 1 Z. Li, 2008 Comp 212 Computer Org & Arch 2

More information

Final Project: MIPS-like Microprocessor

Final Project: MIPS-like Microprocessor Final Project: MIPS-like Microprocessor Objective: The objective of this project is to design, simulate, and implement a simple 32-bit microprocessor with an instruction set that is similar to a MIPS.

More information

CSCI 402: Computer Architectures. Instructions: Language of the Computer (3) Fengguang Song Department of Computer & Information Science IUPUI.

CSCI 402: Computer Architectures. Instructions: Language of the Computer (3) Fengguang Song Department of Computer & Information Science IUPUI. CSCI 402: Computer Architectures Instructions: Language of the Computer (3) Fengguang Song Department of Computer & Information Science IUPUI Recall Big endian, little endian Memory alignment Unsigned

More information

Programming the processor

Programming the processor CSC258 Week 9 Logistics This week: Lab 7 is the last Logisim DE2 lab. Next week: Lab 8 will be assembly. For assembly labs you can work individually or in pairs. No matter how you do it, the important

More information

Review. Lecture #9 MIPS Logical & Shift Ops, and Instruction Representation I Logical Operators (1/3) Bitwise Operations

Review. Lecture #9 MIPS Logical & Shift Ops, and Instruction Representation I Logical Operators (1/3) Bitwise Operations CS6C L9 MIPS Logical & Shift Ops, and Instruction Representation I () inst.eecs.berkeley.edu/~cs6c CS6C : Machine Structures Lecture #9 MIPS Logical & Shift Ops, and Instruction Representation I 25-9-28

More information

Adventures in Assembly Land

Adventures in Assembly Land Adventures in Assembly Land What is an Assembler ASM Directives ASM Syntax Intro to SPIM Simple examples L6 Simulator 1 A Simple Programming Task Add the numbers 0 to 4 10 = 0 + 1 + 2 + 3 + 4 In C : int

More information

Instructions: Language of the Computer

Instructions: Language of the Computer Instructions: Language of the Computer Tuesday 22 September 15 Many slides adapted from: and Design, Patterson & Hennessy 5th Edition, 2014, MK and from Prof. Mary Jane Irwin, PSU Summary Previous Class

More information

CSSE 232 Computer Architecture I. I/O and Addressing

CSSE 232 Computer Architecture I. I/O and Addressing CSSE 232 Computer Architecture I I/O and Addressing 1 / 21 Class Status Reading for today 2.9-2.10, 6.6 (optional) 2 / 21 Outline I/O More memory instructions Addressing modes Jump and branch instructions

More information