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1 COEN-4710 Computer Hardware Lecture 4 Processor Part 2: Pipelining (Ch.4) Cristinel Ababei Department of Electrical and Computer Engineering Credits: Slides adapted primarily from presentations from Mike Johnson, Richard Povinelli, David Patterson, Morgan Kaufmann, and other online sources Page 1 Outline Pipelining Introduction Pipelined MIPS Datapath Pipeline Control Data Hazards Address data hazards - forwarding (HW solution) Double data hazards - revised forwarding Load-use data hazards - hazard detection unit to Stall Branch Hazards Flush Exceptions Exception Handling Routine Improving Performance Page 2 1

2 Laundry Example Pipelining is Natural! Ann, Brian, Cathy, Dave each have one load of clothes to wash, dry, and fold Washer takes 30 minutes A B C D Dryer takes 30 minutes Folder takes 30 minutes Stasher takes 30 minutes to put clothes into drawers Page 3 Sequential Laundry Sequential laundry takes 8 hours for 4 loads 6 PM AM T a s k O r d e r A B C D Time If we pipelined, how long would laundry take? Page 4 2

3 Pipelined Laundry: Start work ASAP Pipelined laundry takes 3.5 hours for 4 loads! 12 2 AM 6 PM T a s k A B Time O r d e r C D What s the theoretical speedup? Page 5 Pipelining Lessons T a s k O r d e r 6 PM Time A B C D Pipelining doesn t help latency of a single task, it helps throughput of entire workload Max potential speedup is Number of pipe stages Performance limited by slowest pipeline stage (Unbalanced lengths of pipe) Time to fill pipeline and time to drain it reduces speedup Might need to stall for dependencies Page 6 3

4 The Five Stages of Load Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Load Ifetch Reg/Dec Exec Mem Wr 1. IF: Get instruction from Instruction Memory 2. ID: Register Fetch and Instruction Decode 3. EX: Calculate the memory address 4. MEM: Read the data from data Memory 5. WB: Write the data back to the register file Page 7 Pipelining Improve performance by increasing instruction throughput Program execution order Time (in instructions) lw $1, 100($0) lw $2, 200($0) lw $3, 300($0) Program execution Time order (in instructions) lw $1, 100($0) lw $2, 200($0) lw $3, 300($0) Instruction fetch Instruction fetch 2 ns Reg ALU 8 ns Data access Reg Instruction fetch Reg ALU 8 ns Data access Reg Instruction fetch 2 ns ALU Reg Instruction fetch Data access ALU Reg Reg Data access ALU Reg Data access Reg 2 ns 2 ns 2 ns 2 ns 2 ns Reg Instruction fetch 8 ns... Note when register reads and writes occur What is the ideal speedup for this pipeline? Page 8 4

5 Pipeline Speedup If all stages are balanced i.e., all take the same time Time between instructions pipelined = Time between instructions nonpipelined Number of stages If not balanced, speedup is less Speedup due to increased throughput Latency (time for each instruction) does not decrease Page 9 Implementing Pipelining What makes it easy MIPS instructions are all the same length Just a few instruction formats Memory operands appear only in loads and stores What makes it hard Structural hazards Multiple instructions needing the same datapath components Data hazards Instructions depending on previous instruction s output Control hazards Changes to instruction sequence - branching, jumping, Exception handling: overflows, interrupts Page 10 5

6 Basic MIPS Datapath Structure MEM Right-to-left flow leads to hazards WB Page 11 Pipeline registers Need registers between stages To hold information produced in previous cycle Page 12 6

7 Pipeline Operation Cycle-by-cycle flow of instructions through the pipelined datapath Single-clock-cycle pipeline diagram Shows pipeline usage in a single cycle Highlight resources used c.f. multi-clock-cycle diagram Graph of operation over time We ll look at single-clock-cycle diagrams for load & store Page 13 IF for Load, Store, Page 14 7

8 ID for Load, Store, Page 15 EX for Load Page 16 8

9 MEM for Load Page 17 WB for Load Wrong register number Page 18 9

10 Corrected Datapath for Load Page 19 EX for Store Page 20 10

11 MEM for Store Page 21 WB for Store Page 22 11

12 Graphically Representing Pipelines Program execution order (in instructions) lw$10, 20($1) Time (in clockcycles) CC1 CC2 CC3 CC4 CC5 CC6 IM Reg ALU DM Reg sub $11, $2, $3 IM Reg ALU DM Reg Can help with answering questions like: How many cycles does it take to execute this code? What is the ALU doing during cycle 4? Grayed portions what s being used for this instruction. Page 23 Multi-Cycle Pipeline Diagram Form showing resource usage Page 24 12

13 Single-Cycle Pipeline Diagram State of pipeline in a given cycle Page 25 Pipeline Control (Simplified) Page 26 13

14 Pipeline control We have 5 separate stages 1. IF: Instruction Fetch and PC Increment 2. ID: Instruction Decode / Register Fetch 3. EX: Execution 4. MEM: Memory Access 5. WR: Write Back How should control be handled? A fancy control center telling everyone what to do? Should we use a state machine? What lines need to be controlled in each stage? Page 27 Pipeline Control Pass control signals along just like the data Execution/Address Calculation stage control lines Memory access stage control lines Write-back stage control lines Instruction Reg Dst ALU Op1 ALU Op0 ALU Src Branch Mem Read Mem Write Reg write Mem to Reg R-format lw sw X X beq X X Page 28 14

15 Datapath with Control Page 29 (1) Data Hazards in ALU Instructions Consider this sequence: sub $2, $1,$3 and $12,$2,$5 or $13,$6,$2 add $14,$2,$2 sw $15,100($2) Page 30 15

16 Data hazards Problem with starting next instruction before first is finished have dependencies that go backward in time Page 31 Software Solution Have compiler guarantee no hazards: no ops sub $2, $1, $3 and $12, $2, $5 or $13, $6, $2 add $14, $2, $2 sw $15, 100($2) Where would we put no ops in this example? Problem: this slows things down! Page 32 16

17 Hardware solution - Forwarding Forwarding: Use outputs before they are actually written Page 33 Detecting the Need to Forward Pass register numbers along pipeline e.g., ID/EX.RegisterRs = register number for Rs sitting in ID/EX pipeline register ALU operand register numbers in EX stage are given by ID/EX.RegisterRs, ID/EX.RegisterRt Data hazards when 1a. EX/MEM.RegisterRd = ID/EX.RegisterRs 1b. EX/MEM.RegisterRd = ID/EX.RegisterRt 2a. MEM/WB.RegisterRd = ID/EX.RegisterRs 2b. MEM/WB.RegisterRd = ID/EX.RegisterRt Fwd from EX/MEM pipeline reg Fwd from MEM/WB pipeline reg Page 34 17

18 Detecting the Need to Forward But only if forwarding instruction will write to a register! EX/MEM.RegWrite, MEM/WB.RegWrite And only if Rd for that instruction is not $zero EX/MEM.RegisterRd 0, MEM/WB.RegisterRd 0 Page 35 Forwarding Paths Page 36 18

19 EX hazard Forwarding Conditions if (EX/MEM.RegWrite and (EX/MEM.RegisterRd 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRs)) ForwardA = 10 if (EX/MEM.RegWrite and (EX/MEM.RegisterRd 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRt)) ForwardB = 10 MEM hazard if (MEM/WB.RegWrite and (MEM/WB.RegisterRd 0) and (MEM/WB.RegisterRd = ID/EX.RegisterRs)) ForwardA = 01 if (MEM/WB.RegWrite and (MEM/WB.RegisterRd 0) and (MEM/WB.RegisterRd = ID/EX.RegisterRt)) ForwardB = 01 Page 37 (2) Double Data Hazard Consider the sequence: add $1,$1,$2 add $1,$1,$3 add $1,$1,$4 Both hazards occur Want to use the most recent Revise MEM hazard condition Only fwd if EX hazard condition isn t true Page 38 19

20 Revised Forwarding Condition MEM hazard if (MEM/WB.RegWrite and (MEM/WB.RegisterRd 0) and not (EX/MEM.RegWrite and (EX/MEM.RegisterRd 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRs)) and (MEM/WB.RegisterRd = ID/EX.RegisterRs)) ForwardA = 01 if (MEM/WB.RegWrite and (MEM/WB.RegisterRd 0) and not (EX/MEM.RegWrite and (EX/MEM.RegisterRd 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRt)) and (MEM/WB.RegisterRd = ID/EX.RegisterRt)) ForwardB = 01 Page 39 Datapath with Forwarding When might this not work? Page 40 20

21 (3) Load-Use Data Hazard Load word can still cause a hazard: Can t read a register after a load instruction writes to same register Need a hazard detection unit to stall the pipeline Need to stall for one cycle Page 41 Load-Use Hazard Detection Check when using instruction is decoded in ID stage ALU operand register numbers in ID stage are given by IF/ID.RegisterRs, IF/ID.RegisterRt Load-use hazard when ID/EX.MemRead and ((ID/EX.RegisterRt = IF/ID.RegisterRs) or (ID/EX.RegisterRt = IF/ID.RegisterRt)) If detected, stall and insert bubble Page 42 21

22 How to Stall the Pipeline Force control values in ID/EX register to 0 EX, MEM and WB do nop (no-operation) Prevent update of PC and IF/ID register Using instruction is decoded again Following instruction is fetched again 1-cycle stall allows MEM to read data for lw Can subsequently forward to EX stage Forwarding and stalling are fully inter-operable; a forward will operate correctly even across a stalled-stage in the pipeline. Page 43 Stall/Bubble in the Pipeline Stall inserted here Page 44 22

23 Stall/Bubble in the Pipeline Or, more accurately Page 45 Hazard Detection Unit How are we forcing a repeated stage here? Page 46 23

24 Code Scheduling to Avoid Stalls Reorder code to avoid use of load result in the next instruction C code for A = B + E; C = B + F; stall stall lw $t1, 0($t0) lw $t2, 4($t0) add $t3, $t1, $t2 sw $t3, 12($t0) lw $t4, 8($t0) add $t5, $t1, $t4 sw $t5, 16($t0) 13 cycles lw $t1, 0($t0) lw $t2, 4($t0) lw $t4, 8($t0) add $t3, $t1, $t2 sw $t3, 12($t0) add $t5, $t1, $t4 sw $t5, 16($t0) 11 cycles Page 47 (4) Branch Hazards If branch outcome determined at the end of EX stage By the time we know to branch, new instructions are in the pipe! : Flush these instructions (Set control values to 0) PC Page 48 24

25 We are basically predicting branch not taken What if it is? Predict Toss all instructions in the pipe Keep going (the branch instruction will update the PC correctly and we ll get to the right place) Undo any memory/register changes (this won t happen, since that s at the end of the pipe) So how do we tell the datapath to quit executing an instruction in the middle of the pipeline? Page 49 Flush To flush the pipe (when branch is taken) Set IF.Flush (new control line) Zero all control lines Similar to stall, except don t disable the PC and IF/ID write controls this effectively writes over what the previous instruction was doing. No memory or register writes will have yet happened, so everything else is OK Could we make the decision quicker, to lose fewer clock cycles? Page 50 25

26 Reducing Branch Delay Move hardware to determine outcome to ID stage Target address adder Register comparator This means the branch decision can be made during the ID stage instead of the EX stage. This is why we need an IF.Flush, but not an ID.Flush! But Problem: Messes up forwarding for branching Page 51 Example: Branch Taken Page 52 26

27 Example: Branch Taken Page 53 Data Hazards for Branches If a comparison register is a destination of 2 nd or 3 rd preceding ALU instruction add $1, $2, $3 IF ID EX MEM WB add $4, $5, $6 IF ID EX MEM WB IF ID EX MEM WB beq $1, $4, target IF ID EX MEM WB Can resolve using forwarding Page 54 27

28 Data Hazards for Branches If a comparison register is a destination of preceding ALU instruction or 2 nd preceding load instruction Need 1 stall cycle lw $1, addr IF ID EX MEM WB add $4, $5, $6 IF ID EX MEM WB beq stalled IF ID beq $1, $4, target ID EX MEM WB Page 55 Data Hazards for Branches If a comparison register is a destination of immediately preceding load instruction Need 2 stall cycles lw $1, addr IF ID EX MEM WB beq stalled IF ID beq stalled ID beq $1, $0, target ID EX MEM WB Page 56 28

29 Other branch hazard methods Dynamic branch prediction Keep a table of bits associated with the current chunk of memory, telling whether a branch was taken last time that instruction was executed. Use that to guess at the next instruction to execute Delayed branching Make the instruction set operate such that at a branch the following instruction is always executed, then the branch actually occurs. Puts the work on the programmer / assembler. MIPS does this!! (hidden in the assembler). Page 57 Stalls and Performance The BIG Picture Stalls reduce performance But are required to get correct results Compiler can arrange code to avoid hazards and stalls Requires knowledge of the pipeline structure Page 58 29

30 Exceptions: One last thing When an exception occurs (e.g. overflow), we have to stop the instruction right away Otherwise we might overwrite a value in the registers To handle this Flush current and 2 previous instructions Need to add ID.Flush and EX.Flush lines (to zero out control line values) Save address where instruction occurred Add special Exception PC (EPC) register Jump to special Exception handling routine Add special case PC input address Page 59 Final Data Path 30

31 Improving Performance Try to avoid stalls! e.g., reorder these instructions: lw $t0, 0($t1) lw $t2, 4($t1) sw $t2, 0($t1) sw $t0, 4($t1) Page 61 Instruction-Level Parallelism (ILP) Pipelining: executing multiple instructions in parallel To increase ILP Deeper pipeline Less work per stage shorter clock cycle Multiple issue Replicate pipeline stages multiple pipelines Start multiple instructions per clock cycle CPI < 1, so use Instructions Per Cycle (IPC) E.g., 4GHz 4-way multiple-issue 16 BIPS, peak CPI = 0.25, peak IPC = 4 But dependencies reduce this in practice Page 62 31

32 SuperPipelining This is just creating longer pipelines. Remember that the speedup is directly related to the number of stages in the pipe. Big issue: How do you break up a datapath into smaller pieces, each with smaller and roughly equal latencies! Page 63 Superscalar Processing Could you do laundry faster if you had 3 washers and 3 dryers? Yes, if you could keep them moving smoothly Basic method: Put multiple copies of datapath into hardware Launch multiple instructions every clock cycle Get ready to have serious control and hazard issues! Biggest issue: need to schedule instructions quickly and efficiently and get them into the pipes, in such a way that hazards are minimized. Page 64 32

33 Dynamic Pipeline Scheduling This is like regular or super pipelining, except with very advanced techniques to make sure there are always instructions ready to fill in if a stall happens (don t want to waste a clock cycle.) Basically keeps a series of instruction buffers and schedule the instructions as needed to keep the pipe full and the program running without hazards. Branch prediction / speculative execution Can create quite a problem for accurate exception handling. Page 65 Current processors Nearly all have pipelining/superscalar design Compiler technology important Can t create efficient code for a pipelined or superscalar processor without the compiler thoroughly understanding how the pipelining, scheduling, forwarding and hazard detection all work for that specific processor. Page 66 33

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