EE 109 Unit 10 MIPS Instruction Set

Transcription

1 1 EE 109 Unit 10 MIPS Instruction Set

2 MIPS INSTRUCTION OVERVIEW 2

3 3 Instruction Set Architecture (ISA) Defines the software interface of the processor and memory system Instruction set is the vocabulary the HW can understand and the SW is composed with 2 approaches CISC = Complex instruction set computer Large, rich vocabulary More work per instruction but slower HW RISC = Reduced instruction set computer Small, basic, but sufficient vocabulary Less work per instruction but faster HW

4 4 MIPS Processor and Bus Interface The MIPS processor can execute software instructions that will cause it to: Load (Read) and Store (Write) data to and from memory or I/O devices Perform arithmetic and logic operations (add, sub, and, etc.) Make decisions to move around in the code (loops, ifs, call a function, etc.) MIPS Processor out op. ALU ADD, SUB, AND, OR (32-bits ALU) in1 in2 PC $0-$31 (32-bits each) Addr (32-bits) Data (32-bits) Control Memory 0 instruc data

5 5 Which Instructions In this class we'll focus on assembly to do the following tasks (shown with the corresponding MIPS assembly mnemonics) Load variables (data) from memory (or I/O) [LW,LH,LB] Perform arithmetic, logical, and shift instructions in the CPU [ADD,SUB,AND,OR,SLL,SRL,SRA] Store variables (data) back to memory after computation is complete [SW, SH, SB] Compare data [SLT] "Branch" to other code (to implement if and loops) [BEQ,BNE,J] Call subroutines/functions [JAL, JR]

6 6 MIPS ISA RISC-style 32-bit internal / 32-bit external data size Registers and ALU are 32-bits wide Memory bus is logically 32-bits wide (though may be physically wider) Registers 32 General Purpose Registers (GPR s) For integer and address values A few are used for specific tasks/values Fixed size instructions All instructions encoded as a single 32-bit word Three operand instruction format (dest, src1, src2) Load/store architecture (all data operands must be in registers and thus loaded from and stored to memory explicitly)

7 7 MIPS GPR s Assembler Name Reg. Number Description $zero $0 Constant 0 value $at $1 Assembler temporary $v0-$v1 $2-$3 Procedure return values or expression evaluation $a0-$a3 $4-$7 Arguments/parameters $t0-$t7 $8-$15 Temporaries $s0-$s7 $16-$23 Saved Temporaries $t8-$t9 $24-$25 Temporaries $k0-$k1 $26-$27 Reserved for OS kernel $gp $28 Global Pointer (Global and static variables/data) $sp $29 Stack Pointer $fp $30 Frame Pointer $ra $31 Return address for current procedure Avoid using the yellow (highlighted) registers for anything other than its stated use

8 8 MIPS Programmer-Visible Registers General Purpose Registers (GPR s) Hold data operands or addresses (pointers) to data stored in memory Special Purpose Registers PC: Program Counter (32-bits) Holds the address of the next instruction to be fetched from memory & executed HI: Hi-Half Reg. (32-bits) For MUL, holds 32 MSB s of result. For DIV, holds 32-bit remainder LO: Lo-Half Reg. (32-bits) For MUL, holds 32 LSB s of result. For DIV, holds 32-bit quotient PC: GPR s $0 - $31 32-bits Recall multiplying two 32-bit numbers yields a 64-bit result HI: LO: MIPS Core Special Purpose Registers

9 9 R=Register Type: Performing Arithmetic, Logic, and Shift Operations IMPORTANT R-TYPE INSTRUCTIONS

10 10 R-Type Arithmetic/Logic Instructions C operator Assembly Notes + ADD $d, $s, $t d=destination, s = src1, t = src2 - SUB $d, $s, $t Order: $s $t. SUBU for unsigned * MUL $d, $s, $t If multiply won t overflow 32-bit result & AND $d, $s, $t OR $d, $s, $t ^ XO$ $d, $s, $t ~( ) NOR $d, $s, $t Can be used for bitwise-not (~) << SLL $d, $s, shamt SLLV $d, $s, $t >> (signed) SRA $d, $s, shamt SRAV $d, $s, $t >> (unsigned) SRL $d, $s, shamt SRLV $d, $s, $t <, >, <=, >= SLT $d, $s, $t SLTU $d, $s, $t * MULT $s, $t MULTU $s, $t / DIV $s, $t DIVU $s, $t Shifts $s left by shamt (shift amount) or $t bits Shifts $s right by shamt or $t bits replicating sign bit to maintain sign Shifts $s left by shamt or $t bits shifting in 0 s Comparison. Order: $s $t. Sets $d=1 if $s < $t, $d=0 otherwise Result in HI/LO. Use mfhi and mflo instruction to move results $[s] / $[t]. Remainder in HI, quotient in LO

11 11 R-Type Instructions To perform arithmetic or logic operations in many processors (MIPS included) a copy of the operand MUST be loaded into a register first Consider the following operations F = X + Y Z G = F Z Complete the assembly code to perform these operations Remember to load/store your operands to/from registers C Code F = X + Y Z; G = F Z; MIPS Assembly LOAD* $4, X # Get X from mem. LOAD $5, Y # Get Y from mem. LOAD $6, Z # Get Z from mem. ADD $7,$4,$5 # Tmp = X+Y SUB $7,$7,$6 # Tmp = Tmp - Z STORE $7, F # Store to F in mem OR $8,$7,$6 # Tmp2 = F Z STORE $8, G # Store to G in mem * LOAD/STORE are not actual instructions. We will learn the actual syntax soon. out op. ALU ADD, SUB, AND, OR (32-bits ALU) in1 in2 $4 $5 $6 $7 $8 MIPS Processor $0-$31 (32-bits each) PC Addr (32-bits) Data (32-bits) Control Load Load Store X (e.g. 12) Y (e.g. 7) Z (e.g. 3) F G Memory

12 12 R-Type Instructions Format 6-bits 5-bits 5-bits 5-bits 5-bits 6-bits opcode rs (src1) rt (src2) rd (dest) shamt function rs, rt, rd are 5-bit fields for register numbers shamt = shift amount and is used for shift instructions indicating # of places to shift bits opcode and func identify actual operation (e.g. ADD, SUB) Example: ADD $5, $24, $17 opcode rs rt rd shamt func Arith. Inst. $24 $17 $5 unused ADD

13 13 Logical Operations Should already be familiar with (sick of) these! Logic operations are usually performed on a pair of bits X1 X2 AND X1 X2 OR X1 X2 XOR X1 NOT AND Output is true if both inputs are true 0 AND x = 0 1 AND x = x x AND x = x OR Output is true if any input is true 0 OR x = x 1 OR x = 1 x OR x = x XOR Output is true if exactly one input is true 0 XOR x = x 1 XOR x = NOT x x XOR x = 0 NOT Output is inverse of input

14 14 Logical Operations Logic operations on numbers means performing the operation on each pair of bits Initial Conditions: $1 = 0xF0, $2 = 0x3C 1 AND $2,$1,$2 R[2] = 0x30 0xF0 AND 0x3C 0x AND OR $2,$1,$2 R[2] = 0xFC 0xF0 OR 0x3C 0xFC OR XOR $2,$1,$2 R[2] = 0xCC 0xF0 XOR 0x3C 0xCC XOR Tip: Unless you're very good w/ hex, convert to binary then perform these operations!

15 15 Logical Operations Logic operations on numbers means performing the operation on each pair of bits Initial Conditions: $1= 0xF0, $2 = 0x3C 4 NOR $2,$1,$2 R[2] = 0x03 0xF0 NOR 0x3C 0x NOR Bitwise NOT operation can be performed by NOR ing register with itself NOR $2,$1,$1 R[2] = 0x0F 0xF0 NOR 0xF0 0x0F NOR

16 16 Shift Operations Shifts data bits either left or right Bits shifted out and dropped on one side Usually (but not always) 0 s are shifted in on the other side In addition to just moving bits around, shifting is a fast way to multiply or divide a number by powers of 2 (see next slides) 2 kinds of shifts Logical shifts (used for unsigned numbers) Arithmetic shifts (used for signed numbers) Right Shift by 2 bits: Original Data Left Shift by 2 bits: Original Data 0 s shifted in 0 s shifted in Shifted by 2 bits Shifted by 2 bits

17 17 Logical Shift 0 s shifted in Only use for operations on unsigned data Right shift by n-bits = Dividing by 2 n Left shift by n-bits = Multiplying by 2 n 0 x C = +12 Logical Right Shift by 2 bits: Logical Left Shift by 3 bits: 0 s shifted in 0 s shifted in = = x x

18 18 Arithmetic Shift Use for operations on signed data Arithmetic Right Shift replicate MSB Right shift by n-bits = Dividing by 2 n Arithmetic Left Shift shifts in 0 s Left shift by n-bits = Multiplying by 2 n 0 x F F F F F F F C = -4 Arithmetic Right Shift by 2 bits: MSB replicated and shifted in x F F F F F F F F Notice if we shifted in 0 s (like a logical right shift) our result would be a positive number and the division wouldn t work Arithmetic Left Shift by 2 bits: 0 s shifted in = = x F F F F F F F 0 Notice there is no difference between an arithmetic and logical left shift. We always shift in 0 s.

19 19 Logical Shift vs. Arithmetic Shift Logical Shift Use for unsigned or nonnumeric data Will always shift in 0 s whether it be a left or right shift Arithmetic Shift Use for signed data Left shift will shift in 0 s Right shift will sign extend (replicate the sign bit) rather than shift in 0 s If negative number stays negative by shifting in 1 s If positive stays positive by shifting in 0 s 0 0 Left shift Left shift 0 Right shift Copies of MSB are shifted in Right shift

20 20 MIPS Logical Shift Instructions SRL instruction Shift Right Logical SLL instruction Shift Left Logical Format: SxL rd, rt, shamt (shamt = shift amount and is a constant; e.g. x << 7) SxLV rd, rt, rs (rs is the shift amount and is variable; e.g. x << y) Notes: shamt limited to a 5-bit value (0-31) SxLV shifts data in rt by number of places specified in rs Examples SRL $5, $12, 7 // Shifts data in reg. $12 right by 7 places SLLV $5, $12, $20 // If $20=5, shift data in $12 left by 5 places opcode rs rt rd shamt func Arith. Inst. unused $12 $5 7 SRL Arith. Inst. $20 $12 $5 unused SLLV

21 21 MIPS Arithmetic Shift Instruction SRA instruction Shift Right Arithmetic No arithmetic left shift (use SLL for arithmetic left shift) Format: SRA rd, rt, shamt SRAV rd, rt, rs Notes: shamt limited to a 5-bit value (0-31) SRAV shifts data in rt by number of places specified in rs Examples SRA $5, $12, 7 SRAV $5, $12, $20 opcode rs rt rd shamt func Arith. Inst. unused $12 $5 7 SRA Arith. Inst. $20 $12 $5 unused SRAV

22 22 Immediate Operands Most ALU instructions also have an immediate form to be used when one operand is a constant value Syntax: ADDI Rs, Rt, imm Because immediates are limited to 16-bits, they must be extended to a full 32- bits when used the by the processor Arithmetic instructions always sign-extend to a full 32-bits even for unsigned instructions (addiu) Logical instructions always zero-extend to a full 32-bits Examples: ADDI $4, $5, -1 // R[4] = R[5] + 0xFFFFFFFF ORI $10, $14, -4 // R[10] = R[14] 0x0000FFFC Arithmetic ADDI ADDIU SLTI SLTIU Logical ANDI ORI XORI Note: SUBI is unnecessary since we can use ADDI with a negative immediate value

23 23 Set If Less-Than SLT $rd, $rs, $rt Compares $rs value with $rt value and stores Boolean (1 = true, 0 = false) value into $rd C code equivalent: bool rd = (rs < rt); $rd can only be 0x or 0x after execution Assumes signed integer comparison SLTI $rd, $rs, immediate Same as above but now 2 nd source is a constant SLTU $rd, $rs, $rt Same as SLT but interprets values as unsigned Initial Conditions: $1= 0xffffffff, $2 = 0x $3 = 0x000000ff SLT $4, $1, $2 $4 = 0x SLT $4, $3, $3 $4 = 0x SLT $4, $3, $1 $4 = 0x SLTI $4, $2, 35 $4 = 0x SLTU $4, $1, $2 $4 = 0x

24 24 Loading (Reading) and Storing (Writing) Data From and To Memory DATA TRANSFER AND MEMORY ACCESS INSTRUCTIONS

25 25 Physical Memory Organization Physical view of memory as large 2-D array of bytes (8K rows by 1KB columns) per chip (and several chips) Address is broken into fields of bits that are used to identify where in the array the desired 32-bit word is Processor always accesses memory chunks the size of the data bus, selecting only the desired bytes as specified by the instruction Proc. A D 0x Physical View of Memory 0x x x Assume each unit is a word 0x0404 = Rank/Bank Row Col XX Sample Address Breakdown

26 26 MIPS Supported Data Sizes Integer 3 Sizes Defined Byte (B) 8-bits Halfword (H) 16-bits = 2 bytes Word (W) 32-bits = 4 bytes Floating Point 3 Sizes Defined Single (S) 32-bits = 4 bytes Double (D) 64-bits = 8 bytes (For a 32-bit data bus, a double would be accessed from memory in 2 reads)

27 27 MIPS Memory Organization We can logically picture memory in the units (sizes) that we actually access them Most processors are byteaddressable Every byte (8-bits) has a unique address 32-bit address bus => 4 GB address space However, 32-bit logical data bus allows us to access 4-bytes of data at a time Logical view of memory arranged in rows of 4-bytes Still with separate addresses for each byte int x,y=5;z=8; x = y+z; Proc. A D F8 13 5A Mem. 0x x x Logical Byte-Oriented View of Mem. 8E 7C AD F A 0x x x Logical Word-Oriented View Recall variables live in memory & need to be loaded into the processor to be used

28 28 Memory & Data Size Little-endian memory can be thought of as right justified Always provide the LS-Byte address of the desired data Size is explicitly defined by the instruction used Memory Access Rules Registers: Halfword or Word access must start on an address that is a multiple of that data size (i.e. half = multiple of 2, word = multiple of 4) Byte Half 31 0 Word (Assume start address = N) LB Used to load a 1- byte var. (char) LH LW Used to load a 4- byte variable (int) N+3 N+2 N+1 Byte operations only access the byte at the specified address N+3 N+2 N+1 Halfword operations access the 2-bytes starting at the specified address N+3 N+2 N+1 Memory Word operations access the 4-bytes starting at the specified address N N N

29 29 Memory Read Instructions (Signed) GPR Sign Extend If address = 0x02 Reg. = 0x Byte LB (Load Byte) Provide address of desired byte Memory A 13 F8 7C Sign Extend Half If address = 0x00 Reg. = 0xFFFFF87C LH (Load Half) Provide address of starting byte A 13 F8 7C Word If address = 0x00 Reg. = 0x5A13F87C LW (Load Word) Provide address of starting byte A 13 F8 7C

30 30 Memory Read Instructions (Unsigned) GPR Zero Extend If address = 0x01 Reg. = 0x000000F8 Byte LBU (Load Byte) Provide address of desired byte Memory A 13 F8 7C Zero Extend Half If address = 0x00 Reg. = 0x0000F87C LHU (Load Half) Provide address of starting byte A 13 F8 7C Word If address = 0x00 Reg. = 0x5A13F87C LW (Load Word) Provide address of starting byte A 13 F8 7C

31 31 Memory Write Instructions GPR Byte Reg. = 0x SB (Store Byte) Provide address of desired byte Memory A 78 F8 7C if address = 0x Half Reg. = 0x SH (Store Half) Provide address of starting byte F8 7C if address = 0x Word Reg. = 0x SW (Store Word) Provide address of starting byte if address = 0x00

32 32 MIPS Memory Alignment Limitations Bytes can start at any address Halfwords must start on an even address Words must start on an address that is a multiple of 4 Examples: A18C good (multiple of 4) FFE6 good (even) A18E invalid (non-multiple of 4) FFE5 invalid (odd) Addr Data Control Addr Data Control EA 7C EA 52 7C C1 29 4B F8 13 5A Valid Accesses C1 29 4B BD CF 49 F8 13 5A Invalid Accesses 00FFE4 00A18C 00FFE4 00A18C

33 33 Load Format (LW,LH,LB) Syntax: LW $rt, offset($rs) $rt = Destination register offset($rs) = Address of desired data Operation: $rt = Mem[ offset + $rs ] offset limited to 16-bit signed number Examples LW $2, 0x40($3) // $2 = 0x5A12C5B7 LBU $2, -1($4) // $2 = 0x000000F8 LH $2, 0xFFFC($4) // $2 = 0xFFFF97CD $2 old val. F8BE97CD 0x $ FE 0x $ C Registers 5A12C5B7 Memory 0x Address

34 34 More LOAD Examples Examples LB $2,0x45($3) // $2 = 0xFFFFFF82 LH $2,-6($4) // $2 = 0x LHU $2, -2($4) // $2 = 0x0000F8BE $2 old val. F8BE97CD 0x $ FE 0x $ C Registers 5A12C5B7 Memory 0x Address

35 35 Store Format (SW,SH,SB) SW $rt, offset($rs) $rt = Source register offset($rs) = Address to store data Operation: Mem[ offset + $rs ] = $rt offset limited to 16-bit signed number Examples SW $2, 0x40($3) SB $2, -5($4) SH $2, 0xFFFE($4) $ AB 89AB97CD 0x $ AB4982FE 0x $ C Registers AB Memory 0x Address

36 36 Loading an Immediate If immediate (constant) 16-bits or less Use ORI or ADDI instruction with $0 register Examples ADDI $2, $0, 1 // $2 = = 1 ORI $2, $0, 0xF110 // $2 = 0 0xF110 = 0xF110 If immediate more than 16-bits Immediates limited to 16-bits so we must load constant with a 2 instruction sequence using the special LUI (Load Upper Immediate) instruction To load $2 with 0x LUI ORI $2,0x1234 $2,$2,0x5678 $2 $ OR LUI ORI

37 37 I-Type Instructions I-Type (Immediate) Format 6-bits 5-bits 5-bits 16-bits opcode rs (src1) rt (src/dst) immediate rs, rt are 5-bit fields for register numbers I = Immediate is a 16-bit constant opcode identifies actual operation Example: ADDI $5, $24, 1 LW $5, -8($3) LW is explained in the next section but is an example of an instruction using the I-type format opcode rs rt ADDI $24 $ LW $3 $5 immediate

38 38 Translating To Machine Code 32-bit Fixed Size Instructions broken into 3 types (R-, I-, and J-) based on opcode R-Type Arithmetic/Logic instructions 3 register operands or shift amount I-Type Use for data transfer, branches, etc. 2 registers + 16-bit const. J-Type 26-bit jump address We'll cover this later R-Type I-Type J-Type 6-bits opcode 6-bits opcode 6-bits opcode 5-bits rs (src1) 5-bits rs (src1) 5-bits rt (src2) 5-bits rt (src/dst) 5-bits rd (dest) 26-bits Jump address 5-bits shamt 16-bits immediate 6-bits function add $5,$7,$ lw $18, -4($3) j 0x Each type uses portions of the instruction to "code" certain aspects of the instruction. But they all start with an opcode that helps determine which type will be used.

39 39 "Be the Compiler" COMPILING HIGH-LEVEL CODE

40 40 Tips for Translating to Assembly We will now translate C code to assembly A few things to remember: Data variables live in memory Data must be brought into registers before being processed You must have an address/pointer in a register to load/store data to/from memory Generally, you will need 4 steps to translate C to assembly: Setup a pointer in a register (LUI + ORI) Load data from memory to a register (LW, LH, LB) Process data (ADD, SUB, AND, OR, etc.) Store data back to memory (SW, SH, SB)

41 41 Translating HLL to Assembly HLL variables are simply locations in memory A variable name really translates to an address in C assembly operator Assembly Notes int x,y,z; x = y + z; LUI $8, 0x1000 ORI $8, $8, 0x0004 LW $9, 4($8) LW $10, 8($8) ADD $9,$9,$10 SW $9, 0($8) Assume 0x & 0x & 0x C char a[100]; a[1]--; LUI $8, 0x1000 ORI $8, $8, 0x000C LB $9, 1($8) ADDI $9,$9,-1 SB $9,1($8) Assume array a 0x C

42 42 Translating HLL to Assembly C operator Assembly Notes int dat[4],x; x = dat[0]; x += dat[1]; LUI $8, 0x1000 ORI $8, $8, 0x0010 LW $9, 0($8) LW $10, 4($8) ADD $9,$9,$10 SW $9, 16($8) Assume 0x & 0x unsigned int y; short z; y = y / 4; z = z << 3; LUI $8, 0x1000 ORI $8, $8, 0x0010 LW $9, 0($8) SRL $9, $9, 2 SW $9, 0($8) LH $9, 4($8) SLL $9, $9, 3 SH $9, 4($8) Assume 0x & 0x

43 43 Directives Pseudo-instructions ASSEMBLERS

44 44 Writing Assembly Code written at the assembly level needs some additional help for specifying certain things Global variables Where code and data should be placed in memory Easy ways to reference memory locations To help us do this assemblers provide some additional statements that we can use

45 45 Our Simulator - MARS Download at:

46 46 Assembler Syntax In MARS and most assemblers each line of the assembly program may be one of three possible options Comment Instruction / Pseudo-instruction Assembler Directive

47 47 Comments In MARS an entire line can be marked as a comment by starting it with a pound (#) character: Example: # This line will be ignored by the assembler LW $2,8($3) ADDI $2,$2,1...

48 48 Instructions In MARS each instruction is written on a separate line and has the following syntax: (Label:) Instruc. Op. Operands Comment Example: START: ADD $2,$3,$4 # R[2]=R[3] + R[4] Notes: Label is optional and is a text identifier for the address where the instruction is placed in memory. (These are normally used to identify the target of a branch or jump instruction.) In MARS, a comment can be inserted after an instruction by using a # sign A label can be on a line by itself in which case it refers to the address of the first instruction listed after it

49 49 Labels and Instructions The optional label in front of an instruction evaluates to the address where the instruction or data starts in memory and can be used in other instructions.text START: LW $4,8($10) L1: ADDI $4,$4,-1 BNE $4,$0,L1 J START Assembly Source File LW ADDI BNE J 0x = START 0x = L1 0x x40000C Note: The BNE instruc. causes the program to branch (jump) to the instruction at the specified address if the two operands are Not Equal. The J(ump) instruction causes program execution to jump to the specified label (address). Assembler finds what address each instruction starts at.text LW $4,8($10) ADDI $4,$4,-1 BNE $4,$0,0x J 0x and replaces the labels with their corresponding address

50 50 Assembler Directives Similar to pre-processor statements (#include, #define, etc.) and global variable declarations in C/C++ Text and data segments Reserving & initializing global variables and constants Compiler and linker status Direct the assembler in how to assemble the actual instructions and how to initialize memory when the program is loaded

51 51 An Example This is output from an actual MIPS gcc/g++ compiler Actual instructions are at the bottom (addiu, srl, etc.) Directives are the things starting with. Labels are names ending with : Let's learn about some of the directives x:.word 5.globl nums.section.bss.align 2.type nums, 40 nums:.space 40.text.align 2.globl _Z6calleei $LFB2:.ent _Z6calleei _Z6calleei:.frame $sp,0,$31.mask 0x ,0.fmask 0x ,0 addiu $2,$4,3 srl $3,$2,31 addu $2,$2,$3

52 52 Text and Static Data Segments.text directive indicates the following instructions should be placed in the program area of memory.data directive indicates the following data declarations will be placed in the data memory segment I/O Space Stack Dynamic Data Segment Static Data Segment Text Segment Unused 0xFFFF_FFFC 0x8000_0000 0x7FFF_FFFC 0x1000_8000 0x1000_0000 0x0040_0000 0x0000_0000

53 53 Static Data Directives Fills memory with specified data when program is loaded Format: (Label:).type_id val_0,val_1,,val_n type_id = {.byte,.half,.word,.float,.double} Each value in the comma separated list will be stored using the indicated size Example: myval:.word 1, 2, 0x0003 Each value 1, 2, 3 is stored as a word (i.e. 32-bits) Label myval evaluates to the start address of the first word (i.e. of the value 1)

54 54 More Static Data Directives Can be used to initialize ASCII strings Format: (Label:).ascii string (Label:).asciiz string.asciiz adds a null-termination character (0) at the end of the string while.ascii does not Example: myval:.asciiz Hello world\n C-strings are just character arrays terminated with a null character ('\0' ASCII = 00 decimal) Each character stored as a byte (including '\n' = Line Feed) Label myval evaluates to the start address of the first byte of the string

55 55 Reserving Memory Reserves space in memory but leaves the contents unchanged Format: (Label:).space num_bytes.data dat1:.word 0x array:.space 4 dat2:.word 0xFEDCBA98 Skipped x C FE DC BA x = dat2 0x = array x = dat1

56 56 Alignment Directive Used to skip to the next, correctly-aligned address for the given data size Format:.align 0,1,2, or 3 0 = byte-, 1 = half-, 2 = word-, 3 = double-alignment.data dat1:.byte 1, 2, 3.align 1 dat2:.half 0x4567.align 2 dat3:.word 0x89ABCDEF Note: The number after.align is not how many bytes to skip, it indicates what type of data will come next and thus the size to be aligned Skipped Skipped x C 89 AB CD EF x = dat3 0x = dat x = dat1

57 57.data example Examples.data C1:.byte 0xFE,0x05 MSG:.asciiz SC\n DAT:.half 1,2.align 2 VAR:.word 0x Skipped because a word must begin on a 4-byte boundary A FE 0x C 0x x x C1 evaluates to 0x MSG evaluates to 0x (Note: \n = Line Feed char. = 0x0A) DAT evaluates to 0x VAR evaluates to 0x C

58 58 C/C++ and Directives Directives are used to initialize or reserve space for global variables in C short int count = 7; char message[16]; int table[8] = {0,1,2,3,4,5,6,7}; void main() {... }.data count:.half 7 message:.space 16.align 2 table:.word 0,1,2,3,4,5,6,7.text.globl main main:... C/C++ style global declarations Assembly equivalent

59 59 Summary & Notes Assembler Directives: Tell the assembler how to build the program memory image Where instructions and data should be placed in memory when the program is loaded How to initialize certain global variables Recall, a compiler/assembler simply outputs a memory IMAGE of the program. It must then be loaded into memory by the OS to be executed. Key: Directives are NOT instructions! They are used by the assembler to create the memory image and then removed The MIPS processor never sees these directives!

60 60 Directives in the Software Flow High Level Language Description int n = 0xC259; void main(){ if (x > 0) x = x + y - z; a = b*x; Compiler.data MOVE.W X,D0 n:.word CMPI.W 0xC259 #0,D0.text BLE SKIP SLT ADD $4,$2,$0 Y,D0 BNE SUB SKIP Z,D0 SKIP MUL SKIP: MUL Assembler Directives are used to create the object code (executable) image Assembler PC Program Executing SLT.c/.cpp files the processor NEVER sees/executes these directives Loader / OS Assembly (.asm/.s files) Object/Machine Code (.o files) Linker BNE Executable Binary Image

61 61 Pseudo-instructions Macros translated by the assembler to instructions actually supported by the HW Simplifies writing code in assembly Example LI (Load-immediate) pseudoinstruction translated by assembler to 2 instruction sequence (LUI & ORI)... li... $2, 0x lui $2, 0x1234 ori $2, $2, 0x With pseudo-instruction After assembler

62 62 Pseudo-instructions Pseudo-instruction NOT Rd,Rs NEG Rd,Rs Actual Assembly NOR Rd,Rs,$0 SUB Rd,$0,Rs LI Rt, immed. # Load Immediate LUI Rt, {immediate[31:16], 16 b0} ORI Rt, {16 b0, immediate[15:0]} LA Rt, label # Load Address LUI Rt, {immediate[31:16], 16 b0} ORI Rt, {16 b0, immediate[15:0]} BLT Rs,Rt,Label SLT $1,Rs,Rt BNE $1,$0,Label Note: Pseudoinstructions are assembler-dependent. See MARS Help for more details.

63 63 Support for Pseudo-instructions Pseudo-instructions often expand to several instructions and there is a need for usage of a temporary register Assembler reserves register $1 In the assembler, $1 = $at (assembler temp.) You can use $1 but it will be overwritten when you use certain pseudo-instructions

64 64 Coding Exercise with MARS int x = 7, y = 5, z = 3; z = x * z + (x y++) # #DEFINE MASK 0xe0; # PORTD &= ~(MASK) # PORTD = ((x << 5) & MASK);

65 65 What are the common features of all processor instruction sets? INSTRUCTION SET ARCHITECTURE

66 66 Components of an ISA 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support SUBtract instruc. vs. NEGate + ADD instrucs. 3. Length and format of instructions How is the operation and operands represented with 1 s and 0 s 4. Registers accessible to the instructions Faster than accessing data from memory 5. Addressing Modes How instructions can specify location of data operands

67 67 Historic Progression of Data Size & Registers Processor Year Trans. Count Data Size GPRs K K /486 85/ K/1.1 8M 32 8 Pentium M 32 >8 Pentium M 32 >= 128 Core 2 Duo M 64 >= core Core i B 64 >= 128 MIPS 1999 var

68 68 General Instruction Format Issues Instructions must specify three things: Operation (OpCode) Source operands Usually 2 source operands (e.g. X+Y) Destination Location Example: ADD $8, $9, $10 ($8 = $9 + $10 where $ = Register) Binary (machine-code) representation broken into fields of bits for each part OpCode Src. 1 Src. 2 Dest. Shift Amount Function Arith. $9 $10 $8 Unused Add

69 69 Historical Instruction Formats Different instruction sets specify these differently 3 operand instruction set (MIPS, PPC, ARM) Similar to example on previous page Format: ADD DST, SRC1, SRC2 (DST = SRC1 + SRC2) 2 operand instructions (Intel / Motorola 68K) Second operand doubles as source and destination Format: ADD SRC1, S2/D (S2/D = SRC1 + S2/D) 1 operand instructions (Old Intel FP, Low-End Embedded) Implicit operand to every instruction usually known as the Accumulator (or ACC) register Format: ADD SRC1 (ACC = ACC + SRC1)

70 70 Historical Instruction Format Examples Consider the pros and cons of each format when performing the set of operations F = X + Y Z G = A + B Simple embedded computers often use single operand format Smaller data size (8-bit or 16-bit machines) means limited instruc. size Modern, high performance processors use 2- and 3-operand formats Single-Operand Two-Operand Three-Operand LOAD X MOVE F,X ADD F,X,Y ADD Y ADD F,Y SUB F,F,Z SUB Z SUB F,Z ADD G,A,B STORE F MOVE G,A LOAD A ADD G,B ADD B STORE G (+) Smaller size to encode each instruction (-) Higher instruction count to load and store ACC value Compromise of two extremes (+) More natural program style (+) Smaller instruction count (-) Larger size to encode each instruction

71 71 MIPS Instruction Format 3 Register operand format Most ALU instructions use 3 registers as their operands All operations are performed on entire 32- bits (no size distinction) Example: ADD $t0, $t1, $t2 Load/Store architecture Load (read) data values from memory into a register Perform operations on registers Store (write) data values back to memory Different load/store instructions for different operand sizes (i.e. byte, half, word) Load/Store Architecture Proc. Mem. 1.) Load operands to proc. registers Proc. Mem. 2.) Proc. Performs operation using register values Proc. Mem. 3.) Store results back to memory