ECE232: Hardware Organization and Design

Transcription

1 ECE232: Hardware Organization and Design Lecture 2: Hardware/Software Interface Adapted from Computer Organization and Design, Patterson & Hennessy, UCB

2 Overview Basic computer components How does a microprocessor view memory? Basic microprocessor components ALU, register file, registers Microprocessor instructions Logic operations (AND, OR, etc) Memory operations MIPs instruction format Control implemented as a series of instructions ECE232: MIPS Instructions-I 2

3 Computer Organization 5 classic components of any computer Processor (CPU) (active) Control ( brain ) Datapath Computer Memory (passive) (where programs, & data live when running) Devices Input Output Keyboard, Mouse Disk (where programs, & data live when not running) Display, Printer Fits in closely with datapath ECE232: MIPS Instructions-I 3

4 Program View of Memory Processor (CPU) Control Datapath Computer Memory Devices Input Output Memory viewed as a large, single -dimension array, with an address A memory address is an index into array The index points to a byte of memory - "Byte addressing" A 32-bit machine addresses memory by a 32-bit address Access bytes (8 bits), words (32 bits) or half-words ? 8 bits of data 8 bits of data 8 bits of data 8 bits of data 8 bits of data 8 bits of data 8 bits of data 8 bits of data ECE232: MIPS Instructions-I 4

5 Memory word addressing CPU Address Bus Memory Every word in memory has an address Today machines address memory as bytes, hence word addresses differ by 4 Memory[0], Memory[4], Memory[8], Word 0 (bytes 0 to 3) Word 1 (bytes 4 to 7) 0x x x x C 0x x x x C 0xfffffff4 0xfffffffc 0xfffffffc Called the address of a word Memory 4GB Max (Typically 512MB-2GB) ECE232: MIPS Instructions-I 5

6 Addressing words: Big or Small Endian Big Endian: address of most significant byte = word address (xx00 = Big End of word) IBM 360/370, Motorola 68k, MIPS, Sparc, HP PA Little Endian: address of least significant byte = word address (xx00 = Little End of word) Intel 80x86, DEC Vax, DEC Alpha little endian byte 0 msb lsb big endian byte 0 ECE232: MIPS Instructions-I 6

7 Registers Computer Processor (CPU) Control Memory Devices Input Datapath Registers Output Once a memory is fetched, the data must be placed somewhere in CPU Advantages of registers registers are faster than memory registers can hold variables and intermediate results memory traffic is reduced, so program runs faster code density improves (later) ECE232: MIPS Instructions-I 7

8 Registers code for A = B + C (This is not MIPS code, It is in English) load R1,B load R2,C add R3,R1,R2 store R3,A # R1 = B # R2 = C # R3 = R1+R2 # A = R3 Many current processors support 32 registers (MIPS) The more registers available, the fewer memory accesses will be necessary Registers can hold lots of intermediate values Instructions must include bits to specify which registers to operate on register address ECE232: MIPS Instructions-I 8

9 Instruction Set Architecture (ISA) Application (FireFox) Software Hardware Compiler Assembler Processor Operating System Memory (Unix; Windows) Datapath & Control Digital Design Circuit Design transistors, IC layout I/O system Instruction Set Architecture Key Idea: abstraction hide unnecessary implementation details helps us cope with enormous complexity of real systems ECE232: MIPS Instructions-I 9

10 The MIPS Instruction Set Used as the example throughout the book Stanford MIPS commercialized by MIPS Technologies ( Large share of embedded core market Applications in consumer electronics, network/storage equipment, cameras, printers, Typical of many modern ISAs See MIPS Reference Data tear-out card, and Appendices B and E ECE232: MIPS Instructions-I 10

11 Arithmetic Operations Add and subtract, three operands Two sources and one destination add a, b, c # a gets b + c All arithmetic operations have this form Design Principle 1: Simplicity favors regularity Regularity makes implementation simpler Simplicity enables higher performance at lower cost ECE232: MIPS Instructions-I 11

12 Arithmetic Example C or Java code: f = (g + h) - (i + j); Compiled MIPS code: add t0, g, h # temp t0 = g + h add t1, i, j # temp t1 = i + j sub f, t0, t1 # f = t0 - t1 ECE232: MIPS Instructions-I 12

13 Register Operands Arithmetic instructions use register operands MIPS has a bit register file Use for frequently accessed data Numbered 0 to bit data called a word Assembler names $t0, $t1,, $t9 for temporary values $s0, $s1,, $s7 for saved variables Design Principle 2: Smaller is faster c.f. main memory: millions of locations ECE232: MIPS Instructions-I 13

14 Register Operand Example C or Java code: f = (g + h) - (i + j); f,, j in $s0,, $s4 Compiled MIPS code: add $t0, $s1, $s2 add $t1, $s3, $s4 sub $s0, $t0, $t1 ECE232: MIPS Instructions-I 14

15 Simplified Datapath Two register fetches in one cycle Load from memory Store to memory Registers A L U Data Memory From Register for SW To register for LW ECE232: MIPS Instructions-I 15

16 Memory Operands Main memory used for composite data Arrays, structures, dynamic data To apply arithmetic operations Load values from memory into registers Store result from register to memory Memory is byte addressed Each address identifies an 8-bit byte Words are aligned in memory Address must be a multiple of 4 MIPS is Big Endian Most-significant byte at least address of a word c.f. Little Endian: least-significant byte at least address ECE232: MIPS Instructions-I 16

17 Memory Operand Example 1 C code: g = h + A[8]; g in $s1, h in $s2, base address of A in $s3 Compiled MIPS code: Index 8 requires offset of 32 4 bytes per word lw $t0, 32($s3) # load word add $s1, $s2, $t0 offset base register ECE232: MIPS Instructions-I 17

18 Memory Operand Example 2 C code: A[12] = h + A[8]; h in $s2, base address of A in $s3 Compiled MIPS code: Index 8 requires offset of 32 lw $t0, 32($s3) # load word add $t0, $s2, $t0 sw $t0, 48($s3) # store word ECE232: MIPS Instructions-I 18

19 Registers vs. Memory Registers in a register file are faster to access than memory Operating on memory data requires loads and stores More instructions to be executed Compiler must use registers for variables as much as possible Only spill to memory for less frequently used variables Register optimization is important! Registers are a fixed resources ECE232: MIPS Instructions-I 19

20 Immediate Operands Constant data specified in an instruction addi $s3, $s3, 4 No subtract immediate instruction Just use a negative constant addi $s2, $s1, -1 Design Principle 3: Make the common case fast Small constants are common Immediate operand avoids a load instruction ECE232: MIPS Instructions-I 20

21 The Constant Zero MIPS register 0 ($zero) is the constant 0 Cannot be overwritten Zero is used a lot for arithmetic operations Useful for common operations E.g., move between registers add $t2, $s1, $zero ECE232: MIPS Instructions-I 21

22 MIPS Registers Fast access to program data Register R0/$0/$zero: hardwired to constant zero Register names: $0-$31 or R0-R31 Specialized names based on usage convention $zero ($0) - always zero $s0-$s7 ($16-$23) - saved registers $t0-$t7 ($8-$15) - temporary registers $sp - stack pointer Other special-purpose registers ECE232: MIPS Instructions-I 22

23 MIPS Registers and Usage Name Register number Usage $zero 0 the constant value 0 $at 1 reserved for assembler $v0-$v1 2-3 values for results and expression evaluation $a0-$a3 4-7 arguments $t0-$t temporary registers $s0-$s saved registers $t8-$t more temporary registers $k0-$k reserved for Operating System kernel $gp 28 global pointer $sp 29 stack pointer $fp 30 frame pointer $ra 31 return address ECE232: MIPS Instructions-I 23

24 Summary Basic microprocessor includes a register file, an ALU, and control circuitry Microprocessors interact with memory Memory access is slow and (when possible) should be avoided Load and store instructions used to access memory Microprocessors operate using primitive instructions Logic operations Arithmetic operations Load and stores More to come Next time: More instructions, instruction implementation ECE232: MIPS Instructions-I 24