Chapter 11. Instruction Sets: Addressing Modes and Formats. Yonsei University

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1 Chapter 11 Instruction Sets: Addressing Modes and Formats

2 Contents Addressing Pentium and PowerPC Addressing Modes Instruction Formats Pentium and PowerPC Instruction Formats 11-2

3 Common Addressing Techniques Addressing Immediate Direct Register Register indirect Displacement Stack 11-3

4 Addressing Modes Addressing Notation A : contents of an address field in the instruction R : contents of an address field in the instruction that refers to a register EA : actual(effective) address of the location containing the referenced operand (X) : contents of location X 11-4

5 Basic Addressing Modes Addressing Two comments needed Virtually all computer architectures providing more than one of these addressing modes The value of the mode field determines which address Interpretation of the effective address(ea) EA will be either a main memory address or a register 11-5

6 Immediate Addressing Addressing Operand is part of instruction Operand = address field used to define and use constants or set initial values of variables e.g. ADD 5 Add 5 to contents of accumulator 5 is operand No memory reference to fetch data Fast Instruction Limited range Opcode Operand OPERAND = A 11-6

7 Direct Addressing Addressing Address field contains address of operand Effective address (EA) = address field (A) e.g. ADD A Add contents of cell A to accumulator Look in memory at address A for operand Single memory reference to access data No additional calculations to work out effective address Limited address space 11-7

8 Direct Addressing Diagram Addressing Opcode Instruction Address A Memory Operand 11-8

9 Indirect Addressing Addressing Memory cell pointed to by address field contains the address of (pointer to) the operand EA = (A) Look in A, find address (A) and look there for operand e.g. ADD (A) Add contents of cell pointed to by contents of A to accumulator 11-9

10 Indirect Addressing Addressing Large address space Advantage : 2 n where n = word length May be nested, multilevel, cascaded e.g. EA = (((A))) Draw the diagram yourself Disadvantage : two memory accesses to find operand One to get its address / a second to get its value Hence slower 11-10

11 Indirect Addressing Diagram Addressing Opcode Instruction Address A Memory Pointer to operand Operand 11-11

12 Register Addressing Addressing Operand is held in register named in address field EA = R Limited number of registers Advantages Very small address field needed Shorter instructions Faster instruction fetch No memory access Very fast execution 11-12

13 Register Addressing Disadvantage : Very limited address space Heavily used register addressing in an instruction - heavily used CPU registers Multiple registers helps performance Requires good assembly programming or compiler writing N.B. C programming register int a; c.f. Direct addressing Addressing 11-13

14 Register Addressing Diagram Addressing Opcode Instruction Register Address R Registers Operand 11-14

15 Register Indirect Addressing Addressing c.f. indirect addressing EA = (R) Operand is in memory cell pointed to by contents of register R Large address space (2 n ) The address space limitation of the address field is overcome by having that field refer to a word-length location containing an address One fewer memory access than indirect addressing 11-15

16 Register Indirect Addressing Diagram Addressing Opcode Instruction Register Address R Memory Registers Pointer to Operand Operand 11-16

17 Displacement Addressing Addressing EA = A + (R) Address field hold two values At least one of two is explicit A = base value R = register that holds displacement Or vice versa Three of the most common uses of displacement addressing Relative addressing Base-register addressing Indexing 11-17

18 Displacement Addressing Diagram Addressing Opcode Register R Instruction Address A Memory Registers Pointer to Operand + Operand 11-18

19 Relative Addressing Addressing A version of displacement addressing R = Program counter (PC) The implicitly referenced register EA = A + (PC) i.e. get operand from A cells from current location pointed to by PC c.f locality of reference & cache usage Most memory references relatively near to the instruction being executed the use of relative addressing saves address bits in the instruction 11-19

20 Base-Register Addressing Addressing A holds displacement R holds pointer to base address R may be explicit or implicit e.g. segment registers in 80x86 A single segment-base register employed and used implicitly In others, the programmer may choose a register to hold the base address of a segment, and the instruction must reference it explicitly 11-20

21 Indexed Addressing Addressing A = base R = displacement EA = A + R An efficient mechanism for performing iterative operations Index registers commonly used for such iterative task Need to increment or decrement the index register after each reference to it Good for accessing arrays (autoindexing) EA = A + R R++

22 Combinations Addressing Postindex EA = (A) + (R) Useful for accessing one of a number of blocks of data of a fixed format Preindex EA = (A+(R)) 11-22

23 Stack Addressing Addressing Stack - reversed block of locations Operand is (implicitly) on top of stack the block is partially filled Pointer(address of the top of the stack) is associated with the stack The top two elements of the stack may be in CPU registers the stack pointer references the third element of the stack e.g. ADD Pop top two items from stack and add 11-23

24 Stack Addressing Diagram Addressing Instruction Implicit Top of Stack register 11-24

25 Pentium Addressing Modes Pentium and PowerPC addressing modes Virtual or effective address is offset into segment Starting address plus offset gives linear address This goes through page translation if paging enabled 12 addressing modes available Immediate Register operand Displacement Base Base with displacement Scaled index with displacement Base with index and displacement Base scaled index with displacement Relative 11-25

26 Pentium Addressing Mode Pentium and PowerPC addressing modes 11-26

27 Pentium Addressing Modes Pentium and PowerPC addressing modes Mode Algorithm LA = linear address Immediate Operand = A (X) contents of X Register operand Displacement Base Base with displacement Scaled index with displacement LA = R LA = (SR) + A LA = (SR) + (B) LA = (SR) + (B)+A LA = (SR) + (I) S + A SR PC A R segment register program counter contents of an address field in the instruction register Base with index and displacement LA = (SR) + (B) + (I) + A B base register Base with scaled index LA = (SR) + (I) S + (B) +A I index register and displacement Relative LA = (PC) + A S scaling factor 11-27

28 PowerPC Addressing Modes Pentium and PowerPC addressing modes Load/store architecture Indirect Instruction includes 16 bit displacement to be added to base register (may be GP register) Can replace base register content with new address Indirect indexed Instruction references base register and index register (both may be GP) EA is sum of contents Branch address Absolute Relative Indirect Arithmetic Operands in registers or part of instruction Floating point is register only

29 PowerPC Addressing Modes Pentium and PowerPC addressing modes MODE Indirect Indirect indexed Absolute Relative Indirect Register Immediate Register Algorithm Load / Store Addressing EA = ( BR ) + D EA = ( BR ) + (IR ) Branch Addressing EA = I EA = ( PC ) + I EA = ( L/CR ) Fixed point Computation EA = GPR Operand = I Floating-point Computation EA = FPR EA = effective address ( X ) = contents of X BR = base register IR = index register L/CR = link or count register GPG = general-purpose register FPR = floating-point register D = displacement I = immediate value PC = program counter 11-29

30 PowerPC Addressing Modes Pentium and PowerPC addressing modes 11-30

31 Instruction Formats Instruction formats Layout of bits in an instruction Includes opcode Includes (implicit or explicit) zero or more operands Usually more than one instruction format in an instruction set 11-31

32 Instruction Length Instruction formats Affected by and affects: Memory size Memory organization Bus structure CPU complexity CPU speed Trade off between powerful instruction repertoire and saving space Either the instruction length should be equal to the memory-transfer length or one should be a multiple of the other 11-32

33 Instruction Length Instruction formats Memory can become a bottleneck Solutions To use cache memory To use shorter instructions The instruction length should be a multiple of the character length, which is usually 8 bits, and of the length of fixedpoint numbers

34 Allocation of Bits Instruction formats Trade off between the number of opcodes and the power of the addressing capability The use of variable-length opcodes Minimum opcode length For some cases, additional operations may be specified by using additional bits in the instruction 11-34

35 Interrelated Factors of Bits Instruction formats Number of addressing modes Number of operands Register versus memory Number of register sets Address range Address granularity 11-35

36 PDP - 8 Instruction formats 12-bit instructions Operates on 12-bit words 11-36

37 Instruction PDP-8 8 Instruction Format formats 11-37

38 PDP - 10 Instruction Formats Instruction formats Indirect Bit Opcode Register Index Register Memory Address

39 Variable-Length Instructions Instruction formats More flexible addressing with various combinations of register and memory references plus addressing modes The principal price for variable-length instructions is an increase in the complexity of the CPU The CPU does not know the length of the next instruction to be fetched A typical strategy is to fetch a number of bytes or words equal to at least the longest possible instruction Sometimes multiple instructions are fetched 11-39

40 PDP - 11 Instruction formats Eight 16-bit general purpose registers One of two is used as a stack pointer for special purpose stack operations The other is used as the program counter 11-40

41 Instruction PDP-11 Instruction Format formats 11-41

42 VAX Two criteria used in designing the VAX instruction format All instructions should have the natural number of operands All operands should have the same generality in specification The result is a highly variable instruction format An instruction consists of a 1 or 2 byte opcode followed by from 0 to 6 operand specifiers 1 to 37 byte instruction length Instruction formats 11-42

43 Example of VAX Instruction Instruction formats 11-43

44 Example of VAX Instruction Instruction formats 11-44

45 Example of VAX Instruction Instruction formats 11-45

46 Pentium Instruction Format Pentium and PowerPC instruction formats 11-46

47 Pentium Instruction Formats Pentium and PowerPC instruction formats Prefix bytes Instruction prefixes Segment override Address size Operand size Fields included by instruction Opcode Mod r/m SIB (scale/index/base) Displacement Immediate 11-47

48 Pentium Instruction Formats Pentium and PowerPC instruction formats The addressing mode is provided as part of the opcode sequence Only one operand can have address-mode information Only one memory operand can be referenced in an instruction Allows the use of not only 1-byte, but 2- byte and 4-byte offset for indexing The encoding of the Pentium II instruction set is very complex 11-48

49 PowerPC Instruction Formats Pentium and PowerPC instruction formats All instructions are 32 bits long and follow a regular format Regular structure of the formats eases the job of the instruction execution units 11-49

50 PowerPC Instruction Formats Pentium and PowerPC instruction formats 11-50

51 PowerPC Instruction Formats Pentium and PowerPC instruction formats 11-51

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