Introduction. Datapath Basics

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Gary Patterson
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1 Introduction CPU performance factors - Instruction count; determined by ISA and compiler - CPI and Cycle time; determined by CPU hardware 1 We will examine a simplified MIPS implementation in this course and a more realistic pipelined version in the next. Simple subset of machine instructions, shows most aspects - Memory reference: lw, sw - Arithmetic/logical: add, sub, and, or, slt - Control transfer: beq, j

2 Review of MIPS Machine Language Simple instructions, all 32 bits wide 2 Very structured, no unnecessary baggage Only three instruction formats: R op rs rt rd shamt funct I op rs rt 16-bit immediate J op 26-bit immediate Basic arithmetical-logical instructions are R-format. Load/store/conditional branch instructions are I-format. Jump/unconditional branch instructions are J-format McQuain, McQuain Feng & Ribbens

3 Instruction Execution PC instruction memory, fetch instruction 3 Register numbers register file, read registers Depending on instruction class - Use ALU to calculate - Arithmetic result - Memory address for load/store - Branch target address - Access data memory for load/store - PC target address or PC + 4

4 CPU Overview 4

5 Need for Selection Mechanisms 5 Must choose which one goes back to PC. BUT, you cannot just join wires together to achieve this Compute address for sequential execution. Compute address for conditional branch.

6 Multiplexors 6 Input 0 Input 1 Input 2... Input K-1 Output Select signal 0 K-1

7 Applying Control Logic The 2x1 multiplexor must have a 1-bit control line to select between the two inputs. There must be a combinational circuit that determines which input should be selected and passed through to the PC. 7 So, under what condition(s) should the branch address be used? if we're executing a conditional branch instruction and the branch condition has evaluated to true.

8 Control Questions 8 What's the logic for controlling the other MUXes? What goes here? What control settings will the ALU need?

9 Logic Design Basics Information encoded in binary - Low voltage = 0, High voltage = 1 - One wire per bit - Multi-bit data encoded on multi-wire buses 9 Combinational elements - Operate on data - Output is purely a function of input State (sequential) elements - Store information - Output/state depends on input and on previous state

10 Building a Datapath 10 Datapath - Elements that process data and addresses in the CPU - Registers, ALUs, mux s, memories, We will build a MIPS datapath incrementally - Refining the overview design

11 Instruction Fetch bit register Increment by 4 for next instruction just what we want unless current instruction is beq

12 R-Format Instructions 12 Read two register operands Perform arithmetic/logical operation Write register result op rs rt rd shamt funct We need to specify which ALU operation we need.

13 Load/Store Instructions 13 Read register operands Calculate address using 16-bit offset - Use ALU, but sign-extend offset Load: Read memory and update register Store: Write register value to memory op rs rt 16-bit immediate

14 Branch Instructions Read register operands Compare operands - Use ALU, subtract and check Zero output Calculate target address - Sign-extend displacement - Shift left 2 places (word displacement) - Add to PC Already calculated by instruction fetch 14 This will be the address of an instruction. So, it must be a multiple of 4. So, the two low-order bits (2^0 and 2^1) must both be zeros. So we won't store those bits in the instruction. So, we effectively get an 18-bit offset, which means we can jump further op rs rt 16-bit immediate

15 Branch Instructions 15 Just re-route wires Sign-bit wire replicated

16 Putting It All Together 16

Chapter 4. The Processor

Chapter 4. The Processor Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS implementations A simplified