Page 1. Structure of von Nuemann machine. Instruction Set - the type of Instructions

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1 Structure of von Nuemann machine Arithmetic and Logic Unit Input Output Equipment Main Memory Program Control Unit 1 1 Instruction Set - the type of Instructions Arithmetic + Logical (ADD, SUB, MULT, DIV, SHIFT, AND, OR,XOR, NOT) Control - branch, jump, call, return Data Transfer - copy, load, store String - move, compare, search + Floating Point - the same as arithmetic but usually take bigger operands + System - OS and memory management + Decimal special purposes (for example COBOL) 2 2 Instruction Set Influences Everything Instructions Source Code Optimizing Compiler Object Code CPI + Cycle time + CPI and Datapath Complexity + Instruction Decode + Instruction Encode 3 3 Page 1 1

2 Classifying Instruction Set Architecture 4 4 The code sequence for C=A+B Stack Push A Push B Add Pop C Accumulator Load A Add B Store C Register (register memory) Load R1, A Add R3,R1, B Store C, R1 Register (load - store) Load R1, A Load R2, B Add R3,R1,R2 Store R3,C 5 5 Typical combinations of memory operands Number of memory addr. Max number of operands Type of architecture 0 3 Registerregister 1 2 Registermemory 2 2 Memorymemory 3 3 Memorymemory Examples Alpha, MIPS, SPARK Intel 80x86, Motorola68000 VAX VAX 6 6 Page 2 2

3 Comparing different architectures Type Advantages Disadvantages Registerregister Registermemory Memorymemory Simple, fixed-length instruction encoding. Simple code generation model. Instruction take similar number of clocks to execute Data can be accessed without a separate load instruction first. Instruction format tends to be easy to encode and yields good density. Most compact. Doesn t waste registers for temporaries Higher instruction count than architectures with memory references. More instructions and lower instruction density leads to larger programs. Clock per instruction vary by operand location. Operands are not equivalent since a source operand in a binary operation is destroyed. Encoding may restrict the number of registers. Large variation in instruction size. Large variation in work per instruction. Memory accesses create memory bottleneck 7 7 Interpreting Memory Addresses Most of the computers are byte addressed and provide access for bytes, half words (16 bits), words (32 bits) and double words (64 bits). There are two different conventions for ordering the bytes within larger object: - Little Endian Big Endian Accesses to object larger than a byte must be aligned in many computers. 8 8 Aligned and misaligned addresses of byte An access to an objects of size s bytes at byte address A is aligned if A mod s = 0. Misaligned causes hardware complications, the memory is typically aligned on a multiple of a word or double word boundary, then such memory access may take multiple aligned memory references. Even if data are aligned, supporting byte, half-word and word accesses requires an alignment network to align bytes, half words and words in 64-bits registers. width of object Value of 3 low-order bits of byte address byte aligned aligned aligned aligned aligned aligned aligned aligned 2 bytes misaligned misaligned misaligned misaligned 9 9 Page 3 3

4 Addresing Modes Addressing modes specify constants and registers in addition to locations in memory When a memory location is used, the actual memory address specified by the addressing mode is called the effective address. Addressing modes have the ability to significantly reduce instruction counts; they also add to the complexity of building a computer and may increase the average CPI of computers that implements those modes Memory addressing modes I Memory addressing modes II Page 4 4

5 Type and Size of Operands Encoding in the opcode designates the type of an operand (computers with tagged data are not use currently). Usually the type of an operand gives its size Common operand type include: Characters (8 bits) Half word (16 bits) Word (32 bits) Single-precision floating point (32 bits) Double-precision floating points( 2 words) + decimal format (packet, unpacked) Integers are almost represented as two s complement binary numbers Characters are usually in ASCII (+ Unicode in Java) Floating point IEEE standard Operation in the Instruction Set Operator type Arithmetic and logical Data transfer Control System Floating point Decimal String Graphics Examples add, subtract, and, or, multiple, etc. load/store, move (on computers with memory addressing) branch jump, procedure call and return virtual memory management, operating system call add, multiply, divide, compare decimal add/multiply, decimal-to-character conversions string move, string compare pixel and vertex operation, compression/decompression operations Instructions for Control Flow Four different types of control flow changes Conditional branches Jumps Procedure calls Procedure returns Page 5 5

6 Addressing for Control Flow Instructions PC-relative destination is specified by supplying a displacement that is added to the program counter it enables position independence Dynamic addressing for example by naming a register that contains the target address; alternatively, the jump may permit any addressing mode to be used to supply the target address it enables register indirect jumps) Case or switch statements Virtual functions or methods Function pointers Conditional Branch Options Name Condition code Condition register Examples How condition Advantages Disadvantages is tested 80x86, PowerPC, SPARK Alpha, MIPS Tests special bits set by ALU operations, possible under program control Tests arbitrary register with the result of a comparison Sometimes condition set is free Simple CC is extra state. Condition codes constraints the ordering of instruction since they pass information from one instruction to a branch Uses up a register Compare PA-RISC, Compare is part One My be too much work and branch VAX of the branch. instruction per instruction for Often compare rather than pipeline execution is limited to two for a subset branch Procedure Invocation Options Procedure calls and returns include control transfer and possibly some state saving; at a minimum the return address must be saved somewhere, sometimes in a special link register or just a GPR There are two basic conventions in use to save registers Caller saving the calling procedure must save the register that it wants preserved for access after the call, and thus the called procedure need not worry about registers. Callee saving the called procedure must save the registers it wants to use, leaving the caller unrestrained Page 6 6

7 Encoding an Instruction Set The architect must balance several competing forces when encoding the instruction set: The desire to have as many registers and addressing modes as possible. The impact of the size of the register and addressing mode fields on the average instruction size and hence on the average program size. A desire to have instructions encoded into lengths that will be easy to handle in a pipelined implementation Encoding an Instruction Set - Variable It virtually allows all addressing modes to be with all operations. It is the best when there are many addressing modes and operations. It is used on VAX, Intel 80xx86, etc Encoding an Instruction Set - Fixed It combines the operation and the addressing mode into the opcode. Often fixed encoding will have only a single size for all instructions. It works the best when there are few addressing modes and operations. It is used on Alpha, MIPS, PowerPC, etc Page 7 7

8 Encoding an Instruction Set - Hybrid Reduce the variability in size and work of the variable architecture but provide multiple instruction lengths to reduce code size. It is used on IBM 360/70, Thumb, etc Page 8 8