Compositionality in system design: interfaces everywhere! UC Berkeley

Size: px
Start display at page:

Download "Compositionality in system design: interfaces everywhere! UC Berkeley"

Transcription

1 Compositionality in system design: interfaces everywhere! Stavros Tripakis UC Berkeley DREAMS Seminar, Mar 2013

2 Computers as parts of cyber physical systems cyber-physical ~98% of the world s processors are not in PCs but are embedded a premium car today has: ~80 computers (ECUs Electronic Control Units) ~100 million lines of code F t Future: smartt cars on smartt roads, d smartt power grids, id smart hospitals, smart cities, Tripakis 2

3 Languages & tools for CPS Simulink Domain specific Different models Simulink: 1 million licenses in 2004 Key concepts: reactive bh behavior concurrency timing I/O Modelica / Dymola LabVIEW Key capabilities: simulation code generation verification SCADE 3

4 Vision These modeling languages of today will become the system programming languages of tomorrow system compiler Rich languages: concurrency, time, robustness, reliability, energy, security, Complex execution platforms: networked, distributed, multicore, Powerful analyses: model checking, WCET analysis, schedulability, performance analysis, reliability analysis, Tripakis 4

5 Model Based Design How to describe what we want? How to be sure that this is what we want? Modeling Tripakis Analysis Synthesis How to build it? Automatically Correct by construction

6 Compositional Model Based Design Industry: system integration is key How to describe systems modularly? How to check properties in a compositional way? Modeling Tripakis Analysis Synthesis How to synthesize parts of the system independently?

7 This talk: interfaces Interface synthesis Interface theories 7 Tripakis 7

8 This talk Interface synthesis joint with R. Lublinerman, C. Szegedy, E. Lee, M. Geilen, B. Rodiers, D. Bui Interface theories Tripakis 8

9 Hierarchy Simulink Ptolemy model = tree of sub models Tripakis 9

10 Hierarchy in block diagrams A B P Tripakis 10

11 Hierarchy in block diagrams P Modularization: hide details, master complexity Tripakis 11

12 Hierarchy benefits Total number of blocks: ~100 Max. number at any level: ~6 model = tree of sub models Tripakis 12

13 Can we exploit this hierarchy beyond syntax? Can we reuse a submodel? Can we treat it as a black box? Can we build model libraries? Surprisingly, the answer is often no even in state of the art tools Tripakis 13

14 Modular compilation... Standard d Compiler (e.g., gcc).... gcc.. Linker (e.g., ld) Source code (e.g.,.cc files) Object code (e.g.,.o files) Executable Enables incremental compilation, IP protection,, and libraries! Tripakis 14

15 Modular code generation Can we do the same for system design languages? automatic code generation initialize state; while (true) do await clock tick; read inputs; compute; write outputs; update state; end while; initialize state; while (true) do await clock tick; read inputs; compute; write outputs; update state; end while; Code for block A Code for block B Code (C, C++, Java, ) Tripakis 15

16 Standard code generation: monolithic x1 x2 P A y1 P.fire(x1, x2) returns (y1, y2) { y1 := A.fire( x1 ); y2 := B.fire( x2 ); B y2 return (y1, y2); } Tripakis 16

17 Problem with monolithic code x1 y1 P.fire(x1, x2) returns (y1, y2); x2 P y2 Tripakis 17

18 Problem with monolithic code False I/O dependencies => code not usable in some contexts Parallel composition of functions is not a function! x1 A y1 P.fire(x1, x2) returns (y1, y2); x2 B y2 P Tripakis 18

19 Brief Simulink demo Tripakis 19

20 [DATE 08, POPL 09] Solution: non monolithic code A Mealy machine with multiple output functions x1 A y1 P.fire1( x1 ) returns y1 { return A.fire( x1 ); } x2 P B y2 P.fire2( x2 ) returns y2 { return B.fire( x2 ); } Tripakis 20

21 Non monolithic interface x1 y1 P.fire1( x1 ) returns y1 ; P x2 y2 P.fire2( x2 ) returns y2 ; Tripakis 21

22 Non monolithic interface x1 y1 P.fire1( x1 ) returns y1 ; x2 P y2 P.fire2( x2 ) returns y2 ; Tripakis 22

23 Non monolithic interface interface does not restrict usage x1 y1 P.fire1( x1 ) returns y1 ; P x2 y2 P.fire2( x2 ) returns y2 ; Tripakis 23

24 Bottom up interface synthesis P B A C Given interfaces for sub blocks A, B, C, compute interface for composite block P. Tripakis 24

25 Simple non monolithic interface x1 A y1 P.fire1( x1 ) returns y1 ; x2 B y2 P.fire2( x2 ) returns y2 ; P Tripakis 25

26 What about more complex diagrams? what about this? or this? Tripakis 26

27 Interface synthesis for block diagrams = graph clustering block diagram interface Tripakis 27

28 How it s done A B C D P Tripakis 28

29 How it s done Interface for B Interface for A P Interface for C Interface for D Tripakis 29

30 How it s done clustering Tripakis 30

31 How it s done Interface for P P.fire1() P.fire2() P.fire3() P Tripakis 31

32 Different clusterings => different interfaces x1 P.fire1() y1 x2 P.fire2() x3 P.fire3() y2 A non monolithic interface for P x2 x1 x3 P.fire() y1 y2 A monolithic interface for P trade off: interface size vs. reusability Tripakis 32

33 Different clustering algorithms = dff different tradeoffs Clustering method Complexity Achieves maximal reusability? Achieves minimal interf. size? Modularity bound? Achieves minimal code size? step get Polynomial No Almost <=2 functions Yes dynamic Polynomial Yes Yes <=N+1 functions* disjoint NP complete Yes Yes? Yes greedy Polynomial Yes No? Yes No * N = number of block outputs Tripakis 33

34 Bottom up interface synthesis = automatic abstraction P B A C Efficient + provably optimal Tripakis 34

35 [RTAS 08] Interfaces for multirate models Block A fires every 3 rounds Interface enriched with deterministic unary automata A B P 3: 2: (3) (2) union When does P need to fire? GCD(3,2) = 1 : over approximation too conservative 3 2: Tripakis 35

36 Interfaces for dataflow models A B 3 P 2 P FIFO queue monolithic interface Tripakis 36

37 [ACM TECS 2013] Interfaces for dataflow models A B 3 P 2 P FIFO queue monolithic interface P 1 A 2 3 B P Q Q original model does not deadlock monolithic interface => deadlocks! Tripakis 37

38 [ACM TECS 2013] Interfaces for dataflow models A P FIFO queue B input FIFO output FIFO SDF++ : shared FIFOs but deterministic! Non monolithic interface for P (generated automatically) Tripakis 38

39 This talk Interface synthesis Interface theories joint with B. Lickly, T. Henzinger, E. Lee, M. Geilen, M. Wiggers, C. Stergiou, M. Broy Tripakis 39

40 Incremental design A steer by wire system: v [ v min, v max ] A B C latency 10ms Tripakis 40

41 Incremental design v [ v min, v max ] A B C latency 10ms Z Tripakis 41

42 Incremental design How to ensure properties are preserved? v [ v min, v max ] A Z C latency 10ms Tripakis 42

43 Interface theories [Alfaro, Henzinger, et al.] Interface = component abstraction Interface composition: A B = C Interface refinement: A A Theorems: (1) If A A and A satisfies P then A satisfies P. (2) If A A and B B, then A B A B. Tripakis 43

44 Substitutability A B C A Z C (1) If A A and A satisfies P then A satisfies P. (2) If A A and B B, then A B A B. Z B and (1) and (2) => substitutability Tripakis 44

45 Which interface theories for CPS? Synchronous relational interfaces Functional properties (correctness) v [ v min, v max ] A B C Actor At interfaces latency 10ms Performance properties (throughput, latency, ) Tripakis 45

46 Which interface theories for CPS? Synchronous relational interfaces Functional properties (correctness) v [ v min, v max ] A B C Actor At interfaces latency 10ms Performance properties (throughput, latency, ) Tripakis 46

47 Interfaces for correctness [ACM TOPLAS 2011] (Real, Real) -> Real x1 x2 Divide y standard type block x2 0 x1 0 x2 0 y relational interface 0 Akin to behavioral types [Liskov et al] Tripakis 47

48 Interfaces for correctness: stateful l(d (dynamic) interface write read 1 place buffer full empty Static interface: (holds at every round) ( empty py ( write full read empty read full write ) ) Dynamic (state dependent) interface: write s0 empty write read read Tripakis 48 s1 full

49 Interfaces for correctness: compatibility bl checking = type checking z A x1 x2 Divide y x2 0 x2 0 x1 0 x2 0 y 0 Type error! Can be checked using SAT/SMT solvers Tripakis 49

50 Interfaces for correctness: interface synthesis = type inference z z 0 A x1 x2 Divide y x 2 z x2 0 x1 0 x2 0 y 0 Automatically synthesized constraint Tripakis 50

51 Interface synthesis: demonic vs. standard composition φ x φ1 y y φ2 z : 1 Standard: 1 2 Demonic : : 1 in ( ) : z : 2 2 : ( y 2 wp( 1, in( 2 )) : 1 in( 2 )) Tripakis 51

52 Interfaces for correctness: refinement ' = def in ( i ) in ( ' ) ( in ( ) ' ) Tripakis 52

53 Interfaces for correctness: refinement in ( ) in ( ' ) ( in ( ) ' ) Weaker than Liskov Wing behavioral subtyping: in ( ) in ( ' ) ' Tripakis 53

54 Main results Preservation of refinement by composition (parallel, serial, restricted feedback): If A A and B B, then A B A B. Refinement <=> substitutability: A can replace A in any context iff A A. full abstraction : refinement not stronger than necessary Tripakis 54

55 Which interface theories for CPS? Synchronous relational interfaces Functional properties (correctness) v [ v min, v max ] A B C Actor At interfaces latency 10ms Performance properties (throughput, latency, ) Tripakis 55

56 Interfaces for performance [HSCC 2011] Relations betweeni/o timedevent event streams No values associated with events 4 t1 t2 t3 t1+4 t2+4 t3+4 delay Tripakis 56

57 Interfaces for performance refinement: the earlier the better deterministic delay: 4 nondeterministic delay: [1,3] [ ] vs. standard refinement = inclusion of behaviors = implementations more deterministic than specs Tripakis 57

58 What it buys us time deterministic dt iiti model easier to analyze, verify, A B C preserves worst case performance (throughput, latency) time nondeterministic system Tripakis 58

59 Conclusions Interfaces = abstractions of components Keep necessary information, hide the rest No unique, one size fits all interface model / theory General principles: Bottom up interface synthesis for hierarchical languages Refinement for incremental design Tripakis 59

60 Thank you Questions? System Compiler Richer languages: concurrency, time, robustness, reliability, energy, security, more complex execution platforms: networked, distributed, multicore, more powerful analyses: model checking, WCET analysis, schedulability, performance analysis, reliability analysis, Tripakis 60

Modular code generation from synchronous models:

Modular code generation from synchronous models: Modular code generation from synchronous models: modularity vs. reusability vs. code size Stavros Tripakis Joint work with Roberto Lublinerman, Penn State CHESS seminar, Berkeley, Feb 2009 1 Semantics-preserving

More information

Refinement calculus for reactive systems

Refinement calculus for reactive systems Refinement calcls for reactive systems Stavros Tripakis UC Berkeley and Aalto University Joint work with Viorel Preoteasa (Aalto), Ben Lickly (Berkeley), Thomas Henzinger (IST Astria), and Edward Lee (Berkeley)

More information

Compositionality in Synchronous Data Flow: Modular Code Generation from Hierarchical SDF Graphs

Compositionality in Synchronous Data Flow: Modular Code Generation from Hierarchical SDF Graphs Compositionality in Synchronous Data Flow: Modular Code Generation from Hierarchical SDF Graphs Stavros Tripakis Dai Bui Marc Geilen Bert Rodiers Edward A. Lee Electrical Engineering and Computer Sciences

More information

Compositionality in Synchronous Data Flow: Modular Code Generation from Hierarchical SDF Graphs

Compositionality in Synchronous Data Flow: Modular Code Generation from Hierarchical SDF Graphs Compositionality in Synchronous Data Flow: Modular Code Generation from Hierarchical SDF Graphs STAVROS TRIPAKIS and DAI BUI, University of California, Berkeley MARC GEILEN, Eindhoven University of Technology

More information

Fundamental Algorithms for System Modeling, Analysis, and Optimization

Fundamental Algorithms for System Modeling, Analysis, and Optimization Fundamental lgorithms for System Modeling, nalysis, and Optimization Stavros Tripakis, Edward. Lee UC erkeley EECS 144/244 Fall 2013 Copyright 2010-2013, E.. Lee, J. Roydhowdhury, S.. Seshia, S. Tripakis,

More information

From synchronous models to distributed, asynchronous architectures

From synchronous models to distributed, asynchronous architectures From synchronous models to distributed, asynchronous architectures Stavros Tripakis Joint work with Claudio Pinello, Cadence Alberto Sangiovanni-Vincentelli, UC Berkeley Albert Benveniste, IRISA (France)

More information

Modelling, Analysis and Scheduling with Dataflow Models

Modelling, Analysis and Scheduling with Dataflow Models technische universiteit eindhoven Modelling, Analysis and Scheduling with Dataflow Models Marc Geilen, Bart Theelen, Twan Basten, Sander Stuijk, AmirHossein Ghamarian, Jeroen Voeten Eindhoven University

More information

Modal Models in Ptolemy

Modal Models in Ptolemy Modal Models in Ptolemy Edward A. Lee Stavros Tripakis UC Berkeley Workshop on Equation-Based Object-Oriented Modeling Languages and Tools 3rd International Workshop on Equation-Based Object-Oriented Modeling

More information

Concurrent Component Patterns, Models of Computation, and Types

Concurrent Component Patterns, Models of Computation, and Types Concurrent Component Patterns, Models of Computation, and Types Edward A. Lee Yuhong Xiong Department of Electrical Engineering and Computer Sciences University of California at Berkeley Presented at Fourth

More information

EECS 144/244: Fundamental Algorithms for System Modeling, Analysis, and Optimization

EECS 144/244: Fundamental Algorithms for System Modeling, Analysis, and Optimization EECS 144/244: Fundamental Algorithms for System Modeling, Analysis, and Optimization Dataflow Lecture: SDF, Kahn Process Networks Stavros Tripakis University of California, Berkeley Stavros Tripakis: EECS

More information

The Ptolemy II Framework for Visual Languages

The Ptolemy II Framework for Visual Languages The Ptolemy II Framework for Visual Languages Xiaojun Liu Yuhong Xiong Edward A. Lee Department of Electrical Engineering and Computer Sciences University of California at Berkeley Ptolemy II - Heterogeneous

More information

UC Berkeley Mobies Technology Project

UC Berkeley Mobies Technology Project UC Berkeley Mobies Technology Project Process-Based Software Components for Networked Embedded Systems PI: Edward Lee CoPI: Tom Henzinger Heterogeneous Modeling Discrete-Event RAM mp I/O DSP DXL ASIC Hydraulic

More information

Overview of Dataflow Languages. Waheed Ahmad

Overview of Dataflow Languages. Waheed Ahmad Overview of Dataflow Languages Waheed Ahmad w.ahmad@utwente.nl The purpose of models is not to fit the data but to sharpen the questions. Samuel Karlins 11 th R.A Fisher Memorial Lecture Royal Society

More information

Fundamental Algorithms for System Modeling, Analysis, and Optimization

Fundamental Algorithms for System Modeling, Analysis, and Optimization Fundamental Algorithms for System Modeling, Analysis, and Optimization Stavros Tripakis, Edward A. Lee UC Berkeley EECS 144/244 Fall 2014 Copyright 2014, E. A. Lee, J. Roydhowdhury, S. A. Seshia, S. Tripakis

More information

Graphical System Design. David Fuller LabVIEW R&D Section Manager

Graphical System Design. David Fuller LabVIEW R&D Section Manager Graphical System Design David Fuller LabVIEW R&D Section Manager Agenda Visions Demo Order & time National Instruments Confidential 2 Virtual Instrumentation National Instruments Confidential 3 Virtual

More information

Predictable Timing of Cyber-Physical Systems Future Research Challenges

Predictable Timing of Cyber-Physical Systems Future Research Challenges Predictable Timing of Cyber- Systems Future Research Challenges DREAMS Seminar, EECS, UC Berkeley January 17, 2012 David Broman EECS Department UC Berkeley, USA Department of Computer and Information Science

More information

EECS 144/244. Fundamental Algorithms for System Modeling, Analysis, and Optimization. Lecture 1: Introduction, Systems

EECS 144/244. Fundamental Algorithms for System Modeling, Analysis, and Optimization. Lecture 1: Introduction, Systems EECS 144/244 Fundamental Algorithms for System Modeling, Analysis, and Optimization Lecture 1: Introduction, Systems Stavros Tripakis UC Berkeley Spring 2013 1 Computers as parts of Systems ~98% of the

More information

Embedded Software Engineering

Embedded Software Engineering Embedded Software Engineering 3 Unit Course, Spring 2002 EECS Department, UC Berkeley Christoph Kirsch www.eecs.berkeley.edu/~fresco/giotto/course-2002 It s significant $4 billion development effort >

More information

Advanced Tool Architectures. Edited and Presented by Edward A. Lee, Co-PI UC Berkeley. Tool Projects. Chess Review May 10, 2004 Berkeley, CA

Advanced Tool Architectures. Edited and Presented by Edward A. Lee, Co-PI UC Berkeley. Tool Projects. Chess Review May 10, 2004 Berkeley, CA Advanced Tool Architectures Edited and Presented by Edward A. Lee, Co-PI UC Berkeley Chess Review May 10, 2004 Berkeley, CA Tool Projects Concurrent model-based design Giotto (Henzinger) E machine & S

More information

Synchronous Statecharts. Christian Motika

Synchronous Statecharts. Christian Motika Execution (KlePto) Esterel to transformation (KIES) Synchronous Statecharts for executing Esterel with Ptolemy Christian Motika Real-Time Systems and Embedded Systems Group Department of Computer Science

More information

Embedded software design with Polychrony

Embedded software design with Polychrony Embedded software design with Polychrony DATE 09 tutorial on Correct-by-Construction Embedded Software Synthesis: Formal Frameworks, Methodologies, and Tools Jean-Pierre Talpin, RIA List of contributors

More information

Main application of SDF: DSP hardware modeling

Main application of SDF: DSP hardware modeling EE 144/244: Fundamental lgorithms for System Modeling, nalysis, and Optimization Fall 2014 Dataflow Timed SDF, Throughput nalysis Stavros Tripakis University of California, erkeley Stavros Tripakis (UC

More information

Ptolemy II The automotive challenge problems version 4.1

Ptolemy II The automotive challenge problems version 4.1 Ptolemy II The automotive challenge problems version 4.1 Johan Eker Edward Lee with thanks to Jie Liu, Paul Griffiths, and Steve Neuendorffer MoBIES Working group meeting, 27-28 September 2001, Dearborn

More information

Reliable Embedded Multimedia Systems?

Reliable Embedded Multimedia Systems? 2 Overview Reliable Embedded Multimedia Systems? Twan Basten Joint work with Marc Geilen, AmirHossein Ghamarian, Hamid Shojaei, Sander Stuijk, Bart Theelen, and others Embedded Multi-media Analysis of

More information

ESE532: System-on-a-Chip Architecture. Today. Process. Message FIFO. Thread. Dataflow Process Model Motivation Issues Abstraction Recommended Approach

ESE532: System-on-a-Chip Architecture. Today. Process. Message FIFO. Thread. Dataflow Process Model Motivation Issues Abstraction Recommended Approach ESE53: System-on-a-Chip Architecture Day 5: January 30, 07 Dataflow Process Model Today Dataflow Process Model Motivation Issues Abstraction Recommended Approach Message Parallelism can be natural Discipline

More information

Computational Models for Concurrent Streaming Applications

Computational Models for Concurrent Streaming Applications 2 Computational Models for Concurrent Streaming Applications The challenges of today Twan Basten Based on joint work with Marc Geilen, Sander Stuijk, and many others Department of Electrical Engineering

More information

Hierarchical FSMs with Multiple CMs

Hierarchical FSMs with Multiple CMs Hierarchical FSMs with Multiple CMs Manaloor Govindarajan Balasubramanian Manikantan Bharathwaj Muthuswamy (aka Bharath) Reference: Hierarchical FSMs with Multiple Concurrency Models. Alain Girault, Bilung

More information

Introduction to Embedded Systems

Introduction to Embedded Systems Introduction to Embedded Systems Sanjit A. Seshia UC Berkeley EECS 149/249A Fall 2015 2008-2015: E. A. Lee, A. L. Sangiovanni-Vincentelli, S. A. Seshia. All rights reserved. Chapter 3: Discrete Dynamics,

More information

Introduction to Electronic Design Automation. Model of Computation. Model of Computation. Model of Computation

Introduction to Electronic Design Automation. Model of Computation. Model of Computation. Model of Computation Introduction to Electronic Design Automation Model of Computation Jie-Hong Roland Jiang 江介宏 Department of Electrical Engineering National Taiwan University Spring 03 Model of Computation In system design,

More information

Actor-Oriented Design: Concurrent Models as Programs

Actor-Oriented Design: Concurrent Models as Programs Actor-Oriented Design: Concurrent Models as Programs Edward A. Lee Professor, UC Berkeley Director, Center for Hybrid and Embedded Software Systems (CHESS) Parc Forum Palo Alto, CA May 13, 2004 Abstract

More information

Specifications Part 1

Specifications Part 1 pm3 12 Specifications Part 1 Embedded System Design Kluwer Academic Publisher by Peter Marwedel TU Dortmund 2008/11/15 ine Marwedel, 2003 Graphics: Alexandra Nolte, Ges Introduction 12, 2008-2 - 1 Specification

More information

Concurrent Models of Computation

Concurrent Models of Computation Concurrent Models of Computation Edward A. Lee Robert S. Pepper Distinguished Professor, UC Berkeley EECS 219D Concurrent Models of Computation Fall 2011 Copyright 2009-2011, Edward A. Lee, All rights

More information

Interface Automata and Actif Actors

Interface Automata and Actif Actors Interface Automata and Actif Actors H. John Reekie Dept. of Electrical Engineering and Computer Science University of California at Berkeley johnr@eecs.berkeley.edu Abstract This technical note uses the

More information

Scalable Semantic Annotation using Lattice-based Ontologies

Scalable Semantic Annotation using Lattice-based Ontologies Scalable Semantic Annotation using Lattice-based Ontologies Ben Lickly 1 Man-Kit Leung 1 Thomas Mandl 2 Edward A. Lee 1 Elizabeth Latronico 2 Charles Shelton 2 Stavros Tripakis 1 1 University of California,

More information

Resource-bound process algebras for Schedulability and Performance Analysis of Real-Time and Embedded Systems

Resource-bound process algebras for Schedulability and Performance Analysis of Real-Time and Embedded Systems Resource-bound process algebras for Schedulability and Performance Analysis of Real-Time and Embedded Systems Insup Lee 1, Oleg Sokolsky 1, Anna Philippou 2 1 RTG (Real-Time Systems Group) Department of

More information

Modular Code Generation from Synchronous Block Diagrams

Modular Code Generation from Synchronous Block Diagrams Modular Code Generation from Synchronous Block Diagrams Modularity vs. Code Size Roberto Lublinerman Computer Science and Engineering Pennsylvania State University rluble@psu.edu Christian Szegedy Cadence

More information

Classes and Inheritance in Actor- Oriented Models

Classes and Inheritance in Actor- Oriented Models Classes and Inheritance in Actor- Oriented Models Stephen Neuendorffer Edward Lee UC Berkeley Chess Review May 8, 2003 Berkeley, CA Introduction Component-based design Object-oriented components Actor-oriented

More information

By: Chaitanya Settaluri Devendra Kalia

By: Chaitanya Settaluri Devendra Kalia By: Chaitanya Settaluri Devendra Kalia What is an embedded system? An embedded system Uses a controller to perform some function Is not perceived as a computer Software is used for features and flexibility

More information

Process-Based Software Components Final Mobies Presentation

Process-Based Software Components Final Mobies Presentation Process-Based Software Components Final Mobies Presentation Edward A. Lee Professor UC Berkeley PI Meeting, Savannah, GA January 21-23, 2004 PI: Edward A. Lee, 510-642-0455, eal@eecs.berkeley.edu Co-PI:

More information

Automated Refinement Checking of Asynchronous Processes. Rajeev Alur. University of Pennsylvania

Automated Refinement Checking of Asynchronous Processes. Rajeev Alur. University of Pennsylvania Automated Refinement Checking of Asynchronous Processes Rajeev Alur University of Pennsylvania www.cis.upenn.edu/~alur/ Intel Formal Verification Seminar, July 2001 Problem Refinement Checking Given two

More information

Applying Models of Computation to OpenCL Pipes for FPGA Computing. Nachiket Kapre + Hiren Patel

Applying Models of Computation to OpenCL Pipes for FPGA Computing. Nachiket Kapre + Hiren Patel Applying Models of Computation to OpenCL Pipes for FPGA Computing Nachiket Kapre + Hiren Patel nachiket@uwaterloo.ca Outline Models of Computation and Parallelism OpenCL code samples Synchronous Dataflow

More information

Concurrent Models of Computation

Concurrent Models of Computation Concurrent Models of Computation Edward A. Lee Robert S. Pepper Distinguished Professor, UC Berkeley EECS 219D: Concurrent Models of Computation Fall 2011 Copyright 2011, Edward A. Lee, All rights reserved

More information

The Gigascale Silicon Research Center

The Gigascale Silicon Research Center The Gigascale Silicon Research Center The GSRC Semantics Project Tom Henzinger Luciano Lavagno Edward Lee Alberto Sangiovanni-Vincentelli Kees Vissers Edward A. Lee UC Berkeley What is GSRC? The MARCO/DARPA

More information

LabVIEW Based Embedded Design [First Report]

LabVIEW Based Embedded Design [First Report] LabVIEW Based Embedded Design [First Report] Sadia Malik Ram Rajagopal Department of Electrical and Computer Engineering University of Texas at Austin Austin, TX 78712 malik@ece.utexas.edu ram.rajagopal@ni.com

More information

Scheduling and Optimizing Stream Programs on Multicore Machines by Exploiting High-Level Abstractions

Scheduling and Optimizing Stream Programs on Multicore Machines by Exploiting High-Level Abstractions Scheduling and Optimizing Stream Programs on Multicore Machines by Exploiting High-Level Abstractions Dai Bui Electrical Engineering and Computer Sciences University of California at Berkeley Technical

More information

Modularity vs. Reusability: Code Generation from Synchronous Block Diagrams

Modularity vs. Reusability: Code Generation from Synchronous Block Diagrams Modularity vs. Reusability: Code Generation from Synchronous Block Diagrams Roberto Lublinerman Department of Computer Science and Engineering The Pennsylvania State University University Park, P 16802

More information

Software Synthesis Trade-offs in Dataflow Representations of DSP Applications

Software Synthesis Trade-offs in Dataflow Representations of DSP Applications in Dataflow Representations of DSP Applications Shuvra S. Bhattacharyya Department of Electrical and Computer Engineering, and Institute for Advanced Computer Studies University of Maryland, College Park

More information

Model-based Analysis of Event-driven Distributed Real-time Embedded Systems

Model-based Analysis of Event-driven Distributed Real-time Embedded Systems Model-based Analysis of Event-driven Distributed Real-time Embedded Systems Gabor Madl Committee Chancellor s Professor Nikil Dutt (Chair) Professor Tony Givargis Professor Ian Harris University of California,

More information

Petri Nets ee249 Fall 2000

Petri Nets ee249 Fall 2000 Petri Nets ee249 Fall 2000 Marco Sgroi Most slides borrowed from Luciano Lavagno s lecture ee249 (1998) 1 Models Of Computation for reactive systems Main MOCs: Communicating Finite State Machines Dataflow

More information

Tokens vs. Signals: On Conformance between Formal Models of Dataflow and Hardware

Tokens vs. Signals: On Conformance between Formal Models of Dataflow and Hardware DOI 10.1007/s11265-015-0971-y Tokens vs. Signals: On Conformance between Formal Models of Dataflow and Hardware Stavros Tripakis Rhishikesh Limaye Kaushik Ravindran Guoqiang Wang Hugo Andrade Arkadeb Ghosal

More information

System-Level Design Languages: Orthogonalizing the Issues

System-Level Design Languages: Orthogonalizing the Issues System-Level Design Languages: Orthogonalizing the Issues The GSRC Semantics Project Tom Henzinger Luciano Lavagno Edward Lee Alberto Sangiovanni-Vincentelli Kees Vissers Edward A. Lee UC Berkeley What

More information

C Code Generation from the Giotto Model of Computation to the PRET Architecture

C Code Generation from the Giotto Model of Computation to the PRET Architecture C Code Generation from the Giotto Model of Computation to the PRET Architecture Shanna-Shaye Forbes Ben Lickly Man-Kit Leung Electrical Engineering and Computer Sciences University of California at Berkeley

More information

Quantitative Verification and Synthesis of Systems

Quantitative Verification and Synthesis of Systems Quantitative Verification and Synthesis of Systems Sanjit A. Seshia Assistant Professor EECS, UC Berkeley Software-at-Scale Workshop August 2010 Quantitative Analysis / Verification Does the brake-by-wire

More information

Understandable Concurrency

Understandable Concurrency Edward A. Lee Professor, Chair of EE, and Associate Chair of EECS Director, CHESS: Center for Hybrid and Embedded Software Systems Director, Ptolemy Project UC Berkeley Chess Review November 21, 2005 Berkeley,

More information

Giotto Domain. 5.1 Introduction. 5.2 Using Giotto. Edward Lee Christoph Kirsch

Giotto Domain. 5.1 Introduction. 5.2 Using Giotto. Edward Lee Christoph Kirsch Chapter 5 from: C. Brooks, E. A. Lee, X. Liu, S. Neuendorffer, Y. Zhao, H. Zheng "Heterogeneous Concurrent Modeling and Design in Java (Volume 3: Ptolemy II Domains)," Technical Memorandum UCB/ERL M04/17,

More information

System-level Synthesis of Dataflow Applications for FPGAbased Distributed Platforms

System-level Synthesis of Dataflow Applications for FPGAbased Distributed Platforms System-level Synthesis of Dataflow Applications for FPGAbased Distributed Platforms Hugo A. Andrade, Kaushik Ravindran, Alejandro Asenjo, Casey Weltzin NI Berkeley, NI Austin National Instruments Corporation

More information

Dynamic Dataflow. Seminar on embedded systems

Dynamic Dataflow. Seminar on embedded systems Dynamic Dataflow Seminar on embedded systems Dataflow Dataflow programming, Dataflow architecture Dataflow Models of Computation Computation is divided into nodes that can be executed concurrently Dataflow

More information

Timing Definition Language (TDL) Concepts, Code Generation and Tools

Timing Definition Language (TDL) Concepts, Code Generation and Tools Timing Definition Language (TDL) Concepts, Code Generation and Tools Wolfgang Pree Embedded Software & Systems Research Center Department of Computer Sciences Univ. Salzburg Overview Motivation Timing

More information

Communication Systems Design in Practice

Communication Systems Design in Practice Communication Systems Design in Practice Jacob Kornerup, Ph.D. LabVIEW R&D National Instruments A Word About National Instruments Annual Revenue: $1.14 billion Global Operations: Approximately 6,870 employees;

More information

Building Unreliable Systems out of Reliable Components: The Real Time Story

Building Unreliable Systems out of Reliable Components: The Real Time Story Building Unreliable Systems out of Reliable Components: The Real Time Story Edward A. Lee Professor, Chair of EE, and Associate Chair of EECS CHESS: Center for Hybrid and Embedded Software Systems UC Berkeley

More information

Portable Real-Time Code from PTIDES Models

Portable Real-Time Code from PTIDES Models Portable Real-Time Code from PTIDES Models Patricia Derler, John Eidson, Edward A. Lee, Slobodan Matic, Christos Stergiou, Michael Zimmer UC Berkeley Invited Talk Workshop on Time Analysis and Model-Based

More information

Reliable Dynamic Embedded Data Processing Systems

Reliable Dynamic Embedded Data Processing Systems 2 Embedded Data Processing Systems Reliable Dynamic Embedded Data Processing Systems sony Twan Basten thales Joint work with Marc Geilen, AmirHossein Ghamarian, Hamid Shojaei, Sander Stuijk, Bart Theelen,

More information

Hardware Design Environments. Dr. Mahdi Abbasi Computer Engineering Department Bu-Ali Sina University

Hardware Design Environments. Dr. Mahdi Abbasi Computer Engineering Department Bu-Ali Sina University Hardware Design Environments Dr. Mahdi Abbasi Computer Engineering Department Bu-Ali Sina University Outline Welcome to COE 405 Digital System Design Design Domains and Levels of Abstractions Synthesis

More information

SDL. Jian-Jia Chen (slides are based on Peter Marwedel) TU Dortmund, Informatik 年 10 月 18 日. technische universität dortmund

SDL. Jian-Jia Chen (slides are based on Peter Marwedel) TU Dortmund, Informatik 年 10 月 18 日. technische universität dortmund 12 SDL Jian-Jia Chen (slides are based on Peter Marwedel) TU Dortmund, Informatik 12 2017 年 10 月 18 日 Springer, 2010 These slides use Microsoft clip arts. Microsoft copyright restrictions apply. Models

More information

Component-Based Design of Embedded Control Systems

Component-Based Design of Embedded Control Systems Component-Based Design of Embedded Control Systems Luca Dealfaro Chamberlain Fong Tom Henzinger Christopher Hylands John Koo Edward A. Lee Jie Liu Xiaojun Liu Steve Neuendorffer Sonia Sachs Shankar Sastry

More information

Static program checking and verification

Static program checking and verification Chair of Software Engineering Software Engineering Prof. Dr. Bertrand Meyer March 2007 June 2007 Slides: Based on KSE06 With kind permission of Peter Müller Static program checking and verification Correctness

More information

Modelling and simulation of guaranteed throughput channels of a hard real-time multiprocessor system

Modelling and simulation of guaranteed throughput channels of a hard real-time multiprocessor system Modelling and simulation of guaranteed throughput channels of a hard real-time multiprocessor system A.J.M. Moonen Information and Communication Systems Department of Electrical Engineering Eindhoven University

More information

Outline. Petri nets. Introduction Examples Properties Analysis techniques. 1 EE249Fall04

Outline. Petri nets. Introduction Examples Properties Analysis techniques. 1 EE249Fall04 Outline Petri nets Introduction Examples Properties Analysis techniques 1 Petri Nets (PNs) Model introduced by C.A. Petri in 1962 Ph.D. Thesis: Communication with Automata Applications: distributed computing,

More information

EE382N.23: Embedded System Design and Modeling

EE382N.23: Embedded System Design and Modeling EE38N.3: Embedded System Design and Modeling Lecture 5 Process-Based MoCs Andreas Gerstlauer Electrical and Computer Engineering University of Texas at Austin gerstl@ece.utexas.edu Lecture 5: Outline Process-based

More information

Embedded Systems 8. Identifying, modeling and documenting how data moves around an information system. Dataflow modeling examines

Embedded Systems 8. Identifying, modeling and documenting how data moves around an information system. Dataflow modeling examines Embedded Systems 8 - - Dataflow modeling Identifying, modeling and documenting how data moves around an information system. Dataflow modeling examines processes (activities that transform data from one

More information

Embedded Software from Concurrent Component Models

Embedded Software from Concurrent Component Models Embedded Software from Concurrent Component Models Edward A. Lee UC Berkeley with Shuvra Bhattacharyya, Johan Eker, Christopher Hylands, Jie Liu, Xiaojun Liu, Steve Neuendorffer, Jeff Tsay, and Yuhong

More information

Using Heterogeneous Formal Methods in Model-Based Development LCCC Workshop on Formal Verification of Embedded Control Systems

Using Heterogeneous Formal Methods in Model-Based Development LCCC Workshop on Formal Verification of Embedded Control Systems Using Heterogeneous Formal Methods in Model-Based Development LCCC Workshop on Formal Verification of Embedded Control Systems Bruce H. Krogh Carnegie Mellon University in Rwanda Kigali, Rwanda 1 Model-Based

More information

The Embedded Systems Design Challenge. EPFL Verimag

The Embedded Systems Design Challenge. EPFL Verimag The Embedded Systems Design Challenge Tom Henzinger Joseph Sifakis EPFL Verimag Formal Methods: A Tale of Two Cultures Engineering Computer Science Differential Equations Linear Algebra Probability Theory

More information

Towards Lab Based MOOCs: Embedded Systems, Robotics, and Beyond

Towards Lab Based MOOCs: Embedded Systems, Robotics, and Beyond Towards Lab Based MOOCs: Embedded Systems, Robotics, and Beyond Sanjit A. Seshia UC Berkeley Joint work with: Edward A. Lee, Jeff. C. Jensen, Alexandre Donzé, Garvit Juniwal, Andy Chang UC Berkeley & NI

More information

PTIDES: A Discrete-Event-Based Programming Model for Distributed Embedded Systems

PTIDES: A Discrete-Event-Based Programming Model for Distributed Embedded Systems PTIDES: A Discrete-Event-Based Programming Model for Distributed Embedded Systems John C. Eidson Edward A. Lee Slobodan Matic Sanjit A. Seshia Jia Zou UC Berkeley Tutorial on Modeling and Analyzing Real-Time

More information

Application-Platform Mapping in Multiprocessor Systems-on-Chip

Application-Platform Mapping in Multiprocessor Systems-on-Chip Application-Platform Mapping in Multiprocessor Systems-on-Chip Leandro Soares Indrusiak lsi@cs.york.ac.uk http://www-users.cs.york.ac.uk/lsi CREDES Kick-off Meeting Tallinn - June 2009 Application-Platform

More information

Review Sources of Architecture. Why Domain-Specific?

Review Sources of Architecture. Why Domain-Specific? Domain-Specific Software Architectures (DSSA) 1 Review Sources of Architecture Main sources of architecture black magic architectural visions intuition theft method Routine design vs. innovative design

More information

Advanced Tool Architectures

Advanced Tool Architectures Advanced Tool Architectures Edited and Presented by Edward A. Lee, Co-PI UC Berkeley Chess Review November 18, 2004 Berkeley, CA Tool Projects Concurrent model-based design E machine & S machine (Henzinger)

More information

A Multi-Modal Composability Framework for Cyber-Physical Systems

A Multi-Modal Composability Framework for Cyber-Physical Systems S5 Symposium June 12, 2012 A Multi-Modal Composability Framework for Cyber-Physical Systems Linh Thi Xuan Phan Insup Lee PRECISE Center University of Pennsylvania Avionics, Automotive Medical Devices Cyber-physical

More information

fakultät für informatik informatik 12 technische universität dortmund Data flow models Peter Marwedel TU Dortmund, Informatik /10/08

fakultät für informatik informatik 12 technische universität dortmund Data flow models Peter Marwedel TU Dortmund, Informatik /10/08 12 Data flow models Peter Marwedel TU Dortmund, Informatik 12 2009/10/08 Graphics: Alexandra Nolte, Gesine Marwedel, 2003 Models of computation considered in this course Communication/ local computations

More information

Unit 2: High-Level Synthesis

Unit 2: High-Level Synthesis Course contents Unit 2: High-Level Synthesis Hardware modeling Data flow Scheduling/allocation/assignment Reading Chapter 11 Unit 2 1 High-Level Synthesis (HLS) Hardware-description language (HDL) synthesis

More information

StateClock: a Tool for Timed Reactive Modules

StateClock: a Tool for Timed Reactive Modules StateClock: a Tool for Timed Reactive Modules Jonathan S. Ostroff Department Of Computer Science, York University, Toronto, Canada, M3J 1P3. Email: jonathan@yorku.ca Abstract: We provide an overview of

More information

Communication Systems Design in Practice

Communication Systems Design in Practice Communication Systems Design in Practice Jacob Kornerup, Ph.D. LabVIEW R&D National Instruments '87 '88 '89 '90 '91 '92 '93 '94 '95 '96 '97 '98 '99 '00 '01 '02 03 04 '05 '06 '07 '08 '09 '10 '11 '12 '13

More information

The Power of Abstraction. Barbara Liskov May 2013 MIT CSAIL

The Power of Abstraction. Barbara Liskov May 2013 MIT CSAIL The Power of Abstraction Barbara Liskov May 2013 MIT CSAIL Software is Complex Systems are big and they do complicated things and they may be distributed and/or concurrent Addressing Complexity Algorithms,

More information

A Deterministic Concurrent Language for Embedded Systems

A Deterministic Concurrent Language for Embedded Systems SHIM:A A Deterministic Concurrent Language for Embedded Systems p. 1/28 A Deterministic Concurrent Language for Embedded Systems Stephen A. Edwards Columbia University Joint work with Olivier Tardieu SHIM:A

More information

FPGA for Software Engineers

FPGA for Software Engineers FPGA for Software Engineers Course Description This course closes the gap between hardware and software engineers by providing the software engineer all the necessary FPGA concepts and terms. The course

More information

Software Design. Levels in Design Process. Design Methodologies. Levels..

Software Design. Levels in Design Process. Design Methodologies. Levels.. Design Software Design Design activity begins with a set of requirements Design done before the system is implemented Design is the intermediate language between requirements and code Moving from problem

More information

Symbolic Buffer Sizing for Throughput-Optimal Scheduling of Dataflow Graphs

Symbolic Buffer Sizing for Throughput-Optimal Scheduling of Dataflow Graphs Symbolic Buffer Sizing for Throughput-Optimal Scheduling of Dataflow Graphs Anan Bouakaz Pascal Fradet Alain Girault Real-Time and Embedded Technology and Applications Symposium, Vienna April 14th, 2016

More information

System-level co-modeling AADL and Simulink specifications using Polychrony (and Syndex)

System-level co-modeling AADL and Simulink specifications using Polychrony (and Syndex) System-level co-modeling AADL and Simulink specifications using Polychrony (and Syndex) AADL Standards Meeting June 6., 2011 Jean-Pierre Talpin, INRIA Parts of this presentation are joint work with Paul,

More information

VHDL for Synthesis. Course Description. Course Duration. Goals

VHDL for Synthesis. Course Description. Course Duration. Goals VHDL for Synthesis Course Description This course provides all necessary theoretical and practical know how to write an efficient synthesizable HDL code through VHDL standard language. The course goes

More information

Static Scheduling and Code Generation from Dynamic Dataflow Graphs With Integer- Valued Control Streams

Static Scheduling and Code Generation from Dynamic Dataflow Graphs With Integer- Valued Control Streams Presented at 28th Asilomar Conference on Signals, Systems, and Computers November, 994 Static Scheduling and Code Generation from Dynamic Dataflow Graphs With Integer- Valued Control Streams Joseph T.

More information

Asynchronous Elastic Dataflows by Leveraging Clocked EDA

Asynchronous Elastic Dataflows by Leveraging Clocked EDA Optimised Synthesis of Asynchronous Elastic Dataflows by Leveraging Clocked EDA Mahdi Jelodari Mamaghani, Jim Garside, Will Toms, & Doug Edwards Verona, Italy 29 th August 2014 Motivation: Automatic GALSification

More information

CSc33200: Operating Systems, CS-CCNY, Fall 2003 Jinzhong Niu December 10, Review

CSc33200: Operating Systems, CS-CCNY, Fall 2003 Jinzhong Niu December 10, Review CSc33200: Operating Systems, CS-CCNY, Fall 2003 Jinzhong Niu December 10, 2003 Review 1 Overview 1.1 The definition, objectives and evolution of operating system An operating system exploits and manages

More information

Advanced ALTERA FPGA Design

Advanced ALTERA FPGA Design Advanced ALTERA FPGA Design Course Description This course focuses on advanced FPGA design topics in Quartus software. The first part covers advanced timing closure problems, analysis and solutions. The

More information

Introduction to Formal Methods

Introduction to Formal Methods 2008 Spring Software Special Development 1 Introduction to Formal Methods Part I : Formal Specification i JUNBEOM YOO jbyoo@knokuk.ac.kr Reference AS Specifier s Introduction to Formal lmethods Jeannette

More information

Conservative and compositional modeling in the CompSOC platform

Conservative and compositional modeling in the CompSOC platform Eindhoven University of Technology MASTER Conservative and compositional modeling in the CompSOC platform Milea, T.Y. Award date: 2012 Link to publication Disclaimer This document contains a student thesis

More information

Desired Characteristics of Modules. Stefan Resmerita, WS2015

Desired Characteristics of Modules. Stefan Resmerita, WS2015 Desired Characteristics of Modules 1 Stable and Understandable Module Interfaces by Information Hiding (I) The design principle Information Hiding goes back to David L. Parnas (1972). Thus, modules are

More information

Embedded Systems 7. Models of computation for embedded systems

Embedded Systems 7. Models of computation for embedded systems Embedded Systems 7 - - Models of computation for embedded systems Communication/ local computations Communicating finite state machines Data flow model Computational graphs Von Neumann model Discrete event

More information

Computational Process Networks a model and framework for high-throughput signal processing

Computational Process Networks a model and framework for high-throughput signal processing Computational Process Networks a model and framework for high-throughput signal processing Gregory E. Allen Ph.D. Defense 25 April 2011 Committee Members: James C. Browne Craig M. Chase Brian L. Evans

More information

FSMs & message passing: SDL

FSMs & message passing: SDL 12 FSMs & message passing: SDL Peter Marwedel TU Dortmund, Informatik 12 Springer, 2010 2012 年 10 月 30 日 These slides use Microsoft clip arts. Microsoft copyright restrictions apply. Models of computation

More information