ASSEMBLY LANGUAGE MACHINE ORGANIZATION

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1 ASSEMBLY LANGUAGE MACHINE ORGANIZATION CHAPTER 3 1

2 Sub-topics The topic will cover: Microprocessor architecture CPU processing methods Pipelining Superscalar RISC Multiprocessing Instruction Cycle Instruction Sets and Types 2

3 MICROPROCESSOR ARCHITECTURE 3

4 Microprocessor (CPU) Architecture This topic focuses on the components in the microprocessor related to the machine instruction cycle namely the : Control Unit, Arithmetic Logic Unit, Registers, and Clock. 4

5 Microprocessor (CPU) Architecture 5

6 Microprocessor (CPU) Microprocessor (CPU) The microprocessor (central processing unit) is similar to the human brain. The heart of a computer is the CPU. It interprets and carries out the basic instructions that operate a computer. Most processor chips manufacturers now offer multi-core processors single chip with more than one separate processor cores. These cores are viewed by the OS as separate processors. Currently there are dual-core processors and quad-core processors. 6

7 Microprocessor (CPU) The processors contains three main components which work together to perform processing operations. CU ALU Registers 7

8 Microprocessor (CPU): 3 main components 8

9 Microprocessor (CPU): System Block Diagram 9

10 Microprocessor (CPU) Machine Cycle CPU Functions: Fetch: Obtain program instruction or data item from the main memory Decode : Translate the program instruction into the commands that computer can process Execute: Carry out the commands one after another Store: Store the result into main memory 10

11 Microprocessor (CPU) Machine Cycle 11

12 Control Unit (CU) According to IEEE the control unit is the parts that effect the retrieval of instruction in proper sequence, the interpretation of each instruction, and the application of the proper signals to the arithmetic unit and other parts in accordance with the interpretation. CU is the brain of the microprocessor. CU contains the microprogram (the entire instruction set). It coordinates and directs most of the operations in the computer. 12

13 Control Unit (CU) CU controls and interprets the execution of instructions, by following a sequence of actions that corresponds to fetch-execute instruction cycle (retrieve instructions from memory then movement of data or address from one part of the CPU to another). 13

14 Control Unit (CU) To determine which instruction to be executed, CU reads the contents of the program counter (PC)/ instruction pointer (IP). The instructions are then decoded by the Instruction Decoder in the CU. Instructions are executed sequentially CU has a Memory Management Unit to supervise the fetching of instructions and data from memory. The I/O interface is also part of the control unit. 14

15 Control Unit (CU) Instruction Decoder Is properly part of the CU. But the decoding of instructions is a separate and distinct phase of microprocessor operations. The microprocessor knows how to add, but does not know when to add and what to add. When an instruction is fetched from the memory, the instruction is then sent to the instruction decoder to be decoded or interpreted. Control signals will then be issued to perform the necessary operation. The interpretation process is called instruction decoding. 15

16 Arithmetic Logic Unit (ALU) ALU is the heart of the microprocessor. ALU performs arithmetic and logical operations on input data. It performs these operations as directed by the CU. Structure: Comparator compares the magnitude of two numbers placed in buffer registers. The comparator, used in conjunction with Status Register, will output the results of the comparison. Logic Registers Performs such logic operations as AND, OR, XOR, etc. 16

17 Arithmetic Logic Unit (ALU) Control of the ALU operation of ALU must be controlled. Accomplished through control leads that provides input path for control signals and facilitate the sequencing and operation of each individual block of circuits. Shifter A special function register. It will move the contents of a register one or more positions left or right. Can also perform a unique operation called rotate when used with status register. 17

18 Registers A single, permanent storage location within the CPU used for particular defined purpose. Used to hold binary value temporarily for Storage, Manipulation, and/or Simple calculations. The basic working components of the CPU. 18

19 Registers A register may hold: data being processed an instruction being executed a memory or I/O address to accessed keeps track of the status of the computer or conditions of calculations. 19

20 Registers Four primary operations by registers: Can be loaded with values from other locations (from other registers or memory location). Data can be added or subtracted. Data can be shifted or rotated right or left by one or more bits. Value of data in register can be tested for certain conditions (zeros, negative, etc) 20

21 Registers Instruction Register (IR) Holds the current instruction being executed. Program Counter Both a counter and a register. The address in the program counter register is always the address of the next instruction to be executed. When the current instruction is finished, the program counter generates an address and places it on the address bus. It then increments, that is, adds 1 to the address it just generated and puts the number in the counter register. 21

22 Registers Program Counter (cont) Again, when the current instruction is finished, it places the new address on the address bus and again adds 1 to the register. Therefore, the program counter continually generates sequential address. Memory Address Register (MAR) Holds the address of a memory location. 22

23 Registers Memory Data Register (MDR) Also known as Memory Buffer Register (MBR). Holds data value that is being stored to or retrieved from the memory location currently addressed by the memory address register. 23

24 Registers Status Register (Flags) Allow computers to keep track of special condition such as: Arithmetic carry and overflow Power failure, and Internal computer error. The Status register contains individual flags (1 bit for each flag) The control unit set (1) or reset (0) flags as a result of conditions that arise during the execution of instructions. 24

25 System Clock The system clock is a device that emits periodic sequence of pulses to control the timing of all computer operations. These pulses define machine cycles. During each machine cycle, some activity occurs, such as the execution of a microinstruction. The interval between corresponding edges of two consecutive pulses is called the clock cycle time. 25

26 System Clock The pace of the clock or the clock speed is measured by the number of ticks per second. Pulse frequencies are currently in the gigahertz range which corresponds to billions of ticks per second. Therefore the faster the clock speed, the more instructions the processor can execute per second. 26

27 CPU PROCESSING METHODS 27

28 CPU Processing Methods In this topic, you will be introduced to the different and interrelated CPU processing methods. The common goal is to increase the performance of the CPU. Among the methods are: Pipelining Superscalar CISC and RISC Multiprocessing 28

29 CPU Processing Methods Performance number of instructions executed in a given amount of time. To increase computer performance, these techniques are used: Separating the fetch unit / execute unit Overlapping the instruction cycle of instructions. Executing more than one instruction in a clock cycle. 29

30 CPU Processing Methods Separating the fetch unit/ execute unit Previously instruction cycles are executed one by one. A new instruction enters the instruction cycle after the previous instruction has completed execution. In the instruction cycle, two phases are involved fetch phase and execute phase. To increase performance, it is possible to separate the two phase and perform them concurrently. 30

31 CPU Processing Methods Fetch unit - retrieves and decodes the instructions Fetches the instructions in parallel Holds them in a buffer until it can be decoded and executed. How many instructions in a buffer? Size of instruction Width of memory bus Size of buffer 31

32 CPU Processing Methods Execute unit performs actual instruction execution Contains ALU and a portion of CU Identifies and controls the steps that comprise the execution part of the instruction. 32

33 CPU Processing Methods Instruction Fetch Unit Bus Interface Instruction Decode Unit Memory Addressing Unit Registers ALU Instruction Execution Unit 33

34 Pipelining A Pipelining is a technique used in advanced microprocessors where the microprocessor begins executing a second instruction before the first has been completed. That is, several instructions are in the pipeline simultaneously, each at a different processing stage. 34

35 Pipelining Computer processors can handle millions of instructions each second. Once one instruction is processed, the next one in line is processed, and so on. A pipeline allows multiple instructions to be processed at the same time. While one stage of an instruction is being processed, other instructions may be undergoing processing at a different stage. Without a pipeline, each instruction would have to wait for the previous one to finish before it could even be accessed. 35

36 Pipelining With pipelining, the processor begins fetching the second instruction before it completes the execution of the first instruction. This way, the processor does not have to wait for one instruction to complete before fetching the next. In computing, a pipeline is a set of data processing elements connected in series, so that the output of one element is the input of the next one. The elements of a pipeline are often executed in parallel or in time sliced fashion. 36

37 Pipelining The pipeline is divided into segments and each segment can execute its operation concurrently with the other segments. When a segment completes an operation, it passes the result to the next segment in the pipeline and fetches the next operation from the preceding segment. The final results of each instruction emerge at the end of the pipeline in rapid succession. 37

38 Pipelining 38

39 Pipelining It is not useful to pipe different types of instructions through a single pipeline different execution units are created based on general types of instructions: Load/store unit Integer arithmetic unit Floating point arithmetic unit Branch unit 39

40 Pipelining Pipeline hazards Situations that prevent the next instruction in the instruction stream from executing during its designated clock cycle. The instruction is said to be stalled. Effect stall following instructions too. No new instructions are fetched during the stall. 40

41 Pipelining Types of hazards: Structural hazard Control Hazard Data hazard 41

42 Pipelining Structural hazard attempt to use the same resource two different ways at a time. Eg: use the register for multiplication and division operation at the same time. 42

43 Pipelining Data hazard attempt to use data before it is ready Eg: the following instruction depends on the result of prior instruction in the pipeline. Control hazard attempt to make a decision before a condition is evaluated Eg: branch instructions 43

44 Pipelining How to overcome hazards? Instruction reordering separate dependent instructions so they are not executed one right after the other. Prediction, superscalar processing. 44

45 Superscalar It means processing more than one instruction per clock cycle. It is a standard feature in modern computer systems. Superscalar processing can increase the throughput by double or more. Separate fetch and execute cycles as much as possible Buffers for fetch and decode phases Parallel execution units 45

46 Scalar VS Superscalar 46

47 Superscalar Technical Issues Out-of-order processing Branch instruction processing Conflict of resources 47

48 Out of Order Processing Hazard / dependency later instruction depend on the result of earlier instruction. Data dependency later instruction completes ahead of the earlier one. Implication wrong order. Solution provide reservation station. 48

49 Out of Order Processing (cont.) Another solution search ahead for instructions. For instance, Intel x86: can search instructions ahead if necessary. 49

50 Branch Instruction Processing Flow / branch dependencies conditional branch instructions. Solution can be broken into 2 parts: optimize correct branch selection methods to prevent errors 50

51 Branch Instruction Processing (cont.) Speculative execution (prevent errors): separate bank of registers used to hold results from later instructions until previous instructions are complete. result transferred into actual register and memory locations. 51

52 Branch Instruction Processing (cont.) Optimization: maintain more than two pipelines predict the correct path based on program usage and performance branch history table 52

53 Conflict of Resources Conflict bet instructions that use the same registers Solution use the same bank of registers Bank of registers hold the results of speculative instructions until instruction complete Concept rename register / logical registers / register alias tables 53

54 Superscalar CPU Block Diagram 54

55 CPU Architecture CISC Complex Instruction Set Computer RISC Reduced Instruction Set Computer CISC vs. RISC Comparisons 55

56 CISC Architecture Examples Intel x86, IBM Z-Series Mainframes, older CPU architectures Characteristics Few general purpose registers Many addressing modes Large number of specialized, complex instructions Instructions are of varying sizes 56

57 Limitations of CISC Architecture Complex instructions are infrequently used by programmers and compilers Memory references, loads and stores, are slow and account for a significant fraction of all instructions Procedure and function calls are a major bottleneck Passing arguments Storing and retrieving values in registers 57

58 RISC (Reduced Instruction Set Computer) Attempts to produce more CPU power by eliminating major bottlenecks to instruction execution speed: Reducing number of data memory access by using registers more effectively. Simplifying the instruction set. 58

59 RISC (Reduced Instruction Set Computer) Features: Examples: Power PC, Sun Sparc, Motorola Limited and simple instruction set. Fixed length, fixed format instruction words Enable pipelining, parallel fetches and executions 59

60 RISC (Reduced Instruction Set Computer) Features: (cont.) Limited addressing modes. Reduce complicated hardware Register-oriented instruction set Reduce memory accesses Large bank of registers Reduce memory accesses Efficient procedure calls 60

61 CISC vs. RISC Processing 61

62 Circular Register Buffer 62

63 Circular Register Buffer - After Procedure Call 63

64 CISC vs. RISC Performance Comparison RISC Simpler instructions more instructions more memory accesses RISC more bus traffic and increased cache memory misses More registers would improve CISC performance but no space available for them Modern CISC and RISC architectures are becoming similar 64

65 Multiprocessing The use of more than 1 CPU to process instructions. Reasons for using multiprocessing: Increase the processing power of a system. Enables parallel processing programs can be divided into independent pieces and the different parts executed simultaneously on multiple processors. 65

66 Multiprocessing 66

67 Multiprocessing Since the execution speed of a CPU is directly related to the clock speed, equivalent processing power can be achieved at much lower clock speeds, reducing power consumption, heat and stress within the various computer components. Adding more CPUs is relatively inexpensive. If a CPU encounters a problem, other CPUs can continue instruction execution, increasing overall throughput. 67

68 Multiprocessing Two types: a) tightly coupled system b) loosely coupled system 68

69 Tightly Coupled System Identical access to programs, data, shared memory, I/O, etc. Easily extends multi-tasking, and redundant program execution Two ways to configure Master-slave multiprocessing Symmetrical multiprocessing (SMP) 69

70 Multiprocessing Typical multiprocessing system configuration 70

71 Multiprocessing - Master-slave Multiprocessing Master CPU Manages the system Controls all resources and scheduling Assigns tasks to slave CPUs 71

72 Multiprocessing - Master-slave Multiprocessing Advantages Simplicity Protection of system and data Disadvantages Master CPU becomes a bottleneck Reliability issues if master CPU fails entire system fails Applications Game, Finance, Economics, Biology, Physics 72

73 Multiprocessing Symmetrical Multiprocessing Each CPU has equal access to resources Each CPU determines what to run using a standard algorithm 73

74 Multiprocessing Symmetrical Multiprocessing Disadvantages Resource conflicts memory, i/o, etc. Complex implementation Advantages High reliability Fault tolerant support is straightforward Balanced workload 74

75 INSTRUCTION CYCLE 75

76 Instruction Cycle The microprocessor s main task is to execute instructions. The instruction cycle is therefore at the heart of understanding the function and operation of the microprocessor. The instruction cycle is composed of two main cycles, because both instructions and data are in memory. Fetch cycle Execute cycle. 76

77 Instruction Cycle Fetch cycle Find and Decode instruction, load from memory into register and signal ALU Execute cycle. Performs operation that instruction requires Move/transform data 77

78 Instruction Cycle Generally, a microprocessor carries out instructions in a three-step (or phase) process. It simply repeats the three-step operation with almost no variation, as long as power is applied to it. These three steps are called Fetch Decode Execute 78

79 Instruction Cycle Phase 1: Fetch Fetching, in a microprocessor, is the term used to indicate that the microprocessor is retrieving an instruction from memory. The microprocessor fetches the instructions from memory one at a time, and brings them into the instruction decoder register to be decoded. 79

80 Instruction Cycle Phase 2: Decode The decode phase of the cycle begins as soon as the instruction, in the form of an 8-bit byte, appears in the instruction decoder register. The decoding is done via PLA (Programmable Logic Array). The array will output the control signals necessary to carry out the instruction. The PLA is designed with microcode to recognize only those bit patterns contained in the instruction set. Upon recognition of a bit pattern the PLA or microcode then generates the internal and external control signals necessary to carry out the given instruction. 80

81 Instruction Cycle - Phase 3: Execute The execution phase begins as soon as the microcode outputs the control signal necessary to carry out the instruction. The length of time needed to complete the execution phase varies considerably with the type of instruction involved. Some instructions are several bytes long. Each byte is fetched and decoded one at a time. After each byte is decoded, the necessary control signals are executed. 81

82 Fetch-Execute Instruction Cycle Basis for every capability of a computer Ultimately the operation of a computer as a whole is defined by the primary operations that can be performed with registers to move data between registers to add or subtract data to a register to shift data within a register to test the value in a register for certain conditions such as negative, positive or zero. 82

83 Fetch-Execute Instruction Cycle Basically, the registers involved are: 1. General purpose (GP) registers or accumulator (A) : used to hold data values between instructions 2. Program counter (PC) : hold the address of the current instruction 3. Instruction register (IR) : hold the current instruction while it is being executed 4. Memory address register and memory data register (MAR & MDR) : used for accessing memory 83

84 Fetch-Execute Instruction Cycle To execute an instruction, 2 phases involve : 1. Fetched the instruction from memory address of the current instruction to be executed identified by the value in PC register this value transferred into MAR so that the computer can retrieve the instruction located at that address STEP 1 : PC MAR this will result in the instruction being transferred from the specified memory location to MDR that instruction is transferred to IR STEP 2 : MDR IR 84

85 Instruction Cycle Fetch Cycle 85

86 Instruction Cycle Execute Cycle This cycle is instruction dependent. The instructions can be categorized into the following four groups: CPU - Memory: Data may be transferred from memory to the CPU or from the CPU to memory. CPU - I/O: Data may be transferred from an I/O module to the CPU or from the CPU to an I/O module. 86

87 Instruction Cycle Execute Cycle Data Processing: The CPU may perform some arithmetic or logic operation on data via the arithmetic-logic unit (ALU). Control: An instruction may specify that the sequence of operation may be altered. For example, the program counter (PC) may be updated with a new memory address to reflect that the next instruction fetched, should be read from this new location. 87

88 Instruction Cycle Execute Cycle Remaining steps : to complete a LOAD instruction 2. Interpret the instruction and perform the action Address portion of the instruction is loaded in MAR STEP 3: IR[address] MAR Actual data is copied into the accumulator STEP 4: MDR A Program Counter incremented STEP 5: PC + 1 PC 88

89 LMC vs. CPU: Fetch and Execute Cycle 89

90 Fetch-Execute Cycle: LOAD 1. PC -> MAR Transfer the address from the PC to the MAR 2. MDR -> IR Transfer the instruction to the IR 3. IR(address) -> MAR Address portion of the instruction is loaded in MAR 4. MDR -> A Actual data are copied into the accumulator 5. PC + 1 -> PC Program Counter is incremented 90

91 Fetch-Execute Cycle: ADD 1. PC -> MAR Transfer the address from the PC to the MAR 2. MDR -> IR Transfer the instruction to the IR 3. IR(address) -> MAR Address portion of the instruction is loaded in MAR 4. A + MDR -> A Contents of MDR are added to contents of accumulator and the result is stored back into accumulator 5. PC + 1 -> PC Program Counter is incremented 91

92 Fetch-Execute Cycle: STORE 1. PC -> MAR Transfer the address from the PC to the MAR 2. MDR -> IR Transfer the instruction to the IR 3. IR(address) -> MAR Address portion of the instruction is loaded in MAR 4. A -> MDR* Accumulator copies data into MDR 5. PC + 1 -> PC Program Counter is incremented *Notice how Step #4 differs for LOAD and STORE 92

93 LMC Fetch-Execute SUBTRACT PC MAR MDR IR IR[addr] MAR A MDR A PC + 1 PC IN PC MAR MDR IR IOR A PC + 1 PC BRANCH PC MAR MDR IR IR[addr] PC OUT HALT PC MAR PC MAR MDR IR MDR IR A IOR PC + 1 PC BRANCH on Condition PC MAR MDR IR If condition false: PC + 1 PC If condition true: IR[addr] PC 93

94 Fetch-Execute Cycle Example Program Counter = 65 Value in Mem Location 65: 590 (LOAD 90) Value in Mem Location 66: 192 (ADD 92) Value in Mem Location 67: 390 (STORE 90) Value in Mem Location 90: 111 Value in Mem Location 92:

95 Explanation 1 st Instruction LOAD 90 PC -> MAR MAR now has 65 MDR -> IR IR contains the instruction: end of fetch IR [address] -> MAR MDR -> A MAR now has 90, the location of the data Move the value 111 from MDR to A PC + 1 -> PC PC now points to 66 95

96 Explanation 2 nd Instruction ADD 92 PC -> MAR MAR now has 66 MDR -> IR IR contains the instruction: end of fetch IR [address] -> MAR A + MDR -> A MAR now has 92, the location of the data 111 in Accumulator in MDR = 333 into Accumulator PC + 1 -> PC PC now points to 67 96

97 Explanation 3 rd Instruction STORE 90 PC -> MAR MAR now has 67 MDR -> IR IR contains the instruction: end of fetch IR [address] -> MAR MAR now holds 90 A -> MDR The value in A, 333 moves to memory location 90 PC + 1 -> PC PC now points to ready for next instruction 97

98 INSTRUCTION SETS AND TYPES 98

99 Instruction Sets and Types The instruction set is grouped into a number of categories: Data Movement (load, store) Most common, greatest flexibility Involve memory and registers Arithmetic Operators + - / * ^ Integers and floating point 99

100 Instruction Sets and Types Boolean Logic Often includes at least AND, XOR, and NOT Single operand manipulation instructions Negating, decrementing, incrementing, set to 0 Bit manipulation instructions Flags to test for conditions 100

101 Instruction Sets and Types Shift and rotate Logical shift zeros are shifted in to replace the bit spaces that have been vacated. Arithmetic shift multiply or divide by a power of 2. Program control Jumps, branch, CALL, RETURN Stack instructions Push, pop 101

102 Instruction Sets and Types Multiple data instructions Performs single operations on multiple pieces of data simultaneously. Multimedia apps I/O and machine control Privileged instructions. 102

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