Lecture 21: Parallelism ILP to Multicores. Parallel Processing 101
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1 Lecture 21: Parallelism ILP to Multicores S 10 L21 1 James C. Hoe Dept of ECE, CMU April 7, 2010 Announcements: Handouts: Lab 4 due this week Optional reading assignments below. The Microarchitecture of Superscalar Processors, Smith and Sohi, Proceedings of IEEE, 12/1995. (on Blackboard) The MIPS R10000 Superscalar Microprocessor, Yeager, IEEE Micro, 4/1996. (on Blackboard) Design Challenges of Technology Scaling, Shekhar Borkar, IEEE Micro, (on Blackboard) Parallel Processing 101 Assume you have N units of work and each unit of work takes 1 unit time on 1 processing element (PE) with 1 PE, it will take N unit time to complete the N units of work with p PEs, how long does it take to complete the same N units of work? Ideally, speedup is linear with p S 10 L21 2 runtime speedup runtime speedup= sequential runtime runtime parallel l N/p 1 p= p=
2 It may be linear, but..... S 10 L21 3 S p How could this be? Parallelization Overhead The cheapest algorithm may not be the most scalable, s.t., runtime parallel@p=1 l = K runtime sequential and K>1 and speedup = p/k K is known facetiously as the parallel slowdown Communications between PEs are not free a PE may spend extra instructions/time in the act of sending or receiving data a PE may spend extra time waiting for data to arrive from another PE a function of latency and bandwidth a PE may spend extra time waiting for another PE to get to a particular point of the computation (a.k.a. synchronization) S 10 L21 4
3 It could be worse S 10 L21 5 S limited scalability p May never get high speedup regardless of the number of PEs Parallelism Defined S 10 L21 6 T 1 (call it Work ): time to complete work with 1 PE x = a + b; y = b * 2 T (call llit Critical Pth ) Path ): z =(x y) * (x+y) time to complete work given infinite PEs T lower bounded by dataflow dependencies a b Average Parallelism: + *2 P avg = T 1 / T x y For a system with ihp PEs - + T p max{ T 1 /p, T } S p min{ p, T 1 /T } * When P avg >>p T p T 1 /p and S p p An app has to have parallelism to get speedup from parallel PEs!!
4 Amdahl s Law on Speedup A program is rarely completely parallelizable. Let s say a fraction f is parallelizable by a factor of p and the rest are not time sequential S 10 L21 7 (1 f) f time parallel (1 f) f/p time parallel = time sequential ( (1 f) + f/p ) S parallel = 1 / ( (1 f) + f/p ) If f is small p doesn t matter. An architect also cannot ignore the sequential performance of the (1 f) portion S 10 L21 8 ILP: the parallelism you already know
5 Going after IPC S 10 L21 9 Scalar Pipeline with Forwarding Operation Latency = 1 Peak IPC = 1 Instruction Level Parallelism = 1 tream instruction st cyc Superscalar Machines S 10 L21 10 Superscalar (Pipelined) Execution OL = 1 baseline cycles Peak IPC = N per baseline cycle ILP = N instru uction stream cyc Achieving full performance requires finding N independent instructions per cycle
6 ILP: Instruction Level Parallelism S 10 L21 11 ILP is a measure of the amount of inter dependencies between instructions Average ILP = T 1 / T = no. instruction / no. cyc required code1: ILP = 1 i.e. must execute serially code2: ILP = 3 ie i.e. can execute at the same time code1: r1 r2 + 1 r3 r1 / 17 r4 r0 - r3 code2: r1 r2 + 1 r3 r9 / 17 r4 r0 - r10 Removing False Dependencies S 10 L21 12 Anti and output dependencies are false dependencies r 3 r 1 op r 2 r 5 r 3 op r 4 r 3 r 6 op r 7 The dependence is on the register name rather than data Given infinite number of registers, anti and output dependencies can always be eliminated
7 Register Renaming: Example S 10 L21 13 Original r1 r2 / r3 r4 r1 * r5 r1 r3 + r6 r3 r1 r5 ILP=1 Renamed r1 r2 / r3 r4 r1 * r5 r8 r3 + r6 r9 r8 r5 ILP=2 Hardware Register Renaming S 10 L21 14 ISA name e.g. r12 Rename Table rename t56 Rename Register File (t0... t63) maintain bindings from ISA reg. names to rename registers When issuing an instruction that updates rd : allocate an unused rename register tx recording binding from rd to tx When to remove a binding? When to de allocate a rename register? r1 r2 / r3 r4 r1 * r5 r1 r3 + r6
8 Out of Order Execution S 10 L21 15 Renaming eliminates WAW and WAR In a RAW dependent instruction pair, the reader must wait for the result from the writer How to get more ILP? r1 r2 + 1 r3 r1 / 17 r4 r0 r3 r11 r r13 r19 / 17 r14 r0 r20 ILP=1 ILP=2 Dataflow Execution Ordering S 10 L21 16 Maintain a window of many pending instructions (a.k.a. Issue Buffer) Dispatch instructions out of order find instructions whose operands are available give preference to older instructions A completing instruction may enable other pending instructions (RAW) Need to remember how to put things back in order (Reorder Buffer)
9 Instruction Reorder Buffer S 10 L21 17 At today s clock frequency, on a memory load a cache hit (best case) takes 4~7 cyc a L1 cache miss takes a few 10s of cycles an off chip cache miss takes a few 100s of cycles ROB is a program order instruction bookkeeping structure instructions must enter and leave in program order holds 10s to 100s of in flight instructions in various stages of execution re sorts all instructions on exit to appear to complete in program order supports precise exception for any in flight instruction Speculative Execution S 10 L21 18 Multiple levels of branch predictions are needed to fetch 100 s instructions beyond the commit point Instructions after a predicted branch are speculative must undo their effects in case of misprediction Maintain separate copies of In order State: a check point state up to just before the first speculated instruction Speculative State: include all state changes after checkpoint,,possibly multiple predicted branches Commit admit known to be good speculative state changes into the in order state Rewind discard all, or part of, the speculative state
10 MIPS R10000 S 10 L21 19 map table pre decoded I cache 4xinst decode (16R4W) map table 8x4 entries Active List (ROB) 16 entry int. Q (R.S.) 64 entry Int GPR 7R3W 16 entry FP. Q (R.S.) 64 entry FPR 5R3W ALU1 ALU2 LD/ST ALU1 ALU2 Read [Yeager 1996, IEEE Micro] if you are really interested State of the Art S 10 L21 20 cores/threads AMD Opteron 8360SE 4x1 Intel Xeon X7460 6x1 Intel Itanium x2 IBM P5 2x2 IBM P6 2x2 Fijitsu SPARC 7 4x2 SUN T2 8x8 Clock (GHz) Issue Rate 3 (x86) 4 (rop) Pipeline depth 12/ /12 Out of order 72(rop) 96(rop) inorder 200 limited 64 inorder on chip$ (MB) Trans (10 6 ) Power (W) > SPECint 2006 per core/total 14.4/170 SPECfp /156 per core/total 22/274 22/ / / / / / / / /1861 /142 /111 Microprocessor Report, Oct 2008
11 S 10 L21 21 Moving beyond ILP Moore s Law S 10 L21 22 The number of transistors that can be economically integrated shall double every 24 months [
12 Transistor Scaling S 10 L21 23 gate length [ commercial products are at 40~45nm today distance between silicon atoms ~ 500 pm Basic Scaling Theory S 10 L21 24 Planned scaling occurs in discrete nodes where each is ~0.7x of the previous in linear dimension e.g., 90nm, 65nm, 45nm, 32nm, 22nm, 15nm, The End Take the same design, reducing the linear dimensions by 0.7x (aka gate shrink ) leads to (ideally) die area = 0.5x delay = 0.7x, frequency=1.43x capacitance = 0.7x Vdd=0.7x (if constant field) or Vdd=1x (if constant voltage) power = C V 2 f = 0.5x (if constant field) BUT power = 1x (if constant voltage) Take the same area, then transistor count = 2x power = 1x (constant field), power = 2x (constant voltage) [refer to the Shekhar article for the more complete story]
13 The Other Moore s Law S 10 L21 25 This part is for later This is not all scaling driven. Without the extensive instruction reordering and speculation in modern pipelines, we would not be able to run the CPU at multi GHz against 50ns DRAMs Moore s Law Performance S 10 L21 26 According to scaling theory, we should complexity: 1x transistors at 1.43x frequency x performance at x complexity: 2x transistors at 1.43x frequency 2.8x performance at constant power Instead, we have been getting (for high perf CPUs) ~2x transistors t ~2x frequency (note: faster than scaling would give us) all together we get about ~2x performance at ~2x power
14 Performance (In)efficiency To hit the expected performance target on singlethread microprocessors we had been pushing frequency harder by deepening pipelines we used the 2x transistors to build more complicated microarchitectures so the fast/deep pipelines don t stall (i.e., caches, BP, superscalar, out of order) The consequence of performance inefficiency is S 10 L21 27 limit of economical PC cooling [ITRS] Intel P4 Tehas 150W (Guess what happened next) [from Shekhar Borkar, IEEE Micro, July 1999] The Other Moore s Law S 10 L21 28
15 Turning the Corner S 10 L21 29 Much less energy and power to do the same work slowly Suppose at full frequency Runtime = Work /c perf Energy = (c switch + c leakage / c perf ) Work Power = c switch c perf + c leakage c switch is a constant for energy per unit work done c perf is a constant for work per unit time c leakage is the leakage power When frequency is reduced by a fraction s freq, the supply voltage can also be reduced by a fraction s voltage Runtime = Work / (c perf s freq ) Energy = (c switch s voltage2 + c leakage s ~2.5 voltage / c perf s freq ) Work Power = c switch s voltage2 c perf s freq + c leakage s ~2.5 voltage Disclaimer: this is good enough for 447. Don t try to pass this off in any of the circuits courses Voltage Frequency Scaling Intel P4 660 with Enhanced SpeedStep S 10 L21 30 What if you did the same work on 2 cores at half speed?
16 Parallelization vs. Energy/Power S 10 L21 31 Ideal parallelization by N cores Runtime speedup by N = W / (c perf N) Energy speedup by N = (c switch + c leakage / c perf ) W Power speedup by N = N (c switch c perf + c leakage ) Alternatively, we can trade N speedup for power and energy reduction by s freq =1/N, if s voltage s freq Runtime iso perf = W / c perf Energy iso perf = (c switch / N 2 + c leakage / (c perf N ~1.5 )) W Power iso perf = c switch c perf / N 2 + c leakage / N ~1.5 Disclaimer: this is good enough for 447. Don t try to pass this off in any of the circuits courses On to Multicores and Manycores S 10 L21 32 Core Core Core $ $ $ Fat Interconnect Big L2 Bigger L3 We are here because we need to compute faster while using less energy per operation... and the boss says to stay on the Moore s Law
17 What is to come? S 10 L21 33 We (actually Intel, et al.) know how to pack more cores on a die to stay on Moore s law in terms of aggregate or throughput performance life is good if your N units of work (on slide 2) is N independent programs just run them what if your N units of work is N operations of the same program? rewrite a parallel program what if your N units of work is N sequentially dependent operations of the same program??? Will we (the users) run out of parallelism in our workloads to make use of the many many cores?
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